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abi011020
/
eda_verilog_code_100k

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3
84.9M
['module Four_to_1_4_bit_mux(O,D,S); //declares module\\\\n\\\\n\\\\tinput wire [15:0]D; // four data inputs\\\\n\\\\tinput wire [1:0]S; // two selector inputs\\\\n\\\\toutput wire [3:0]O; //define output data wire\\\\n\\\\t\\\\n\\\\tFour_to_1_1_bit_mux inst0(O[0],D[3:0],S); //calls the four to 1, 1 bit module from earlier.\\\\n\\\\tFour_to_1_1_bit_mux inst1(O[1],D[7:4],S); //calls the four to 1, 1 bit module from earlier.\\\\n\\\\tFour_to_1_1_bit_mux inst2(O[2],D[11:8],S); //calls the four to 1, 1 bit module from earlier.\\\\n\\\\tFour_to_1_1_bit_mux inst3(O[3],D[15:12],S); //calls the four to 1, 1 bit module from earlier.\\\\n\\\\t//using four of the four to 1, 1 bit functions from earlier, we can create a 4 to 1, 4 bits multiplexer.\\\\n\\\\t\\\\nendmodule']
['module ex6_top(\\\\n\\\\tCLOCK_50,\\\\n\\\\tKEY,\\\\n\\\\tHEX0,\\\\n\\\\tHEX1,\\\\n\\\\tHEX2,\\\\n\\\\tHEX3,\\\\n\\\\tHEX4\\\\n);\\\\n\\\\n\\\\n\\\\tinput CLOCK_50;\\\\n\\\\t\\\\n\\\\tinput [1:0] KEY;\\\\n\\\\t\\\\n\\\\toutput[6:0] HEX0;\\\\n\\\\toutput[6:0] HEX1;\\\\n\\\\toutput[6:0] HEX2;\\\\n\\\\toutput[6:0] HEX3;\\\\n\\\\toutput[6:0] HEX4;\\\\n\\\\t\\\\n\\\\twire [15:0] count_out;\\\\n\\\\t\\\\n\\\\twire [3:0] BCD0;\\\\n\\\\twire [3:0] BCD1;\\\\n\\\\twire [3:0] BCD2;\\\\n\\\\twire [3:0] BCD3;\\\\n\\\\twire [3:0] BCD4;\\\\n\\\\twire\\\\tclock_in;\\\\n\\\\t\\\\n\\\\ttick divider(CLOCK_50, clock_in);\\\\n\\\\t\\\\n\\\\t\\\\n\\\\t\\\\n\\\\tcounter_16 counter (CLOCK_50, (!KEY[0] & clock_in), !KEY[1], count_out);\\\\n\\\\t\\\\n\\\\tbin2bcd_16 wtfisbin2bcd (count_out, BCD0, BCD1, BCD2, BCD3, BCD4);\\\\n\\\\t\\\\n\\\\thex_to_7seg seg0 (HEX0, BCD0);\\\\n\\\\thex_to_7seg seg1 (HEX1, BCD1);\\\\n\\\\thex_to_7seg seg2 (HEX2, BCD2);\\\\n\\\\thex_to_7seg seg3 (HEX3, BCD3);\\\\n\\\\thex_to_7seg seg4 (HEX4, BCD4);\\\\n\\\\t\\\\t\\\\n\\\\t\\\\nendmodule']
["module Decryption(input [127:0] in, input [255:0] Key, input [5:0] counter, input clk, output [127:0] out, input [5:0] maxRound);\\\\n\\\\nwire [127:0] inRound;\\\\nwire [127:0] inMix;\\\\nwire [127:0] outMix;\\\\nwire [127:0] inShift;\\\\nwire [127:0] inSub;\\\\nwire [127:0] outSub;\\\\nreg [127:0] stored;\\\\nwire [1407:0] full_key128;\\\\nwire [1663:0] full_key192;\\\\nwire [1919:0] full_key256;\\\\nwire [127:0] currentKey;\\\\n\\\\nKeyExpansion #(10,4)kr1(Key[255 -: 128] , full_key128);\\\\nKeyExpansion #(12,6)kr2(Key[255 -: 192] , full_key192);\\\\nKeyExpansion #(14,8)kr3(Key , full_key256);\\\\n\\\\nassign inRound = (counter == maxRound)? in : stored;\\\\nassign inShift = (counter == maxRound)? inMix : outMix;\\\\nassign out = (counter == maxRound)? in : ((counter == (maxRound + maxRound - 6'd1))? outMix : inMix);\\\\nassign currentKey = (maxRound == 6'd10)? full_key128[((counter - 6'd10)*(-128) + 1407) -: 128] : ((maxRound == 6'd12)? full_key192[((counter - 6'd12)*(-128) + 1663) -: 128] : full_key256[((counter - 6'd14)*(-128) + 1919) -: 128]);\\\\n\\\\nAddRoundKey op1 (inRound, inMix, currentKey);\\\\nInv_MixColumns op2 (inMix, outMix);\\\\nInvShiftRows op3 (inShift, inSub);\\\\nInvSubBytes op4 (inSub, outSub);\\\\n\\\\nalways@(posedge clk) begin\\\\n\\\\tif(counter < maxRound + maxRound)\\\\n\\\\t\\\\tstored <= outSub;\\\\nend\\\\n\\\\nendmodule"]
["module test(\\\\n output reg [7:0] D_R, D_G, D_B,\\\\n output reg [3:0] COMM,\\\\n output reg [1:0] COMM_CLK,\\\\n output reg [5:0] life,\\\\n output reg [6:0] d7_1,\\\\n input CLK, left, right,reset);\\\\n \\\\n segment7 S0(bcd_s, A0,B0,C0,D0,E0,F0,G0);\\\\n segment7 S1(bcd_m, A1,B1,C1,D1,E1,F1,G1);\\\\n divfreq F4(CLK,CLK_div);\\\\n divfreq1 div1(CLK, CLK_time);\\\\n divmove F6(CLK,CLK_move);\\\\n divmove01 F2(CLK,CLK_move01);\\\\n divmove02 F3(CLK,CLK_move02);\\\\n \\\\n \\\\n reg [3:0] bcd_s,bcd_m;\\\\n reg [6:0] seg1, seg2; \\\\n reg LEFT,RIGHT;\\\\n byte pos,count,count1;\\\\n bit[2:0] cnt;\\\\n integer a,b,touch;\\\\n reg [7:0] plate[7:0];\\\\n reg [7:0] people[7:0];\\\\n reg [7:0] blueobj[7:0];\\\\n reg [2:0] random01, random02, r, r1;\\\\n \\\\n reg [7:0] win [7:0]; \\\\n reg [7:0] over [7:0];\\\\n \\\\n initial\\\\n begin\\\\n\\\\t\\\\tbcd_m = 0;\\\\n\\\\t\\\\tbcd_s = 0;\\\\n\\\\t\\\\tcnt=0;\\\\n\\\\t\\\\ttouch=6;\\\\n\\\\t\\\\tlife=6'b111111;\\\\n\\\\t\\\\tD_R=8'b11111111;\\\\n\\\\t\\\\tD_G=8'b11111111;\\\\n\\\\t\\\\tD_B=8'b11111111;\\\\n\\\\t\\\\tCOMM=4'b1000;\\\\n\\\\t\\\\trandom01 = (5*random01 + 3)%16;\\\\n\\\\t\\\\tr = random01 % 8;\\\\n\\\\t\\\\trandom02 = (5*(random02+1) + 3)%16;\\\\n\\\\t\\\\tr1 = random02 % 8;\\\\n\\\\t\\\\ta=0;\\\\n\\\\t\\\\tb=0;\\\\n\\\\t\\\\tcount1=1;\\\\n\\\\t\\\\tover[0]= 8'b00111100;\\\\n\\\\t\\\\tover[1]= 8'b00011000;\\\\n\\\\t\\\\tover[2]= 8'b10000001;\\\\n\\\\t\\\\tover[3]= 8'b11000011;\\\\n\\\\t\\\\tover[4]= 8'b11000011;\\\\n\\\\t\\\\tover[5]= 8'b10000001;\\\\n\\\\t\\\\tover[6]= 8'b00011000;\\\\n\\\\t\\\\tover[7]= 8'b00111100;\\\\n\\\\t\\\\twin[0]= 8'b11000011;\\\\n\\\\t\\\\twin[1]= 8'b10000001;\\\\n\\\\t\\\\twin[2]= 8'b00111100;\\\\n\\\\t\\\\twin[3]= 8'b00111100;\\\\n\\\\t\\\\twin[4]= 8'b00111100;\\\\n\\\\t\\\\twin[5]= 8'b00111100;\\\\n\\\\t\\\\twin[6]= 8'b10000001;\\\\n\\\\t\\\\twin[7]= 8'b11000011;\\\\n\\\\t\\\\tpos=3;\\\\t//init position people\\\\t\\\\n\\\\t\\\\tplate[0]= 8'b11111111;\\\\n\\\\t\\\\tplate[1]= 8'b11111111;\\\\n\\\\t\\\\tplate[2]= 8'b11111111;\\\\n\\\\t\\\\tplate[3]= 8'b11111111;\\\\n\\\\t\\\\tplate[4]= 8'b11111111;\\\\n\\\\t\\\\tplate[5]= 8'b11111111;\\\\n\\\\t\\\\tplate[6]= 8'b11111111;\\\\n\\\\t\\\\tplate[7]= 8'b11111111;\\\\n\\\\t\\\\tblueobj[0]= 8'b11111111;\\\\n\\\\t\\\\tblueobj[1]= 8'b11111111;\\\\n\\\\t\\\\tblueobj[2]= 8'b11111111;\\\\n\\\\t\\\\tblueobj[3]= 8'b11111111;\\\\n\\\\t\\\\tblueobj[4]= 8'b11111111;\\\\n\\\\t\\\\tblueobj[5]= 8'b11111111;\\\\n\\\\t\\\\tblueobj[6]= 8'b11111111;\\\\n\\\\t\\\\tblueobj[7]= 8'b11111111;\\\\n\\\\t\\\\tpeople[0]= 8'b11111111;\\\\n\\\\t\\\\tpeople[1]= 8'b11111111;\\\\n\\\\t\\\\tpeople[2]= 8'b01111111;\\\\n\\\\t\\\\tpeople[3]= 8'b01111111;\\\\n\\\\t\\\\tpeople[4]= 8'b01111111;\\\\n\\\\t\\\\tpeople[5]= 8'b11111111;\\\\n\\\\t\\\\tpeople[6]= 8'b11111111;\\\\n\\\\t\\\\tpeople[7]= 8'b11111111;\\\\n end\\\\n //7\\\\u6bb5\\\\u986f\\\\u793a\\\\u5668\\\\u7684\\\\u8996\\\\u89ba\\\\u66ab\\\\u7559\\\\n\\\\talways@(posedge CLK_div)\\\\n\\\\tbegin\\\\n\\\\t\\\\tseg1[0] = A0;\\\\n\\\\t\\\\tseg1[1] = B0;\\\\n\\\\t\\\\tseg1[2] = C0;\\\\n\\\\t\\\\tseg1[3] = D0;\\\\n\\\\t\\\\tseg1[4] = E0;\\\\n\\\\t\\\\tseg1[5] = F0;\\\\n\\\\t\\\\tseg1[6] = G0;\\\\n\\\\t\\\\t\\\\n\\\\t\\\\tseg2[0] = A1;\\\\n\\\\t\\\\tseg2[1] = B1;\\\\n\\\\t\\\\tseg2[2] = C1;\\\\n\\\\t\\\\tseg2[3] = D1;\\\\n\\\\t\\\\tseg2[4] = E1;\\\\n\\\\t\\\\tseg2[5] = F1;\\\\n\\\\t\\\\tseg2[6] = G1;\\\\n\\\\t\\\\t\\\\n\\\\t\\\\tif(count1 == 0)\\\\n\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\td7_1 <= seg1;\\\\n\\\\t\\\\t\\\\t\\\\tCOMM_CLK[1] <= 1'b1;\\\\n\\\\t\\\\t\\\\t\\\\tCOMM_CLK[0] <= 1'b0;\\\\n\\\\t\\\\t\\\\t\\\\tcount1 <= 1'b1;\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\telse if(count1 == 1)\\\\n\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\td7_1 <= seg2;\\\\n\\\\t\\\\t\\\\t\\\\tCOMM_CLK[1] <= 1'b0;\\\\n\\\\t\\\\t\\\\t\\\\tCOMM_CLK[0] <= 1'b1;\\\\n\\\\t\\\\t\\\\t\\\\tcount1 <= 1'b0;\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\tend\\\\n\\\\t//\\\\u8a08\\\\u6642&\\\\u9032\\\\u4f4d\\\\t\\\\n\\\\talways@(posedge CLK_move01, posedge reset)\\\\n\\\\tbegin\\\\n\\\\t\\\\tif(reset)\\\\n\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\ttouch=6;\\\\n\\\\t\\\\t\\\\t\\\\tbcd_m = 3'b0;\\\\n\\\\t\\\\t\\\\t\\\\tbcd_s = 4'b0;\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\telse\\\\n\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t//touch\\\\n\\\\t\\\\t\\\\t\\\\tif(touch>0)\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tif( people[r][7]==1'b1 && blueobj[r][7]==1'b0)\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\ttouch=touch-1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tif(people[r][7]==1'b0 && blueobj[r][7]==1'b0)\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tbcd_s <= bcd_s + 1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tif(bcd_s >= 9)\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tbcd_s <= 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tbcd_m <= bcd_m + 1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tend\\\\t\\\\t\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tif(bcd_m >= 9) bcd_m <= 0;\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\tend\\\\n\\\\n\\\\talways@(posedge CLK_move01)\\\\n\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\tif(reset==1)\\\\n\\\\t\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\ta=0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tblueobj[0]= 8'b11111111;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tblueobj[1]= 8'b11111111;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tblueobj[2]= 8'b11111111;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tblueobj[3]= 8'b11111111;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tblueobj[4]= 8'b11111111;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tblueobj[5]= 8'b11111111;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tblueobj[6]= 8'b11111111;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tblueobj[7]= 8'b11111111;\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t// fall obj01\\\\n\\\\t\\\\t\\\\tif(touch>0 && bcd_m < 2)\\\\n\\\\t\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tif(a == 0)\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\trandom01 = (5*random01 + 3)%16;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tr = random01 % 8;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tblueobj[r][a] = 1'b0;\\\\t\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\ta = a+1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t\\\\t\\\\telse if (a > 0 && a <= 7)\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tblueobj[r][a-1] = 1'b1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tblueobj[r][a] = 1'b0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\ta = a+1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t\\\\t\\\\telse if(a == 8) \\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tblueobj[r][a-1] = 1'b1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\ta = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\tend\\\\n\\\\t/*\\\\n\\\\talways@(posedge CLK_move02)\\\\n\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\tif(reset==1)\\\\n\\\\t\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tb = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tplate[0] = 8'b11111111;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tplate[1] = 8'b11111111;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tplate[2] = 8'b11111111;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tplate[3] = 8'b11111111;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tplate[4] = 8'b11111111;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tplate[5] = 8'b11111111;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tplate[6] = 8'b11111111;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tplate[7] = 8'b11111111;\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t//fall obj02\\\\n\\\\t\\\\t\\\\tif(b == 0)\\\\n\\\\t\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\trandom02 = (5*(random01+1) + 3)%16;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tr1 = random02 % 8;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tplate[r1][b] = 1'b0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tb = b+1;\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\telse if (b > 0 && b <= 7)\\\\n\\\\t\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tplate[r1][b-1] = 1'b1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tplate[r1][b] = 1'b0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tb = b+1;\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\telse if(b == 8) \\\\n\\\\t\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tplate[r1][b-1] = 1'b1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tb = 0;\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\tend*/\\\\n\\\\talways@(posedge CLK_move)\\\\n\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\tRIGHT = right;\\\\n\\\\t\\\\t\\\\tLEFT = left;\\\\n\\\\t\\\\t\\\\tif(reset==1)\\\\n\\\\t\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tpos=2;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tpeople[0] = 8'b11111111;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tpeople[1] = 8'b11111111;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tpeople[2] = 8'b01111111;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tpeople[3] = 8'b01111111;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tpeople[4] = 8'b01111111;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tpeople[5] = 8'b11111111;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tpeople[6] = 8'b11111111;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tpeople[7] = 8'b11111111;\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t\\\\t//----------------------------------------------\\\\n\\\\t\\\\t\\\\t\\\\t//move people\\\\n\\\\t\\\\t\\\\t\\\\tif(LEFT==1 && pos!=0)\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tpos=pos-1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tpeople[pos][7]=1'b0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tpeople[pos+1][7]=1'b0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tpeople[pos+2][7]=1'b0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tpeople[pos+3][7]=1'b1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t\\\\tif(RIGHT==1 && pos!=5)\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tpos=pos+1;\\\\t\\\\t\\\\t\\\\t\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tpeople[pos-1][7]=1'b1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tpeople[pos][7]=1'b0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tpeople[pos+1][7]=1'b0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tpeople[pos+2][7]=1'b0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\tend\\\\n\\\\t\\\\n\\\\t\\\\n\\\\talways @(posedge CLK_div)\\\\n\\\\t\\\\tbegin \\\\n\\\\t\\\\t\\\\tif(cnt>=7)\\\\n\\\\t\\\\t\\\\t\\\\tcnt=0;\\\\n\\\\t\\\\t\\\\telse\\\\n\\\\t\\\\t\\\\t\\\\tcnt = cnt +1;\\\\n\\\\t\\\\t\\\\tCOMM={1'b1,cnt};\\\\n\\\\t\\\\t\\\\tif(touch>0)\\\\n\\\\t\\\\t\\\\t\\\\tif(bcd_m < 2)\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tD_G<=plate[cnt];\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tD_R<=people[cnt];\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tD_B<=blueobj[cnt];\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tif(touch==6)\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tlife=6'b111111;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\telse if(touch==5)\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tlife=6'b111110;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\telse if(touch==4)\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tlife=6'b111100;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\telse if(touch==3)\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tlife=6'b111000;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\telse if(touch==2)\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tlife=6'b110000;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\telse if(touch==1)\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tlife=6'b100000;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t\\\\telse\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tD_R<=win[cnt];\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tD_B<=8'b11111111;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\telse if(touch==0)\\\\n\\\\t\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tlife=6'b000000;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tD_R<=over[cnt];\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tD_B<=8'b11111111;\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\tend\\\\nendmodule", "module divfreq(input CLK, output reg CLK_div); \\\\nreg [24:0] Count; \\\\nalways @(posedge CLK) \\\\n\\\\tbegin \\\\n\\\\t\\\\tif(Count > 50000) \\\\n\\\\t\\\\tbegin \\\\n\\\\t\\\\t\\\\tCount <= 25'b0; \\\\n\\\\t\\\\t\\\\tCLK_div <= ~CLK_div; \\\\n\\\\t\\\\tend \\\\n\\\\t\\\\telse \\\\n\\\\t\\\\t\\\\tCount <= Count + 1'b1; \\\\n\\\\tend \\\\nendmodule", "module divmove(input CLK, output reg CLK_div); \\\\nreg [24:0] Count; \\\\nalways @(posedge CLK) \\\\n\\\\tbegin \\\\n\\\\t\\\\tif(Count > 3500000) \\\\n\\\\t\\\\tbegin \\\\n\\\\t\\\\t\\\\tCount <= 25'b0; \\\\n\\\\t\\\\t\\\\tCLK_div <= ~CLK_div; \\\\n\\\\t\\\\tend \\\\n\\\\t\\\\telse \\\\n\\\\t\\\\t\\\\tCount <= Count + 1'b1; \\\\n\\\\tend \\\\nendmodule", "module divmove01(input CLK, output reg CLK_div); \\\\nreg [24:0] Count; \\\\nalways @(posedge CLK) \\\\n\\\\tbegin \\\\n\\\\t\\\\tif(Count > 3500000) \\\\n\\\\t\\\\tbegin \\\\n\\\\t\\\\t\\\\tCount <= 25'b0; \\\\n\\\\t\\\\t\\\\tCLK_div <= ~CLK_div; \\\\n\\\\t\\\\tend \\\\n\\\\t\\\\telse \\\\n\\\\t\\\\t\\\\tCount <= Count + 1'b1; \\\\n\\\\tend \\\\nendmodule", "module divmove02(input CLK, output reg CLK_div); \\\\nreg [24:0] Count; \\\\nalways @(posedge CLK) \\\\n\\\\tbegin \\\\n\\\\t\\\\tif(Count > 3500000) \\\\n\\\\t\\\\tbegin \\\\n\\\\t\\\\t\\\\tCount <= 25'b0; \\\\n\\\\t\\\\t\\\\tCLK_div <= ~CLK_div; \\\\n\\\\t\\\\tend \\\\n\\\\t\\\\telse \\\\n\\\\t\\\\t\\\\tCount <= Count + 1'b1; \\\\n\\\\tend \\\\nendmodule", "module divfreq1(input CLK, output reg CLK_time);\\\\n reg [25:0] Count;\\\\n initial\\\\n begin\\\\n CLK_time = 0;\\\\n\\\\t end\\\\t\\\\n\\\\t\\\\t\\\\n always @(posedge CLK)\\\\n begin\\\\n if(Count > 25000000)\\\\n begin\\\\n Count <= 25'b0;\\\\n CLK_time <= ~CLK_time;\\\\n end\\\\n else\\\\n Count <= Count + 1'b1;\\\\n end\\\\nendmodule", 'module segment7(input [0:3] a, output A,B,C,D,E,F,G);\\\\n\\\\tassign A = ~(a[0]&~a[1]&~a[2] | ~a[0]&a[2] | ~a[1]&~a[2]&~a[3] | ~a[0]&a[1]&a[3]),\\\\n\\\\t B = ~(~a[0]&~a[1] | ~a[1]&~a[2] | ~a[0]&~a[2]&~a[3] | ~a[0]&a[2]&a[3]),\\\\n\\\\t\\\\t\\\\t C = ~(~a[0]&a[1] | ~a[1]&~a[2] | ~a[0]&a[3]),\\\\n\\\\t\\\\t\\\\t D = ~(a[0]&~a[1]&~a[2] | ~a[0]&~a[1]&a[2] | ~a[0]&a[2]&~a[3] | ~a[0]&a[1]&~a[2]&a[3] | ~a[1]&~a[2]&~a[3]),\\\\n\\\\t\\\\t\\\\t E = ~(~a[1]&~a[2]&~a[3] | ~a[0]&a[2]&~a[3]),\\\\n\\\\t\\\\t\\\\t F = ~(~a[0]&a[1]&~a[2] | ~a[0]&a[1]&~a[3] | a[0]&~a[1]&~a[2] | ~a[1]&~a[2]&~a[3]),\\\\n\\\\t\\\\t\\\\t G = ~(a[0]&~a[1]&~a[2] | ~a[0]&~a[1]&a[2] | ~a[0]&a[1]&~a[2] | ~a[0]&a[2]&~a[3]);\\\\n\\\\t\\\\t\\\\t \\\\nendmodule']
['module part2 (SW, HEX0, HEX1, HEX2, HEX3);\\\\n input [17:0] SW;\\\\n output [0:6] HEX0, HEX1, HEX2, HEX3;\\\\n\\\\n wire z;\\\\n wire [3:0] M, A;\\\\n assign A[3] = 0;\\\\n\\\\n comparator C0 (SW[3:0], z);\\\\n circuitA A0 (SW[3:0], A[2:0]);\\\\n mux_4bit_2to1 M0 (z, SW[3:0], A, M);\\\\n circuitB B0 (z, HEX1);\\\\n b2d_7seg S0 (M, HEX0);\\\\nendmodule', 'module b2d_7seg (X, SSD);\\\\n input [3:0] X;\\\\n output [0:6] SSD;\\\\n\\\\n assign SSD[0] = ((~X[3] & ~X[2] & ~X[1] & X[0]) | (~X[3] & X[2] & ~X[1] & ~X[0]));\\\\n assign SSD[1] = ((~X[3] & X[2] & ~X[1] & X[0]) | (~X[3] & X[2] & X[1] & ~X[0]));\\\\n assign SSD[2] = (~X[3] & ~X[2] & X[1] & ~X[0]);\\\\n assign SSD[3] = ((~X[3] & ~X[2] & ~X[1] & X[0]) | (~X[3] & X[2] & ~X[1] & ~X[0]) | (~X[3] & X[2] & X[1] & X[0]) | (X[3] & ~X[2] & ~X[1] & X[0]));\\\\n assign SSD[4] = ~((~X[2] & ~X[0]) | (X[1] & ~X[0]));\\\\n assign SSD[5] = ((~X[3] & ~X[2] & ~X[1] & X[0]) | (~X[3] & ~X[2] & X[1] & ~X[0]) | (~X[3] & ~X[2] & X[1] & X[0]) | (~X[3] & X[2] & X[1] & X[0]));\\\\n assign SSD[6] = ((~X[3] & ~X[2] & ~X[1] & X[0]) | (~X[3] & ~X[2] & ~X[1] & ~X[0]) | (~X[3] & X[2] & X[1] & X[0]));\\\\nendmodule', 'module comparator (V, z);\\\\n input [3:0] V;\\\\n output z;\\\\n\\\\n assign z = (V[3] & (V[2] | V[1]));\\\\nendmodule', 'module circuitA (V, A);\\\\n input [2:0] V;\\\\n output [2:0] A;\\\\n\\\\n assign A[0] = V[0];\\\\n assign A[1] = ~V[1];\\\\n assign A[2] = (V[2] & V[1]);\\\\nendmodule', "module circuitB (z, SSD);\\\\n input z;\\\\n output [0:6] SSD;\\\\n\\\\n assign SSD[0] = z;\\\\n assign SSD[1:2] = 2'b00;\\\\n assign SSD[3:5] = {3{z}};\\\\n assign SSD[6] = 1;\\\\nendmodule", 'module mux_4bit_2to1 (s, U, V, M);\\\\n // if ~s, send U\\\\n input s;\\\\n input [3:0] U, V;\\\\n output [3:0] M;\\\\n\\\\n assign M = ({4{~s}} & U) | ({4{s}} & V);\\\\nendmodule']
['module ALU16Bit(a, b, cin, less, op, result, cout, set, zero, g, p, overflow);\\\\n\\\\tinput [15:0] a, b;\\\\n\\\\tinput cin, less;\\\\n\\\\tinput [2:0] op;\\\\n\\\\toutput [15:0] result;\\\\n\\\\toutput cout, set, zero, g, p, overflow;\\\\n\\\\t\\\\n\\\\twire g0, g1, g2, g3, p0, p1, p2, p3;\\\\n\\\\t\\\\n\\\\twire dud_0,dud_1,dud_2,dud_3,dud_4,dud_5,dud_6,dud_7,dud_8,dud_9,dud_10;\\\\n\\\\t\\\\n\\\\tOverflowDetection OverflowDetection_0(C2, C3, overflow);\\\\n\\\\t\\\\n\\\\tCLA CLA_0(g0, p0, g1, p1, g2, p2, g3, p3, cin, C0, C1, C2, C3, g, p);\\\\n\\\\t\\\\n\\\\tFourBitALU ALU_0(a[3:0], b[3:0], op, result[3:0], cin, g0, p0, dud_0, dud_1);\\\\n\\\\tFourBitALU ALU_1(a[7:4], b[7:4], op, result[7:4], C1, g1, p1, dud_2, dud_3);\\\\n\\\\tFourBitALU ALU_2(a[11:8], b[11:8], op, result[11:8], C2, g2, p2, dud_4, dud_5);\\\\n\\\\tFourBitALU ALU_3(a[15:12], b[15:12], op, result[15:12], C3, g3, p3, dud_6, dud_7);\\\\n\\\\n\\\\tassign zero = 0; //(zero_0 & zero_1 & zero_2 & zero_3);\\\\n\\\\tassign cout = C3;\\\\n\\\\tassign set = result[15];\\\\n\\\\nendmodule']
["module alu(opcode, A, B, ALU_out, flags);\\\\n\\\\ninput [3:0] opcode;\\\\ninput [15:0] A;\\\\ninput [15:0] B;\\\\noutput [15:0] ALU_out;\\\\noutput [2:0] flags;\\\\n\\\\nlocalparam ADD = 4'b0000;\\\\nlocalparam SUB = 4'b0001;\\\\nlocalparam RED = 4'b0010;\\\\nlocalparam XOR = 4'b0011;\\\\nlocalparam SLL = 4'b0100;\\\\nlocalparam SRA = 4'b0101;\\\\nlocalparam ROR = 4'b0110;\\\\nlocalparam PADDSB_op = 4'b0111;\\\\n\\\\nlocalparam LW = 4'b1000;\\\\nlocalparam SW = 4'b1001;\\\\n\\\\n//flags\\\\nwire N, V, Z_flag;\\\\nassign flags[0] = N;\\\\nassign flags[1] = V;\\\\nassign flags[2] = Z_flag;\\\\n\\\\n\\\\n//ADD\\\\n//cla_16b(Sum, Ovfl, A, B, sub);\\\\nwire [15:0] cla_output;\\\\nwire [15:0] ADD_sum;\\\\nwire ADD_Ovfl;\\\\nwire ADD_sub;\\\\nassign ADD_sub = (opcode == SUB) ? 1'b1 : 1'b0;\\\\n//add_16_bit add_sub_add(.Sum(ADD_sum), .A(A), .B(B));\\\\ncla_16b add_sub_cla(.Sum(cla_output), .Ovfl(ADD_Ovfl), .A(A), .B(B), .sub(ADD_sub));\\\\n\\\\nassign ADD_sum = (~ADD_sub) ? ADD_Ovfl ? (cla_output[15] == 1'b0 ? 16'h7FFF : 16'h8000): cla_output :\\\\n\\\\t\\\\t\\\\tADD_Ovfl ? (cla_output[15] == 1'b1 ? 16'h7FFF : 16'h8000): cla_output; //overflow saturation\\\\n\\\\n//shifter SH \\\\nwire [15:0] SH_out;\\\\nwire SH_mode;\\\\nassign SH_mode = (opcode == SRA) ? 1'b0 : 1'b1; //mode 1 => SLL ; mode 0 => SRA\\\\n\\\\n//instantiate shifter\\\\nShifter alu_shifter(.Shift_Out(SH_out), .Shift_In(A), .Shift_Val(B[3:0]), .Mode(SH_mode));\\\\n\\\\n//Parallel Add PA\\\\n//PADDSB(Sum, Overflow, A, B); \\\\nwire [15:0] PA_result;\\\\nPADDSB PA(.Sum(PA_result), .A(A), .B(B));\\\\n\\\\n//Reduction RED\\\\n//reduction_16b (A, B, Out)\\\\nwire [15:0] RED_result;\\\\nreduction_16b alu_RED(.A(A), .B(B), .Out(RED_result));\\\\n\\\\n\\\\n//ROR\\\\n//ROR(result, A, imm)\\\\nwire [15:0] ROR_result;\\\\nROR alu_ROR(.result(ROR_result), .A(A), .imm(B[3:0]));\\\\n\\\\n\\\\n//set flags\\\\nassign V = ((opcode == ADD) | (opcode == SUB)) ? ADD_Ovfl : 1'bz;\\\\nassign N = ((opcode == ADD) | (opcode == SUB)) ? (ADD_sum[15] == 1) ? 1'b1 : 1'b0 : 1'bz;\\\\nassign Z_flag = ((opcode == ADD) | (opcode == SUB)) ? (ADD_sum == 0) ? 1'b1 : 1'b0 : (opcode == XOR) ? ((A ^ B) == 0) ? 1'b1 : 1'b0 : \\\\n\\\\t (opcode == SLL) ? (SH_out == 0) ? 1'b1 : 1'b0 : (opcode == SRA) ? (SH_out == 0) ? 1'b1 : 1'b0 : \\\\n\\\\t (opcode == ROR) ? (ROR_result == 0) ? 1'b1 : 1'b0 : 1'bz;\\\\n\\\\n\\\\n//set ALU_out\\\\nassign ALU_out = (opcode == ADD) ? ADD_sum : (opcode == SUB) ? ADD_sum : \\\\n\\\\t\\\\t (opcode == SW) ? ADD_sum : (opcode == LW) ? ADD_sum :\\\\n\\\\t\\\\t (opcode == RED) ? RED_result : (opcode == XOR) ? (A ^ B) : \\\\n\\\\t\\\\t (opcode == SLL) ? SH_out : (opcode == SRA) ? SH_out :\\\\n\\\\t\\\\t (opcode == ROR) ? ROR_result : (opcode == PADDSB_op) ? PA_result : 16'b0;\\\\n\\\\n\\\\t\\\\t \\\\n\\\\n\\\\nendmodule"]
["module vga_top(\\\\n\\\\tinput ClkPort,\\\\n\\\\tinput BtnC,\\\\n\\\\tinput BtnU,\\\\n\\\\t\\\\n\\\\t//VGA signal\\\\n\\\\toutput hSync, vSync,\\\\n\\\\toutput [3:0] vgaR, vgaG, vgaB,\\\\n\\\\t\\\\n\\\\t//SSG signal \\\\n\\\\toutput An0, An1, An2, An3, An4, An5, An6, An7,\\\\n\\\\toutput Ca, Cb, Cc, Cd, Ce, Cf, Cg, Dp,\\\\n\\\\t\\\\n\\\\toutput MemOE, MemWR, RamCS, QuadSpiFlashCS\\\\n\\\\t);\\\\n\\\\t\\\\n\\\\twire bright;\\\\n\\\\twire[9:0] hc, vc;\\\\n\\\\twire[15:0] score;\\\\n\\\\twire [6:0] ssdOut;\\\\n\\\\twire [3:0] anode;\\\\n\\\\twire [11:0] rgb;\\\\n\\\\tdisplay_controller dc(.clk(ClkPort), .hSync(hSync), .vSync(vSync), .bright(bright), .hCount(hc), .vCount(vc));\\\\n\\\\tvga_bitchange vbc(.clk(ClkPort), .bright(bright), .button(BtnU), .hCount(hc), .vCount(vc), .rgb(rgb), .score(score));\\\\n\\\\tcounter cnt(.clk(ClkPort), .displayNumber(score), .anode(anode), .ssdOut(ssdOut));\\\\n\\\\t\\\\n\\\\tassign Dp = 1;\\\\n\\\\tassign {Ca, Cb, Cc, Cd, Ce, Cf, Cg} = ssdOut[6 : 0];\\\\n assign {An7, An6, An5, An4, An3, An2, An1, An0} = {4'b1111, anode};\\\\n\\\\n\\\\t\\\\n\\\\tassign vgaR = rgb[11 : 8];\\\\n\\\\tassign vgaG = rgb[7 : 4];\\\\n\\\\tassign vgaB = rgb[3 : 0];\\\\n\\\\t\\\\n\\\\t// disable mamory ports\\\\n\\\\tassign {MemOE, MemWR, RamCS, QuadSpiFlashCS} = 4'b1111;\\\\n\\\\nendmodule"]
["module breakout_graph_animate (clk, reset, btnU, btnD, video_on, pix_x, pix_y, vgaRed, vgaGreen, vgaBlue, score);\\\\ninput clk, reset, btnU, btnD, video_on;\\\\ninput [10:0] pix_x, pix_y;\\\\noutput [3:0] vgaRed, vgaGreen, vgaBlue;\\\\noutput [15:0] score;\\\\n\\\\nreg [3:0] vgaRed, vgaGreen, vgaBlue;\\\\nreg offpage;\\\\n\\\\n// Constant and signal declaration\\\\n// x, y coordinates (0,0) to (799, 599)\\\\nlocalparam MAX_X = 800;\\\\nlocalparam MAX_Y = 600;\\\\n\\\\n// Vertical stripe as a wall\\\\n// wall left, right boundary\\\\nlocalparam WALL_X_L = 0;\\\\nlocalparam WALL_X_R = 3;\\\\n\\\\n// Top horizontal stripe as a wall\\\\n// Wall top, bottom boundary\\\\nlocalparam T_WALL_T = 0;\\\\nlocalparam T_WALL_B = 3;\\\\n\\\\n// Bottom horizontal strip as a wall\\\\n// Wall top, bottom boundary\\\\nlocalparam B_WALL_T = 596;\\\\nlocalparam B_WALL_B = 599;\\\\n\\\\n//Right horizontal stripe as a wall\\\\n// Wall left, right boundary\\\\nlocalparam WALL_Y_L = 798;\\\\nlocalparam WALL_Y_R = 799;\\\\n\\\\n//-----------------------------------------------//\\\\n\\\\n// Paddle\\\\n// bar left, right boundary\\\\nlocalparam BAR_X_L = 741;\\\\nlocalparam BAR_X_R = 750;\\\\n// Bar top, bottom boundary\\\\nwire [10:0] bar_y_t, bar_y_b;\\\\nlocalparam BAR_Y_SIZE = 80;\\\\n// Register to track top boundary (x position fixed)\\\\nreg [10:0] bar_y_reg, bar_y_next;\\\\n// Bar moving velocity when a button is pressed \\\\nlocalparam BAR_V = 4;\\\\n\\\\n//-----------------------------------------------// \\\\n\\\\n// Square ball\\\\nlocalparam BALL_SIZE = 8;\\\\n// Ball left, right boundary\\\\nwire [10:0] ball_x_l, ball_x_r;\\\\n// Ball top, bottom boundary \\\\nwire [10:0] ball_y_t, ball_y_b;\\\\n// Reg to track left, top position\\\\nreg [10:0] ball_x_reg, ball_y_reg;\\\\nwire [10:0] ball_x_next, ball_y_next;\\\\n// Reg to track ball speed\\\\nreg [10:0] x_delta_reg, x_delta_next;\\\\nreg [10:0] y_delta_reg, y_delta_next;\\\\n// Ball velocity can be positive or negative\\\\nlocalparam BALL_V_P = 2;\\\\nlocalparam BALL_V_N = -2;\\\\nlocalparam BALL_V_P_Y = 1;\\\\nlocalparam BALL_V_N_Y = -1;\\\\n\\\\n//------------------------------------------------// \\\\n\\\\n// Round ball\\\\nwire [2:0] rom_addr, rom_col;\\\\nreg [7:0] rom_data;\\\\nwire rom_bit;\\\\n\\\\n//------------------------------------------------//\\\\n\\\\n// Object output signals\\\\nwire wall_on, bar_on, sq_ball_on, rd_ball_on;\\\\nwire C0_ON, C1_ON, C2_ON, C3_ON, C4_ON, C5_ON, C6_ON;\\\\nwire score_ON_R, score_ON_RM, score_ON_LM, score_ON_L;\\\\nwire [3:0] wall_rgb_red, wall_rgb_green, wall_rgb_blue;\\\\nwire [3:0] bar_rgb_red, bar_rgb_green, bar_rgb_blue;\\\\nwire [3:0] ball_rgb_red, ball_rgb_green, ball_rgb_blue;\\\\n\\\\n//------------------------------------------------//\\\\n\\\\nwire blocks_reset;\\\\n\\\\n// Column one blocks\\\\nwire [5:0] C0_count;\\\\nwire C0_U, C0_D, C0_L, C0_R;\\\\nbreakout_blocks column0(.clk(clk), .reset(blocks_reset), .pix_x(pix_x), .pix_y(pix_y), .ball_x_r(ball_x_r),\\\\n\\\\t\\\\t .ball_x_l(ball_x_l), .ball_y_t(ball_y_t), .ball_y_b(ball_y_b), .moveU(C0_U), \\\\n\\\\t\\\\t .moveD(C0_D), .moveL(C0_L), .moveR(C0_R), .C0_count(C0_count), .C0_ON(C0_ON));\\\\n\\\\n// Column two blocks\\\\nwire [5:0] C1_count;\\\\nwire C1_U, C1_D, C1_L, C1_R;\\\\nbreakout_blocks_C1 column1(.clk(clk), .reset(blocks_reset), .pix_x(pix_x), .pix_y(pix_y), .ball_x_r(ball_x_r),\\\\n\\\\t\\\\t .ball_x_l(ball_x_l), .ball_y_t(ball_y_t), .ball_y_b(ball_y_b), .moveU(C1_U), \\\\n\\\\t\\\\t .moveD(C1_D), .moveL(C1_L), .moveR(C1_R), .C1_count(C1_count), .C1_ON(C1_ON));\\\\n\\\\n// Column three blocks\\\\nwire [5:0] C2_count;\\\\nwire C2_U, C2_D, C2_L, C2_R;\\\\nbreakout_blocks_C2 column2(.clk(clk), .reset(blocks_reset), .pix_x(pix_x), .pix_y(pix_y), .ball_x_r(ball_x_r),\\\\n\\\\t\\\\t .ball_x_l(ball_x_l), .ball_y_t(ball_y_t), .ball_y_b(ball_y_b), .moveU(C2_U), \\\\n\\\\t\\\\t .moveD(C2_D), .moveL(C2_L), .moveR(C2_R), .C2_count(C2_count), .C2_ON(C2_ON));\\\\n\\\\n// Column four blocks\\\\nwire [5:0] C3_count;\\\\nwire C3_U, C3_D, C3_L, C3_R;\\\\nbreakout_blocks_C3 column3(.clk(clk), .reset(blocks_reset), .pix_x(pix_x), .pix_y(pix_y), .ball_x_r(ball_x_r),\\\\n\\\\t\\\\t .ball_x_l(ball_x_l), .ball_y_t(ball_y_t), .ball_y_b(ball_y_b), .moveU(C3_U), \\\\n\\\\t\\\\t .moveD(C3_D), .moveL(C3_L), .moveR(C3_R), .C3_count(C3_count), .C3_ON(C3_ON));\\\\n\\\\n// Column five blocks\\\\nwire [4:0] C4_count; \\\\nwire C4_U, C4_D, C4_L, C4_R;\\\\nbreakout_blocks_C4 column4(.clk(clk), .reset(blocks_reset), .pix_x(pix_x), .pix_y(pix_y), .ball_x_r(ball_x_r),\\\\n\\\\t\\\\t .ball_x_l(ball_x_l), .ball_y_t(ball_y_t), .ball_y_b(ball_y_b), .moveU(C4_U), \\\\n\\\\t\\\\t .moveD(C4_D), .moveL(C4_L), .moveR(C4_R), .C4_count(C4_count), .C4_ON(C4_ON));\\\\n\\\\n// Column six blocks\\\\nwire [4:0] C5_count; \\\\nwire C5_U, C5_D, C5_L, C5_R;\\\\nbreakout_blocks_C5 column5(.clk(clk), .reset(blocks_reset), .pix_x(pix_x), .pix_y(pix_y), .ball_x_r(ball_x_r),\\\\n\\\\t\\\\t .ball_x_l(ball_x_l), .ball_y_t(ball_y_t), .ball_y_b(ball_y_b), .moveU(C5_U), \\\\n\\\\t\\\\t .moveD(C5_D), .moveL(C5_L), .moveR(C5_R), .C5_count(C5_count), .C5_ON(C5_ON));\\\\n\\\\n// Column seven blocks\\\\nwire [3:0] C6_count;\\\\nwire C6_U, C6_D, C6_L, C6_R;\\\\nbreakout_blocks_C6 column6(.clk(clk), .reset(blocks_reset), .pix_x(pix_x), .pix_y(pix_y), .ball_x_r(ball_x_r),\\\\n\\\\t\\\\t .ball_x_l(ball_x_l), .ball_y_t(ball_y_t), .ball_y_b(ball_y_b), .moveU(C6_U), \\\\n\\\\t\\\\t .moveD(C6_D), .moveL(C6_L), .moveR(C6_R), .C6_count(C6_count), .C6_ON(C6_ON));\\\\n\\\\n//-----------------------------------------------------------------------//\\\\n\\\\n\\\\n// Score counter\\\\n// Secondary score counter\\\\nreg [7:0] secondary_score;\\\\nalways @(posedge clk) begin\\\\n\\\\tif (reset || offpage)\\\\n\\\\t\\\\tsecondary_score <= 0;\\\\n\\\\telse\\\\n\\\\t\\\\tsecondary_score <= C6_count + C5_count + C4_count + C3_count + C2_count + C1_count + C0_count;\\\\nend\\\\n\\\\n// If secondary_score reaches 224,\\\\n// send_224 will go high for one clk cycle\\\\nreg buffer_1, buffer_2;\\\\nassign two_twenty_two = (secondary_score == 224);\\\\nalways @(posedge clk) buffer_1 <= two_twenty_two;\\\\nalways @(posedge clk) buffer_2 <= buffer_1;\\\\nwire send_224 = buffer_1 && !buffer_2;\\\\n\\\\n// Send 224 indicates that the full board has been destroyed\\\\n// Hence, a full board score needs to be sent to the main score\\\\n// becuase the board is going to reset and send the values back to zero. \\\\nreg [15:0] full_board;\\\\nalways @(posedge clk) begin\\\\n\\\\tif (reset || offpage)\\\\n\\\\t\\\\tfull_board <= 0;\\\\n\\\\telse if (send_224)\\\\n\\\\t\\\\tfull_board <= full_board + 224;\\\\nend\\\\n\\\\n// Main score. Notice full_board only increments every time\\\\n// the board is completely destroyed. \\\\nreg [15:0] score;\\\\nalways @(posedge clk) begin\\\\n\\\\tif (reset || offpage)\\\\n\\\\t\\\\tscore <= 0;\\\\n\\\\telse\\\\n\\\\t\\\\tscore <= full_board + C6_count + C5_count + C4_count + C3_count + C2_count + C1_count + C0_count;\\\\nend\\\\n\\\\n// Send the full score to be converted from base 2 to base 10\\\\nwire [15:0] b_10_score;\\\\nwire moveD1;\\\\nb_10_vga b10_vga(.clk(clk), .sw(score), .num_out(b_10_score));\\\\n\\\\n// Send the score to the onscreen scoreboard\\\\nscore scoreboard(.clk(clk), .reset(), .score(b_10_score), .pix_x(pix_x), .pix_y(pix_y), .ball_x_r(ball_x_r), \\\\n\\\\t\\\\t .ball_x_l(ball_x_l), .ball_y_t(ball_y_t), .ball_y_b(ball_y_b), .moveD(moveD1), .moveL(), .moveR(), \\\\n\\\\t\\\\t .score_ON_R(score_ON_R), .score_ON_RM(score_ON_RM), .score_ON_LM(score_ON_LM), .score_ON_L(score_ON_L));\\\\n\\\\n//------------------------- BODY ---------------------------------// \\\\n\\\\n\\\\n\\\\n// Round ball image ROM\\\\nalways @*\\\\ncase (rom_addr)\\\\n\\\\t3'h0: rom_data = 8'b00111100;\\\\t// ****\\\\n\\\\t3'h1: rom_data = 8'b01111110;\\\\t// ******\\\\n\\\\t3'h2: rom_data = 8'b11111111;\\\\t// ********\\\\n\\\\t3'h3: rom_data = 8'b11111111;\\\\t// ********\\\\n\\\\t3'h4: rom_data = 8'b11111111;\\\\t// ********\\\\n\\\\t3'h5: rom_data = 8'b11111111;\\\\t// ********\\\\n\\\\t3'h6: rom_data = 8'b01111110;\\\\t// ******\\\\n\\\\t3'h7: rom_data = 8'b00111100;\\\\t// ****\\\\nendcase\\\\n\\\\nassign blocks_reset = reset || offpage || send_224;\\\\n\\\\n// Registers \\\\nalways @(posedge clk, posedge reset)\\\\n// Reset entire board\\\\n\\\\tif (reset)\\\\n\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\tbar_y_reg = 11'h104;\\\\n\\\\t\\\\t\\\\tball_x_reg = 11'h18f;\\\\n\\\\t\\\\t\\\\tball_y_reg = 11'h12b;\\\\n\\\\t\\\\t\\\\tx_delta_reg = 11'h002;\\\\n\\\\t\\\\t\\\\ty_delta_reg = 11'h002;\\\\n\\\\t\\\\tend\\\\n\\\\n// Reset blocks and ball to the center of the screen\\\\n\\\\telse if (offpage || send_224)\\\\n\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\tbar_y_reg = bar_y_next;\\\\n\\\\t\\\\t\\\\tball_x_reg = 11'h18f;\\\\n\\\\t\\\\t\\\\tball_y_reg = 11'h12b;\\\\n\\\\t\\\\t\\\\tx_delta_reg = x_delta_next;\\\\n\\\\t\\\\t\\\\ty_delta_reg = y_delta_next;\\\\n\\\\t\\\\tend\\\\t\\\\t\\\\n\\\\telse \\\\n\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\tbar_y_reg = bar_y_next;\\\\n\\\\t\\\\t\\\\tball_x_reg = ball_x_next;\\\\n\\\\t\\\\t\\\\tball_y_reg = ball_y_next;\\\\n\\\\t\\\\t\\\\tx_delta_reg = x_delta_next;\\\\n\\\\t\\\\t\\\\ty_delta_reg = y_delta_next;\\\\n\\\\t\\\\tend\\\\n\\\\n// refresh_tick: 1-clock tick asserted at start of v-sync\\\\n// i.e. - when the screen is refreshed (72 Hz)\\\\nassign refr_tick = (pix_y == 601) && (pix_x == 0);\\\\n\\\\n\\\\n\\\\n//------------------------------------------------------------------// \\\\n\\\\n\\\\n\\\\n// Wall left vertical strip\\\\n// Pixel within wall\\\\nassign wall_on = ((WALL_X_L <= pix_x) && (pix_x <= WALL_X_R)) || ((T_WALL_T <= pix_y) && (pix_y <= T_WALL_B)) || \\\\n\\\\t\\\\t ((B_WALL_T <= pix_y) && (pix_y <= B_WALL_B)); // || ((WALL_Y_L <= pix_x) && (pix_x <= WALL_Y_R));\\\\n// Wall RGB\\\\nassign wall_rgb_red = 4'b0000;\\\\nassign wall_rgb_green = 4'b0111;\\\\nassign wall_rgn_blue = 4'b0000;\\\\n\\\\n\\\\n\\\\n//------------------------------------------------------------------//\\\\t\\\\n\\\\n\\\\n\\\\n// Right vertical Bar (Paddle)\\\\n// Boundary\\\\nassign bar_y_t = bar_y_reg;\\\\nassign bar_y_b = bar_y_t + BAR_Y_SIZE - 1;\\\\n// Pixel within bar\\\\nassign bar_on = (BAR_X_L <= pix_x) && (pix_x <= BAR_X_R) && (bar_y_t <= pix_y) && (pix_y <= bar_y_b);\\\\n// Bar RGB output\\\\nassign bar_rgb_red = 4'b0000;\\\\nassign bar_rgb_green = 4'b0000;\\\\nassign bar_rgb_blue = 4'b0111;\\\\n\\\\n// New bar y-position\\\\nalways @*\\\\nbegin\\\\n\\\\tbar_y_next = bar_y_reg;\\\\t// No move;\\\\n\\\\tif (refr_tick) begin\\\\n\\\\t\\\\tif (btnD & (bar_y_b < (MAX_Y - 1 - BAR_V)))\\\\n\\\\t\\\\t\\\\tbar_y_next = bar_y_reg + BAR_V;\\\\t// Move down\\\\n\\\\t\\\\telse if (btnU & (bar_y_t > BAR_V))\\\\n\\\\t\\\\t\\\\tbar_y_next = bar_y_reg - BAR_V; // Move up\\\\n\\\\tend\\\\nend\\\\n\\\\n\\\\n\\\\n//-------------------------------------------------------------------//\\\\n\\\\n// Square Ball\\\\n// Boundary\\\\nassign ball_x_l = ball_x_reg;\\\\nassign ball_y_t = ball_y_reg;\\\\nassign ball_x_r = ball_x_l + BALL_SIZE - 1;\\\\nassign ball_y_b = ball_y_t + BALL_SIZE - 1;\\\\n// Pixel within square ball\\\\nassign sq_ball_on = (ball_x_l <= pix_x) && (pix_x <= ball_x_r) && (ball_y_t <= pix_y) && (pix_y <= ball_y_b);\\\\n// Map current pixel location to ROM addr/col\\\\nassign rom_addr = pix_y[2:0] - ball_y_t[2:0];\\\\nassign rom_col = pix_x[2:0] - ball_x_l[2:0];\\\\nassign rom_bit = rom_data[rom_col];\\\\n// Pixel within ball\\\\nassign rd_ball_on = sq_ball_on && rom_bit;\\\\n// Ball RGB output\\\\nassign ball_rgb_red = 4'b0111;\\\\nassign ball_rgb_green = 4'b0000;\\\\nassign ball_rgb_blue = 4'b0000;\\\\n// New ball position\\\\nassign ball_x_next = (refr_tick) ? ball_x_reg + x_delta_reg : ball_x_reg;\\\\nassign ball_y_next = (refr_tick) ? ball_y_reg + y_delta_reg : ball_y_reg;\\\\n\\\\n// Ouput from blocks - move up\\\\nassign MOVE_UP = C0_U || C1_U || C2_U || C3_U || C4_U || C5_U || C6_U;\\\\n\\\\n// Ouput from blocks - move down\\\\nassign MOVE_DOWN = C0_D || C1_D || C2_D || C3_D || C4_D || C5_D || C6_D;\\\\n\\\\n// Ouput from blocks - move left\\\\nassign MOVE_LEFT = C0_L || C1_L || C2_L || C3_L || C4_L || C5_L || C6_L;\\\\n\\\\n// Ouput from blocks - move right\\\\nassign MOVE_RIGHT = C0_R || C1_R || C2_R || C3_R || C4_R || C5_R || C6_R;\\\\n\\\\n// In case two directions are set high at the same time,\\\\n// make a counter, and chose a new direction.\\\\nreg UP_DOWN, LEFT_RIGHT;\\\\n\\\\n// Case of multiple hits at once continued....\\\\nalways @(posedge clk)\\\\n\\\\tif ((MOVE_UP == 1) && (MOVE_DOWN == 1))\\\\n\\\\t\\\\tUP_DOWN <= UP_DOWN + 1;\\\\n\\\\nalways @(posedge clk)\\\\n\\\\tif ((MOVE_LEFT == 1) && (MOVE_RIGHT == 1))\\\\n\\\\t\\\\tLEFT_RIGHT <= LEFT_RIGHT + 1;\\\\n\\\\n// New ball velocity - Off-screen\\\\nalways @*\\\\nbegin\\\\n\\\\n\\\\tif (ball_x_r >= WALL_Y_L)\\\\n\\\\t\\\\toffpage = 1;\\\\n\\\\telse\\\\n\\\\t\\\\toffpage = 0;\\\\nend\\\\n\\\\n// New ball velocity - y-direction\\\\nalways @*\\\\nbegin\\\\n\\\\ty_delta_next = y_delta_reg;\\\\n\\\\n\\\\t// reach top\\\\n\\\\tif (ball_y_t <= T_WALL_B)\\\\t\\\\n\\\\t\\\\ty_delta_next = BALL_V_P;\\\\n\\\\n\\\\t// reach bottom\\\\n\\\\telse if (ball_y_b >= B_WALL_T)\\\\n\\\\t\\\\ty_delta_next = BALL_V_N;\\\\n\\\\n\\\\t// Ball hits top of a block\\\\n\\\\telse if ((MOVE_UP == 1) && (MOVE_DOWN == 0))\\\\n\\\\t\\\\ty_delta_next = BALL_V_N;\\\\n\\\\n\\\\t// Ball hits the bottom of a block\\\\n\\\\telse if ((MOVE_DOWN == 1) && (MOVE_UP == 0))\\\\n\\\\t\\\\ty_delta_next = BALL_V_P;\\\\n\\\\n\\\\t// Ball hits both top and bottom of neighbor blocks\\\\n\\\\telse if ((MOVE_DOWN == 1) && (MOVE_UP == 1))\\\\n\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\tif (UP_DOWN == 1)\\\\n\\\\t\\\\t\\\\t\\\\ty_delta_next = BALL_V_P;\\\\n\\\\n\\\\t\\\\t\\\\telse\\\\n\\\\t\\\\t\\\\t\\\\ty_delta_next = BALL_V_N;\\\\n\\\\n\\\\t\\\\tend\\\\n\\\\n\\\\t// Reach bottom of paddle, hit, ball bounce back\\\\n\\\\telse if ((BAR_X_L <= ball_x_r) && (ball_x_r <= BAR_X_R) && ((bar_y_t + 40) <= ball_y_b) && (ball_y_t <= bar_y_b))\\\\t\\\\n\\\\t\\\\t\\\\ty_delta_next = BALL_V_P_Y;\\\\n\\\\n\\\\telse if ((BAR_X_L <= ball_x_r) && (ball_x_r <= BAR_X_R) && (bar_y_t <= ball_y_b) && (ball_y_t <= (bar_y_t + 39)))\\\\n\\\\t\\\\t\\\\ty_delta_next = BALL_V_N_Y;\\\\n\\\\n\\\\t\\\\nend\\\\n\\\\n// New ball velocity - x-direction\\\\nalways @*\\\\nbegin\\\\n\\\\tx_delta_next = x_delta_reg;\\\\n\\\\n\\\\t// reach left wall\\\\n\\\\tif (ball_x_l <= WALL_X_R)\\\\t\\\\t\\\\n\\\\t\\\\tx_delta_next = BALL_V_P; // bounce ball\\\\n\\\\n\\\\t// Ball hits the left side of a block\\\\n\\\\telse if ((MOVE_LEFT == 1) && (MOVE_RIGHT == 0))\\\\n\\\\t\\\\tx_delta_next = BALL_V_N;\\\\n\\\\t\\\\n\\\\t// Ball hits the right side of a block\\\\n\\\\telse if ((MOVE_RIGHT == 1) && (MOVE_LEFT == 0))\\\\n\\\\t\\\\tx_delta_next = BALL_V_P;\\\\n\\\\n\\\\t// Ball hits both left and right of neighbor blocks\\\\n\\\\telse if ((MOVE_LEFT == 1) && (MOVE_RIGHT == 1))\\\\n\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\tif (LEFT_RIGHT == 1)\\\\n\\\\t\\\\t\\\\t\\\\tx_delta_next = BALL_V_P;\\\\n\\\\n\\\\t\\\\t\\\\telse\\\\n\\\\t\\\\t\\\\t\\\\tx_delta_next = BALL_V_N;\\\\n\\\\n\\\\t\\\\tend\\\\n\\\\n\\\\t// Reach bottom of paddle, hit, ball bounce back\\\\n\\\\telse if ((BAR_X_L <= ball_x_r) && (ball_x_r <= BAR_X_R) && ((bar_y_t + 40) <= ball_y_b) && (ball_y_t <= bar_y_b))\\\\t\\\\n\\\\t\\\\t\\\\tx_delta_next = BALL_V_N;\\\\n\\\\n\\\\telse if ((BAR_X_L <= ball_x_r) && (ball_x_r <= BAR_X_R) && (bar_y_t <= ball_y_b) && (ball_y_t <= (bar_y_t + 39)))\\\\n\\\\t\\\\t\\\\tx_delta_next = BALL_V_N;\\\\n\\\\nend\\\\n\\\\n//------------------- Y-Block ------------------------------------------//\\\\nwire block_on;\\\\ny_block y(.pix_x(pix_x), .pix_y(pix_y), .block_on(block_on));\\\\n\\\\n//-----------------------------------------------------------------------// \\\\n// RGB Multiplexing Circuit\\\\nalways @*\\\\n\\\\tif (~video_on) begin\\\\n\\\\t\\\\tvgaRed <= 4'b0000;\\\\n\\\\t\\\\tvgaGreen <= 4'b0000;\\\\n\\\\t\\\\tvgaBlue <= 4'b0000;\\\\n\\\\tend\\\\n\\\\telse begin\\\\n\\\\t// Top, bottom, and left wall is on\\\\n\\\\t\\\\tif (wall_on) begin\\\\n\\\\t\\\\t\\\\tvgaRed <= wall_rgb_red;\\\\n\\\\t\\\\t\\\\tvgaGreen <= wall_rgb_green;\\\\n\\\\t\\\\t\\\\tvgaBlue <= wall_rgb_blue;\\\\n\\\\t\\\\tend \\\\n\\\\t// Paddle is on\\\\n\\\\t\\\\telse if (bar_on) begin\\\\n\\\\t\\\\t\\\\tvgaRed <= bar_rgb_red;\\\\n\\\\t\\\\t\\\\tvgaGreen <= bar_rgb_green;\\\\n\\\\t\\\\t\\\\tvgaBlue <= bar_rgb_blue;\\\\n\\\\t\\\\tend\\\\n\\\\t// Ball is on\\\\n\\\\t\\\\telse if (rd_ball_on) begin\\\\n\\\\t\\\\t\\\\tvgaRed <= ball_rgb_red;\\\\n\\\\t\\\\t\\\\tvgaGreen <= ball_rgb_green;\\\\n\\\\t\\\\t\\\\tvgaBlue <= ball_rgb_blue;\\\\n\\\\t\\\\tend\\\\n\\\\t// Blocks in column one are on\\\\t\\\\n\\\\t\\\\telse if (C0_ON) begin\\\\n\\\\t\\\\t\\\\tvgaRed <= 4'b0111;\\\\n\\\\t\\\\t\\\\tvgaGreen <= 4'b0011;\\\\n\\\\t\\\\t\\\\tvgaBlue <= 4'b1101;\\\\n\\\\t\\\\tend\\\\n\\\\t// Blocks in column two are on\\\\t\\\\n\\\\t\\\\telse if (C1_ON) begin\\\\n\\\\t\\\\t\\\\tvgaRed <= 4'b1010;\\\\n\\\\t\\\\t\\\\tvgaGreen <= 4'b0000;\\\\n\\\\t\\\\t\\\\tvgaBlue <= 4'b1000;\\\\n\\\\t\\\\tend\\\\n\\\\t// Blocks in column three are on\\\\t\\\\n\\\\t\\\\telse if (C2_ON) begin\\\\n\\\\t\\\\t\\\\tvgaRed <= 4'b0000;\\\\n\\\\t\\\\t\\\\tvgaGreen <= 4'b0000;\\\\n\\\\t\\\\t\\\\tvgaBlue <= 4'b1111;\\\\n\\\\t\\\\tend\\\\n\\\\t// Blocks in column four are on\\\\t\\\\n\\\\t\\\\telse if (C3_ON) begin\\\\n\\\\t\\\\t\\\\tvgaRed <= 4'b0001;\\\\n\\\\t\\\\t\\\\tvgaGreen <= 4'b1011;\\\\n\\\\t\\\\t\\\\tvgaBlue <= 4'b0011;\\\\n\\\\t\\\\tend\\\\n\\\\t// Blocks in column five are on\\\\n\\\\t\\\\telse if (C4_ON) begin\\\\n\\\\t\\\\t\\\\tvgaRed <= 4'b1111;\\\\n\\\\t\\\\t\\\\tvgaGreen <= 4'b1110;\\\\n\\\\t\\\\t\\\\tvgaBlue <= 4'b0100;\\\\n\\\\t\\\\tend\\\\n\\\\t// Blocks in column six are on\\\\n\\\\t\\\\telse if (C5_ON) begin\\\\n\\\\t\\\\t\\\\tvgaRed <= 4'b1111;\\\\n\\\\t\\\\t\\\\tvgaGreen <= 4'b0111;\\\\n\\\\t\\\\t\\\\tvgaBlue <= 4'b0010;\\\\n\\\\t\\\\tend\\\\n\\\\t// Blocks in column seven are on\\\\n\\\\t\\\\telse if (C6_ON) begin\\\\n\\\\t\\\\t\\\\tvgaRed <= 4'b1101;\\\\n\\\\t\\\\t\\\\tvgaGreen <= 4'b0001;\\\\n\\\\t\\\\t\\\\tvgaBlue <= 4'b0010;\\\\n\\\\t\\\\tend\\\\n\\\\t// Ones bit of scoreboard is on\\\\n\\\\t\\\\telse if (score_ON_R) begin\\\\n\\\\t\\\\t\\\\tvgaRed <= 4'b0111;\\\\n\\\\t\\\\t\\\\tvgaGreen <= 4'b0001;\\\\n\\\\t\\\\t\\\\tvgaBlue <= 4'b0001;\\\\n\\\\t\\\\tend\\\\n\\\\t// Tens bit of scoreboard is on\\\\n\\\\t\\\\telse if (score_ON_RM) begin\\\\n\\\\t\\\\t\\\\tvgaRed <= 4'b0111;\\\\n\\\\t\\\\t\\\\tvgaGreen <= 4'b0001;\\\\n\\\\t\\\\t\\\\tvgaBlue <= 4'b0001;\\\\n\\\\t\\\\tend\\\\n\\\\t// Hundreds bit of scoreboard is on\\\\n\\\\t\\\\telse if (score_ON_LM) begin\\\\n\\\\t\\\\t\\\\tvgaRed <= 4'b0111;\\\\n\\\\t\\\\t\\\\tvgaGreen <= 4'b0001;\\\\n\\\\t\\\\t\\\\tvgaBlue <= 4'b0001;\\\\n\\\\t\\\\tend\\\\n\\\\t// Thousands bit of scoreboard is on\\\\t\\\\n\\\\t\\\\telse if (score_ON_L) begin\\\\n\\\\t\\\\t\\\\tvgaRed <= 4'b0111;\\\\n\\\\t\\\\t\\\\tvgaGreen <= 4'b0001;\\\\n\\\\t\\\\t\\\\tvgaBlue <= 4'b0001;\\\\n\\\\t\\\\tend\\\\n\\\\t// Y-Block is on\\\\n\\\\t\\\\telse if (block_on) begin\\\\n\\\\t\\\\t\\\\tvgaRed <= ball_rgb_red;\\\\n\\\\t\\\\t\\\\tvgaGreen <= ball_rgb_green;\\\\n\\\\t\\\\t\\\\tvgaBlue <= ball_rgb_blue;\\\\n\\\\t\\\\tend\\\\n\\\\t// Background is on\\\\n\\\\t\\\\telse begin\\\\n\\\\t\\\\t\\\\tvgaRed <= 4'b0000;\\\\n\\\\t\\\\t\\\\tvgaGreen <= 4'b0000;\\\\n\\\\t\\\\t\\\\tvgaBlue <= 4'b0000;\\\\n\\\\t\\\\tend\\\\n\\\\tend\\\\n\\\\t\\\\t\\\\nendmodule"]
['module top(clk, rst_n);\\\\n\\\\tinput clk, rst_n;\\\\n\\\\t//write enable\\\\n\\\\tinput pc_we, reg_we, mem_we;\\\\n\\\\n\\\\t//pc & imem\\\\n\\\\tinput [8:0] pc_in, pc_out;\\\\n\\\\tinput [31:0] op;\\\\n\\\\n\\\\t//decoder\\\\n\\\\tinput [4:0] dst;\\\\n\\\\tinput [4:0] src0, src1;\\\\n\\\\tinput [43:0] dec_data;\\\\n\\\\n\\\\t//alu\\\\n\\\\tinput [6:0] alu_op;\\\\n\\\\tinput [43:0] alu_out;\\\\n\\\\n\\\\t//zf\\\\n\\\\tinput zf, zf_out;\\\\n\\\\n\\\\t//selector\\\\n\\\\tinput sel1, sel2;\\\\n\\\\tinput [43:0] sel1_out, sel2_out;\\\\n\\\\n\\\\t//register\\\\n\\\\tinput [43:0] reg_data0, reg_data1;\\\\n\\\\n\\\\t//memory\\\\n\\\\tinput [43:0] mem_data;\\\\n\\\\n\\\\t//sel\\\\n\\\\tsel s1(.in0(dec_data), .in1(reg_data0), .sel(sel1), .out(sel1_out));\\\\n\\\\tsel s2(.in0(alu_out), .in1(mem_data), .sel(sel2), .out(sel2_out));\\\\n\\\\n\\\\t//register\\\\n\\\\tregfile r0(.src0(src0), .src1(src1), .dst(dst), .we(reg_we), .data(sel2_out), .clk(clk), .rst_n(rst_n), .data0(reg_data0), .data1(reg_data1));\\\\n\\\\n\\\\t//alu\\\\n\\\\talu a0(.in0(sel1_out), .in1(reg_data1), .op(alu_op), .zf(zf), .out(alu_out));\\\\n\\\\n\\\\t//memory\\\\n\\\\tmemory mem0(.in(alu_out), .out(mem_data), .addr(reg_data1), .rst_n(rst_n), .clk(clk), .we(mem_we));\\\\n\\\\n\\\\t//pc\\\\n\\\\tpc pc0(.pc_in(pc_in), .pc_out(pc_out), .rst_n(rst_n), .clk(clk), .we(pc_we));\\\\n\\\\n\\\\t//imem\\\\n\\\\timem imem0(.pc(pc_out), .op(op));\\\\n\\\\n\\\\t//zf\\\\n\\\\tzf zf0(.clk(clk), .rst_n(rst_n), .zf_in(zf), .zf_out(zf_out));\\\\n\\\\n\\\\t//decoder\\\\n\\\\tdecoder dec1(.op(op), .zf(zf_out), .pc_in(pc_in), .pc_we(pc_we), .src0(src0), .src1(src1), .dst(dst), .reg_we(reg_we), .sel1(sel1), .sel2(sel2), .data(dec_data), .alu_op(alu_op), .mem_we(mem_we));\\\\n\\\\nendmodule']
["module for shfR_L logic.\\\\n*/\\\\nmodule shfR_L(in, bit_cnt, Out);\\\\n\\\\ninput [15:0] in;\\\\ninput [3:0] bit_cnt;\\\\n\\\\noutput reg [15:0] Out;\\\\n\\\\n\\\\nalways@(*) begin\\\\n\\\\tcase(bit_cnt)\\\\n\\\\t\\\\t4'b0001 : assign Out = {1'h0, in[15:1]};\\\\n\\\\t\\\\t4'b0010 : assign Out = {2'h0, in[15:2]};\\\\n\\\\t\\\\t4'b0011 : assign Out = {3'h0, in[15:3]};\\\\n\\\\t\\\\t4'b0100 : assign Out = {4'h0, in[15:4]};\\\\n\\\\t\\\\t4'b0101 : assign Out = {5'h0, in[15:5]};\\\\n\\\\t\\\\t4'b0110 : assign Out = {6'h0, in[15:6]};\\\\n\\\\t\\\\t4'b0111 : assign Out = {7'h0, in[15:7]};\\\\n\\\\t\\\\t4'b1000 : assign Out = {8'h0, in[15:8]};\\\\n\\\\t\\\\t4'b1001 : assign Out = {9'h0, in[15:9]};\\\\n\\\\t\\\\t4'b1010 : assign Out = {10'h0, in[15:10]};\\\\n\\\\t\\\\t4'b1011 : assign Out = {11'h0, in[15:11]};\\\\n\\\\t\\\\t4'b1100 : assign Out = {12'h0, in[15:12]};\\\\n\\\\t\\\\t4'b1101 : assign Out = {13'h0, in[15:13]};\\\\n\\\\t\\\\t4'b1110 : assign Out = {14'h0, in[15:14]};\\\\n\\\\t\\\\t4'b1111 : assign Out = {15'h0, in[15]};\\\\n\\\\t\\\\t// 0 -> no shft\\\\n\\\\t\\\\tdefault: assign Out = in;\\\\n\\\\tendcase\\\\nend\\\\n\\\\n\\\\n\\\\nendmodule"]
["module FU_LeftCircularShift_jamahl29(R, B, C, V, N, Z);\\\\n\\\\tinput [7:0] B; \\\\n\\\\t\\\\n\\\\toutput [7:0] R;\\\\t\\\\n\\\\toutput C, V, N, Z;\\\\n\\\\t\\\\n\\\\tassign R = { B[6:0], B[7] };\\\\t\\\\n\\\\tassign C = 1'b0;\\\\n\\\\tassign V = 1'b0;\\\\n\\\\tassign N = 1'b0;\\\\n\\\\tassign Z = 1'b0;\\\\n\\\\t\\\\nendmodule", "module FU_RightCircularShift_jamahl29(R, B, C, V, N, Z);\\\\n\\\\tinput [7:0] B;\\\\n\\\\t\\\\n\\\\toutput [7:0] R;\\\\t\\\\n\\\\toutput C, V, N, Z;\\\\n\\\\t\\\\n\\\\tassign R = { B[0], B[7:1] };\\\\n\\\\tassign C = 1'b0;\\\\n\\\\tassign V = 1'b0;\\\\n\\\\tassign N = 1'b0;\\\\n\\\\tassign Z = 1'b0;\\\\n\\\\t\\\\nendmodule", 'module add_adder(S, Cout, A, B, Cin);\\\\n output S;\\\\n output Cout;\\\\n input A;\\\\n input B;\\\\n input Cin;\\\\n\\\\t\\\\n \\\\n wire w1;\\\\n wire w2;\\\\n wire w3;\\\\n wire w4;\\\\n \\\\n xor(w1, A, B);\\\\n xor(S, Cin, w1);\\\\n and(w2, A, B); \\\\n and(w3, A, Cin);\\\\n and(w4, B, Cin); \\\\n or(Cout, w2, w3, w4);\\\\nendmodule', "module FU_add_jamahl29(S, C, V, N, Z, A, B);\\\\n\\\\toutput [7:0] S; // The 4-bit sum/difference.\\\\n output \\\\tC; // The 1-bit carry/borrow status.\\\\n output \\\\tV; // The 1-bit overflow status.\\\\n\\\\toutput N, Z;\\\\n input [7:0] \\\\tA; // The 4-bit augend/minuend.\\\\n input [7:0] \\\\tB; // The 4-bit addend/subtrahend.\\\\n wire \\\\tOp; // The operation: 0 => Add, 1=>Subtract.\\\\n assign Op = 1'b0;\\\\n\\\\t\\\\n wire \\\\tC0; // The carry out bit of fa0, the carry in bit of fa1.\\\\n wire \\\\tC1; // The carry out bit of fa1, the carry in bit of fa2.\\\\n wire \\\\tC2; // The carry out bit of fa2, the carry in bit of fa3.\\\\n wire \\\\tC3; // The carry out bit of fa2, used to generate final carry/borrrow.\\\\n\\\\twire C4, C5, C6, C7;\\\\n \\\\n wire \\\\tB0; // The xor'd result of B[0] and Op\\\\n wire \\\\tB1; // The xor'd result of B[1] and Op\\\\n wire \\\\tB2; // The xor'd result of B[2] and Op\\\\n wire \\\\tB3; // The xor'd result of B[3] and Op\\\\n\\\\twire B4, B5, B6, B7;\\\\n\\\\n\\\\t\\\\n // Looking at the truth table for xor we see that \\\\n // B xor 0 = B, and\\\\n // B xor 1 = not(B).\\\\n // So, if Op==1 means we are subtracting, then\\\\n // adding A and B xor Op alog with setting the first\\\\n // carry bit to Op, will give us a result of\\\\n // A+B when Op==0, and A+not(B)+1 when Op==1.\\\\n // Note that not(B)+1 is the 2's complement of B, so\\\\n // this gives us subtraction. \\\\n\\\\t\\\\n xor(B0, B[0], Op);\\\\n xor(B1, B[1], Op);\\\\n xor(B2, B[2], Op);\\\\n xor(B3, B[3], Op);\\\\n\\\\txor(B4, B[4], Op);\\\\n\\\\txor(B5, B[5], Op);\\\\n\\\\txor(B6, B[6], Op);\\\\n\\\\txor(B7, B[7], Op);\\\\n \\\\n \\\\n add_adder fa0(S[0], C0, A[0], B0, Op); // Least significant bit.\\\\n add_adder fa1(S[1], C1, A[1], B1, C0);\\\\n add_adder fa2(S[2], C2, A[2], B2, C1);\\\\n add_adder fa3(S[3], C3, A[3], B3, C2); // Most significant bit.\\\\n\\\\tadd_adder fa4(S[4], C4, A[4], B4, C3);\\\\n\\\\tadd_adder fa5(S[5], C5, A[5], B5, C4);\\\\n\\\\tadd_adder fa6(S[6], C6, A[6], B6, C5);\\\\n\\\\tadd_adder fa7(S[7], C7, A[7], B7, C6);\\\\n\\\\t\\\\n\\\\txor(C, C7, Op); // Carry = C3 for addition, Carry = not(C3) for subtraction.\\\\n xor(V, C7, C6); // If the two most significant carry output bits differ, then we have an overflow.\\\\n\\\\tassign N = (S[7] == 1'b1) ? 1'b1 : 1'b0;\\\\n\\\\tassign Z = ( S == 8'b00000000 ) ? 1'b1 : 1'b0;\\\\n\\\\t\\\\nendmodule", "module FU_subtractor_jamahl29(S, C, V, N, Z, A, B);\\\\n output [7:0] S; // The 4-bit sum/difference.\\\\n output \\\\tC; // The 1-bit carry/borrow status.\\\\n output \\\\tV; // The 1-bit overflow status.\\\\n\\\\toutput N, Z;\\\\n input [7:0] \\\\tA; // The 4-bit augend/minuend.\\\\n input [7:0] \\\\tB; // The 4-bit addend/subtrahend.\\\\n wire \\\\tOp; // The operation: 0 => Add, 1=>Subtract.\\\\n assign Op = 1'b1;\\\\n\\\\t\\\\n wire \\\\tC0; // The carry out bit of fa0, the carry in bit of fa1.\\\\n wire \\\\tC1; // The carry out bit of fa1, the carry in bit of fa2.\\\\n wire \\\\tC2; // The carry out bit of fa2, the carry in bit of fa3.\\\\n wire \\\\tC3; // The carry out bit of fa2, used to generate final carry/borrrow.\\\\n\\\\twire C4, C5, C6, C7;\\\\n \\\\n wire \\\\tB0; // The xor'd result of B[0] and Op\\\\n wire \\\\tB1; // The xor'd result of B[1] and Op\\\\n wire \\\\tB2; // The xor'd result of B[2] and Op\\\\n wire \\\\tB3; // The xor'd result of B[3] and Op\\\\n\\\\twire B4, B5, B6, B7;\\\\n\\\\n\\\\t\\\\n // Looking at the truth table for xor we see that \\\\n // B xor 0 = B, and\\\\n // B xor 1 = not(B).\\\\n // So, if Op==1 means we are subtracting, then\\\\n // adding A and B xor Op alog with setting the first\\\\n // carry bit to Op, will give us a result of\\\\n // A+B when Op==0, and A+not(B)+1 when Op==1.\\\\n // Note that not(B)+1 is the 2's complement of B, so\\\\n // this gives us subtraction. \\\\n\\\\t\\\\n xor(B0, B[0], Op);\\\\n xor(B1, B[1], Op);\\\\n xor(B2, B[2], Op);\\\\n xor(B3, B[3], Op);\\\\n\\\\txor(B4, B[4], Op);\\\\n\\\\txor(B5, B[5], Op);\\\\n\\\\txor(B6, B[6], Op);\\\\n\\\\txor(B7, B[7], Op);\\\\n \\\\n \\\\n sub_adder fa0(S[0], C0, A[0], B0, Op); // Least significant bit.\\\\n sub_adder fa1(S[1], C1, A[1], B1, C0);\\\\n sub_adder fa2(S[2], C2, A[2], B2, C1);\\\\n sub_adder fa3(S[3], C3, A[3], B3, C2); // Most significant bit.\\\\n\\\\tsub_adder fa4(S[4], C4, A[4], B4, C3);\\\\n\\\\tsub_adder fa5(S[5], C5, A[5], B5, C4);\\\\n\\\\tsub_adder fa6(S[6], C6, A[6], B6, C5);\\\\n\\\\tsub_adder fa7(S[7], C7, A[7], B7, C6);\\\\n\\\\t\\\\n\\\\txor(C, C7, Op); // Carry = C3 for addition, Carry = not(C3) for subtraction.\\\\n\\\\t//assign C = (C7 != 0 && C7 ) ? 1'b1 : 1'b0;\\\\n xor(V, C7, C6); // If the two most significant carry output bits differ, then we have an overflow.\\\\n\\\\tassign N = (S[7] == 1'b1) ? 1'b1 : 1'b0;\\\\n\\\\tassign Z = ( S == 8'b00000000 ) ? 1'b1 : 1'b0;\\\\n\\\\t\\\\nendmodule", 'module sub_adder(S, Cout, A, B, Cin);\\\\n output S;\\\\n output Cout;\\\\n input A;\\\\n input B;\\\\n input Cin;\\\\n\\\\t\\\\n \\\\n wire w1;\\\\n wire w2;\\\\n wire w3;\\\\n wire w4;\\\\n \\\\n xor(w1, A, B);\\\\n xor(S, Cin, w1);\\\\n and(w2, A, B); \\\\n and(w3, A, Cin);\\\\n and(w4, B, Cin); \\\\n or(Cout, w2, w3, w4);\\\\nendmodule', 'module FU_halfadder_jamahl29(A, B, R, cout);\\\\n\\\\tinput A, B;\\\\n\\\\toutput R, cout;\\\\n\\\\t\\\\t\\\\n\\\\tand and1(cout, A, B);\\\\n\\\\txor xor1(R, A, B);\\\\n\\\\nendmodule', "module FU_incrementer_jamahl29(A, R, C, V, N, Z);\\\\n\\\\tinput [7:0] A;\\\\n\\\\toutput [7:0] R;\\\\n\\\\twire cout;\\\\n\\\\toutput C, V, N, Z;\\\\n\\\\twire [7:0]cin;\\\\n\\\\tassign cin = 8'b00000001;\\\\n\\\\twire [7:0] w;\\\\n\\\\t\\\\n\\\\tFU_halfadder_jamahl29 inc1(A[0], cin, R[0], w[1]);\\\\n\\\\tFU_halfadder_jamahl29 inc2(A[1], w[1], R[1], w[2]);\\\\n\\\\tFU_halfadder_jamahl29 inc3(A[2], w[2], R[2], w[3]);\\\\n\\\\tFU_halfadder_jamahl29 inc4(A[3], w[3], R[3], w[4]);\\\\n\\\\tFU_halfadder_jamahl29 inc5(A[4], w[4], R[4], w[5]);\\\\n\\\\tFU_halfadder_jamahl29 inc6(A[5], w[5], R[5], w[6]);\\\\n\\\\tFU_halfadder_jamahl29 inc7(A[6], w[6], R[6], w[7]);\\\\n\\\\tFU_halfadder_jamahl29 inc8(A[7], w[7], R[7], cout);\\\\n\\\\t\\\\n\\\\tassign C = (cout == 1'b1) ? 1'b1 : 1'b0;\\\\n\\\\tassign V = (A == 8'b01111111) ? 1'b1 : 1'b0;\\\\n\\\\tassign N = (R[7] == 1'b1) ? 1'b1 : 1'b0;\\\\n\\\\tassign Z = ( R == 8'b00000000 ) ? 1'b1 : 1'b0;\\\\n\\\\t\\\\nendmodule", "module FU_negate_jamahl29(A, R, C, V, N, Z);\\\\n\\\\tinput [7:0] A;\\\\n\\\\toutput [7:0] R;\\\\n\\\\twire cout;\\\\n\\\\toutput C, V, N, Z;\\\\n\\\\twire [7:0]cin;\\\\n\\\\tassign cin = 8'b00000001;\\\\n\\\\twire [7:0] w;\\\\n\\\\twire AN;\\\\n\\\\twire A0, A1, A2, A3, A4, A5, A6, A7;\\\\n\\\\t\\\\n\\\\tnot (A0,A[0]);\\\\n\\\\tnot (A1,A[1]);\\\\n\\\\tnot (A2,A[2]);\\\\n\\\\tnot (A3,A[3]);\\\\n\\\\tnot (A4,A[4]);\\\\n\\\\tnot (A5,A[5]);\\\\n\\\\tnot (A6,A[6]);\\\\n\\\\tnot (A7,A[7]);\\\\n\\\\t\\\\n\\\\tFU_halfadder_jamahl29 neg1(A0, cin, R[0], w[1]);\\\\n\\\\tFU_halfadder_jamahl29 neg2(A1, w[1], R[1], w[2]);\\\\n\\\\tFU_halfadder_jamahl29 neg3(A2, w[2], R[2], w[3]);\\\\n\\\\tFU_halfadder_jamahl29 neg4(A3, w[3], R[3], w[4]);\\\\n\\\\tFU_halfadder_jamahl29 neg5(A4, w[4], R[4], w[5]);\\\\n\\\\tFU_halfadder_jamahl29 neg6(A5, w[5], R[5], w[6]);\\\\n\\\\tFU_halfadder_jamahl29 neg7(A6, w[6], R[6], w[7]);\\\\n\\\\tFU_halfadder_jamahl29 neg8(A7, w[7], R[7], cout);\\\\n\\\\t\\\\n\\\\tassign C = (cout == 1'b1) ? 1'b1 : 1'b0;\\\\n\\\\tassign V = (~A == 8'b01111111) ? 1'b1 : 1'b0;\\\\n\\\\tassign N = (R[7] == 1'b1) ? 1'b1 : 1'b0;\\\\n\\\\tassign Z = ( R == 8'b00000000 ) ? 1'b1 : 1'b0;\\\\n\\\\nendmodule", "module FU_bitnand_jamahl29(A, B, R, C, V, N, Z);\\\\n\\\\tinput [7:0]A, B;\\\\n\\\\toutput [7:0] R;\\\\n\\\\toutput C, V, N, Z;\\\\n\\\\t\\\\n\\\\tassign R = ~(A & B);\\\\n\\\\n\\\\tassign C = 1'b0;\\\\n\\\\tassign V = 1'b0;\\\\n\\\\tassign N = (R[7] == 1'b1) ? 1'b1 : 1'b0;\\\\n\\\\tassign Z = ( R == 8'b00000000 ) ? 1'b1 : 1'b0;\\\\n\\\\t\\\\nendmodule", "module FU_bitxnor_jamahl29(A, B, R, C, V, N, Z);\\\\n\\\\tinput [7:0]A, B;\\\\n\\\\toutput [7:0] R;\\\\n\\\\toutput C, V, N, Z;\\\\n\\\\t\\\\n\\\\tassign R = ~(A ^ B);\\\\n\\\\t\\\\n\\\\tassign C = 1'b0;\\\\n\\\\tassign V = 1'b0;\\\\n\\\\tassign N = (R[7] == 1'b1) ? 1'b1 : 1'b0;\\\\n\\\\tassign Z = ( R == 8'b00000000 ) ? 1'b1 : 1'b0;\\\\n\\\\nendmodule", "module FU_bitnot_jamahl29(A, R, C, V, N, Z);\\\\n\\\\tinput [7:0]A;\\\\n\\\\toutput [7:0] R;\\\\n\\\\toutput C, V, N, Z;\\\\n\\\\n\\\\tassign R = ~A;\\\\n\\\\t\\\\n\\\\tassign C = 1'b0;\\\\n\\\\tassign V = 1'b0;\\\\n\\\\tassign N = (R[7] == 1'b1) ? 1'b1 : 1'b0;\\\\n\\\\tassign Z = ( R == 8'b00000000 ) ? 1'b1 : 1'b0;\\\\n\\\\n\\\\nendmodule", "module FU_Bmult4_jamahl29( B, R, C, V, N, Z);\\\\n\\\\tinput [7:0] B;\\\\n\\\\toutput [7:0] R;\\\\n\\\\toutput C, V, N, Z;\\\\n\\\\t\\\\n\\\\tassign R = B << 2;\\\\n\\\\t\\\\n\\\\tassign C = 1'b0;\\\\n\\\\tassign V = 1'b0;\\\\n\\\\tassign N = (R[7] == 1'b1) ? 1'b1 : 1'b0;\\\\n\\\\tassign Z = ( R == 8'b00000000 ) ? 1'b1 : 1'b0;\\\\n\\\\nendmodule", "module FU_Bdiv16_jamahl29( B, R, C, V, N, Z);\\\\n\\\\tinput [7:0] B;\\\\n\\\\toutput [7:0] R;\\\\n\\\\toutput C, V, N, Z;\\\\n\\\\twire [7:0] compB;\\\\n\\\\tnot notB(compB, B)\\\\n\\\\t\\\\n\\\\tassign R = (B[7] == 1'b1) ? { 4'b1111 , B[7:4] } : { 4'b0000 , B[7:4] };\\\\n\\\\t\\\\n\\\\tassign C = 1'b0;\\\\n\\\\tassign V = 1'b0;\\\\n\\\\tassign N = (R[7] == 1'b1) ? 1'b1 : 1'b0;\\\\n\\\\tassign Z = ( R == 8'b00000000 ) ? 1'b1 : 1'b0;\\\\n\\\\t\\\\nendmodule", "module FU_Bmod16_jamahl29( B, R, C, V, N, Z);\\\\n\\\\tinput [7:0] B;\\\\n\\\\toutput [7:0] R;\\\\n\\\\toutput C, V, N, Z;\\\\n\\\\t\\\\n\\\\tassign R = {4'b0000 , B[3:0] };\\\\n\\\\n\\\\tassign C = 1'b0;\\\\n\\\\tassign V = 1'b0;\\\\n\\\\tassign N = 1'b0;\\\\n\\\\tassign Z = ( R == 8'b00000000 ) ? 1'b1 : 1'b0;\\\\n\\\\t\\\\nendmodule"]
['module start_stop_gen (\\\\n\\\\tclk,\\\\n\\\\tn_rst,\\\\n\\\\tbus_busy,\\\\n\\\\tstart,\\\\n\\\\tstop,\\\\n\\\\tclock_div,\\\\n\\\\tSDA,\\\\n\\\\tSCL,\\\\n\\\\tdone\\\\n);\\\\n\\\\tinput clk;\\\\n\\\\tinput n_rst;\\\\n\\\\tinput bus_busy;\\\\n\\\\tinput start;\\\\n\\\\tinput stop;\\\\n\\\\tinput wire [31:0] clock_div;\\\\n\\\\toutput reg SDA;\\\\n\\\\toutput reg SCL;\\\\n\\\\toutput reg done;\\\\n\\\\tlocalparam COUNTER_BITS = 9;\\\\n\\\\twire enabled;\\\\n\\\\twire wait_expired;\\\\n\\\\treg [4:0] state;\\\\n\\\\treg [4:0] next_state;\\\\n\\\\tassign enabled = start | stop;\\\\n\\\\tflex_counter_master #(.NUM_CNT_BITS(32)) counter(\\\\n\\\\t\\\\t.clk(clk),\\\\n\\\\t\\\\t.n_rst(n_rst),\\\\n\\\\t\\\\t.rollover_val(clock_div),\\\\n\\\\t\\\\t.rollover_flag(wait_expired),\\\\n\\\\t\\\\t.count_enable(enabled),\\\\n\\\\t\\\\t.clear(!enabled)\\\\n\\\\t);\\\\n\\\\tlocalparam [4:0] IDLE_BUSY = 1;\\\\n\\\\tlocalparam [4:0] IDLE_NOT_BUSY = 0;\\\\n\\\\tlocalparam [4:0] START1 = 2;\\\\n\\\\tlocalparam [4:0] START2 = 3;\\\\n\\\\tlocalparam [4:0] START3 = 4;\\\\n\\\\tlocalparam [4:0] START_DONE = 5;\\\\n\\\\tlocalparam [4:0] STOP1 = 6;\\\\n\\\\tlocalparam [4:0] STOP2 = 7;\\\\n\\\\tlocalparam [4:0] STOP3 = 8;\\\\n\\\\tlocalparam [4:0] STOP_DONE = 9;\\\\n\\\\talways @(*) begin\\\\n\\\\t\\\\tnext_state = state;\\\\n\\\\t\\\\tcase (state)\\\\n\\\\t\\\\t\\\\tIDLE_NOT_BUSY:\\\\n\\\\t\\\\t\\\\t\\\\tif (start)\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tnext_state = START1;\\\\n\\\\t\\\\t\\\\t\\\\telse if (stop)\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tnext_state = STOP1;\\\\n\\\\t\\\\t\\\\t\\\\telse if (bus_busy)\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tnext_state = IDLE_BUSY;\\\\n\\\\t\\\\t\\\\tIDLE_BUSY:\\\\n\\\\t\\\\t\\\\t\\\\tif (start)\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tnext_state = START1;\\\\n\\\\t\\\\t\\\\t\\\\telse if (stop)\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tnext_state = STOP1;\\\\n\\\\t\\\\t\\\\t\\\\telse if (!bus_busy)\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tnext_state = IDLE_NOT_BUSY;\\\\n\\\\t\\\\t\\\\tSTART1: next_state = (wait_expired ? START2 : START1);\\\\n\\\\t\\\\t\\\\tSTART2: next_state = (wait_expired ? START3 : START2);\\\\n\\\\t\\\\t\\\\tSTART3: next_state = (wait_expired ? START_DONE : START3);\\\\n\\\\t\\\\t\\\\tSTOP1: next_state = (wait_expired ? STOP2 : STOP1);\\\\n\\\\t\\\\t\\\\tSTOP2: next_state = (wait_expired ? STOP3 : STOP2);\\\\n\\\\t\\\\t\\\\tSTOP3: next_state = (wait_expired ? STOP_DONE : STOP3);\\\\n\\\\t\\\\tendcase\\\\n\\\\t\\\\tif (!enabled & bus_busy)\\\\n\\\\t\\\\t\\\\tnext_state = IDLE_BUSY;\\\\n\\\\t\\\\telse if (!enabled & !bus_busy)\\\\n\\\\t\\\\t\\\\tnext_state = IDLE_NOT_BUSY;\\\\n\\\\tend\\\\n\\\\talways @(posedge clk or negedge n_rst)\\\\n\\\\t\\\\tif (!n_rst)\\\\n\\\\t\\\\t\\\\tstate <= IDLE_NOT_BUSY;\\\\n\\\\t\\\\telse\\\\n\\\\t\\\\t\\\\tstate <= next_state;\\\\n\\\\talways @(*) begin\\\\n\\\\t\\\\tSDA = 1;\\\\n\\\\t\\\\tSCL = 1;\\\\n\\\\t\\\\tdone = 0;\\\\n\\\\t\\\\tcase (state)\\\\n\\\\t\\\\t\\\\tIDLE_NOT_BUSY: begin\\\\n\\\\t\\\\t\\\\t\\\\tSDA = 1;\\\\n\\\\t\\\\t\\\\t\\\\tSCL = 1;\\\\n\\\\t\\\\t\\\\t\\\\tdone = 0;\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\tIDLE_BUSY: begin\\\\n\\\\t\\\\t\\\\t\\\\tSDA = 1;\\\\n\\\\t\\\\t\\\\t\\\\tSCL = 0;\\\\n\\\\t\\\\t\\\\t\\\\tdone = 0;\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\tSTART1: begin\\\\n\\\\t\\\\t\\\\t\\\\tSDA = 1;\\\\n\\\\t\\\\t\\\\t\\\\tSCL = 1;\\\\n\\\\t\\\\t\\\\t\\\\tdone = 0;\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\tSTART2: begin\\\\n\\\\t\\\\t\\\\t\\\\tSDA = 0;\\\\n\\\\t\\\\t\\\\t\\\\tSCL = 1;\\\\n\\\\t\\\\t\\\\t\\\\tdone = 0;\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\tSTART3: begin\\\\n\\\\t\\\\t\\\\t\\\\tSDA = 0;\\\\n\\\\t\\\\t\\\\t\\\\tSCL = 0;\\\\n\\\\t\\\\t\\\\t\\\\tdone = 0;\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\tSTART_DONE: begin\\\\n\\\\t\\\\t\\\\t\\\\tSDA = 0;\\\\n\\\\t\\\\t\\\\t\\\\tSCL = 0;\\\\n\\\\t\\\\t\\\\t\\\\tdone = 1;\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\tSTOP1: begin\\\\n\\\\t\\\\t\\\\t\\\\tSDA = 0;\\\\n\\\\t\\\\t\\\\t\\\\tSCL = 0;\\\\n\\\\t\\\\t\\\\t\\\\tdone = 0;\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\tSTOP2: begin\\\\n\\\\t\\\\t\\\\t\\\\tSDA = 0;\\\\n\\\\t\\\\t\\\\t\\\\tSCL = 1;\\\\n\\\\t\\\\t\\\\t\\\\tdone = 0;\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\tSTOP3: begin\\\\n\\\\t\\\\t\\\\t\\\\tSDA = 1;\\\\n\\\\t\\\\t\\\\t\\\\tSCL = 1;\\\\n\\\\t\\\\t\\\\t\\\\tdone = 0;\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\tSTOP_DONE: begin\\\\n\\\\t\\\\t\\\\t\\\\tSDA = 1;\\\\n\\\\t\\\\t\\\\t\\\\tSCL = 1;\\\\n\\\\t\\\\t\\\\t\\\\tdone = 1;\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\tendcase\\\\n\\\\tend\\\\nendmodule']
["module register_5(M1, ldM1, clk, q);\\\\n//module add_sub (a, b, s,add,sub);\\\\n//module Ashreg_11b (r, M2, clrq, ldM2, ldq, sh, clk, q);\\\\n//module mux2to1 (i0, i1, sel , y);\\\\n//module datapath (data_in, clk, ldM1, ldM2, ldq, clrq, sh, add, sub, sel, q1, q0, data_out); //ldM2=init\\\\n//module controller (start, rst, clk, q0, q1, ldM1, clrq, ldM2, ldq, sh, add, sub, sel, done);\\\\n//module BoothMultiplier (start, rst, clk, done, data_in, data_out);\\\\n\\\\nmodule BoothMultiplier_tb();\\\\n reg [4:0] data_in;\\\\n reg start, rst, clk;\\\\n wire [4:0] data_out, ps, add_sub_out; //test\\\\n wire done, add, sub; //test\\\\n wire [10:0] q; //test\\\\n \\\\n BoothMultiplier DUT(start, rst, clk, done, data_in, data_out, q, ps, add_sub_out, add, sub); //test\\\\n \\\\n initial\\\\n begin\\\\n start = 1'b0;\\\\n rst = 1'b0;\\\\n clk = 1'b0;\\\\n #11 rst = 1'b1;\\\\n #31 rst = 1'b0;\\\\n #31 start = 1'b1;\\\\n #31 start = 1'b0;\\\\n #31 data_in = 5'b10001;\\\\n #61 data_in = 5'b10001;\\\\n #1700 $finish;\\\\n end\\\\n \\\\n always\\\\n begin\\\\n #31 clk = ~clk;\\\\n end\\\\n \\\\n \\\\nendmodule"]
["module degree_computation(deg_Ri,deg_Qi,stop_i,d1out,start,//input\\\\n deg_Ro,deg_Qo,stop_o,sw,//output\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t clk,reset);//,//);\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t //DR2,DQ2,addr_signal,addq_signal);//~~~~\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t// mr_signal,mq_signal,r2mux_signal,q2mux_signal//~~\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t //);\\\\n\\\\ninput [4:0]deg_Ri,deg_Qi;\\\\ninput [12:0]d1out;\\\\ninput stop_i,clk,start,reset;\\\\n\\\\noutput [4:0]deg_Ro,deg_Qo;\\\\noutput stop_o,sw;\\\\n/*output [4:0]//DR2,DQ2,addr_signal,addq_signal;//,//~~~~\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t mr_signal,mq_signal,r2mux_signal,q2mux_signal;//~~~~~~~~~~~~~~\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t */\\\\nparameter DELAY =1; \\\\n\\\\t\\\\t\\\\t\\\\t\\\\t \\\\n\\\\t\\\\t\\\\t\\\\t\\\\t \\\\nwire out,j1_signal,j2_signal,z_lead,stop1_signal,stop2_signal;\\\\nwire [4:0]rmux_signal,qmux_signal,\\\\n addr_signal,addq_signal,\\\\n\\\\t mr_signal,mq_signal,\\\\n\\\\t r2mux_signal,q2mux_signal;\\\\nwire [12:0]dmux_signal;\\\\n\\\\n\\\\nreg shift_reg,sw_reg,start_reg;\\\\nreg [4:0]DR1,DR2,DR3,DQ1,DQ2,DQ3;//reg [16:0]shift_reg;\\\\n\\\\n\\\\n//-----------------------------------------------------------------\\\\n\\\\nassign out=(deg_Ri<deg_Qi); //|| deg_Ri==deg_Qi);\\\\nassign sw=shift_reg;\\\\n\\\\nmux_5 mdeg1(.a(DQ1),.b(DR1),.sel(sw_reg),.out(rmux_signal));\\\\nmux_5 mdeg2(.a(DR1),.b(DQ1),.sel(sw_reg),.out(qmux_signal));\\\\n\\\\nassign addr_signal=DR2-5'd1;\\\\nassign addq_signal=DQ2-5'd1;\\\\nmux_5 mdeg3(.a(DR2),.b(addr_signal),.sel(z_lead),.out(mr_signal));\\\\nmux_5 mdeg4(.a(addq_signal),.b(DQ2),.sel(z_lead),.out(mq_signal));\\\\n\\\\nmux_5 mdeg5(.a(DR2),.b(mr_signal),.sel(stop_i),.out(r2mux_signal));\\\\nmux_5 mdeg6(.a(DQ2),.b(mq_signal),.sel(stop_i),.out(q2mux_signal));\\\\n\\\\nassign deg_Ro=DR3;\\\\nassign deg_Qo=DQ3;\\\\n\\\\nassign j1_signal=(mr_signal<8);\\\\nassign j2_signal=(mq_signal<8);\\\\nassign stop1_signal=(j1_signal || j2_signal);//or\\\\nassign stop2_signal=start_reg;\\\\nassign stop_o=stop1_signal && stop2_signal;\\\\n\\\\n//--- verify coeff of Q==0 --------\\\\n\\\\nmux_13 mdeg7(.a(d1out),.b(13'd1),.sel(start_reg),.out(dmux_signal));\\\\nassign z_lead=(dmux_signal==0);\\\\n\\\\n\\\\nalways@(posedge clk or negedge reset)\\\\nbegin\\\\n \\\\n\\\\n\\\\t \\\\n\\\\t if(!reset)\\\\n\\\\t begin\\\\n\\\\t shift_reg <=#1 0;\\\\n\\\\t\\\\t sw_reg <=#1 0;\\\\n\\\\t\\\\t start_reg <=#1 1;\\\\n\\\\t\\\\t DR1 <=#1 0;\\\\n\\\\t\\\\t DR2 <=#1 0;\\\\n\\\\t\\\\t DR3 <=#1 0;\\\\n\\\\t\\\\t DQ1 <=#1 0;\\\\n\\\\t\\\\t DQ2 <=#1 0;\\\\n\\\\t\\\\t DQ3 <=#1 0;\\\\n\\\\t end\\\\n\\\\t else\\\\n\\\\t begin\\\\n\\\\t shift_reg <=#1 out;\\\\n\\\\t sw_reg <=#1 out;\\\\n\\\\t DR1 <=#1 deg_Ri;\\\\n\\\\t DQ1 <=#1 deg_Qi;\\\\n\\\\n DR2 <=#1 rmux_signal;\\\\n\\\\t DQ2 <=#1 qmux_signal;\\\\n\\\\n\\\\t DR3 <=#1 r2mux_signal;\\\\n\\\\t DQ3 <=#1 q2mux_signal;\\\\n\\\\t\\\\t //--- verify coeff of Q==0 --------\\\\n\\\\t start_reg <=#1 start;\\\\n\\\\t end\\\\n\\\\nend\\\\nendmodule"]
["module floatingmultiplier(\\\\ninput [31:0] num1, num2,\\\\noutput [31:0] product\\\\n );\\\\n \\\\nwire [31:0] out;\\\\nwire [8:0] realexp1;\\\\nwire [8:0] realexp2;\\\\nwire [8:0] preshiftexp;\\\\nwire [5:0] shift;\\\\nwire [8:0] prerealexp;\\\\nwire valid;\\\\nwire [47:0] fracprod;\\\\n\\\\nmultsign MS1(.sign1(num1[31]), .sign2(num2[31]), .signout(out[31])); //figure out positive/negative\\\\nrealexp RE1(.in({1'b0,num1[30:23]}), .out(realexp1)); \\\\nrealexp RE2(.in({1'b0,num2[30:23]}), .out(realexp2)); \\\\naddexp AE1(.in1(realexp1), .in2(realexp2), .out(preshiftexp));\\\\nnormmultexp NME(.num1(preshiftexp), .num2(shift), .out(prerealexp));\\\\nrealmultexp RME(.in(prerealexp), .out({valid,out[30:23]}));\\\\nfmtocpu FTC(.in(out), .invalid(valid), .product(product));\\\\nfracmult FM(.num1({1'b1, num1[22:0]}), .num2({1'b1, num2[22:0]}), .product(fracprod));\\\\ntruncmult TM(.num(fracprod), .truncated(out[22:0]), .shift(shift));\\\\nendmodule"]
["module mul_matr #(\\\\n parameter BITS =28\\\\n) (\\\\n input clk, \\\\n input [1:0] mat_sel, \\\\n\\\\tinput [4:0]adr,\\\\n //input[10:0] in_or_w1,\\\\n input signed [20:0] w2, \\\\n output reg [2:0] decision \\\\n );\\\\n\\\\n\\\\n\\\\treg signed [10:0] mem1 [BITS:0][BITS:0]; //input matrix\\\\n\\\\treg signed [10:0] mem2 [BITS:0][BITS:0]; //weight matrix/hiddenlayer\\\\n\\\\treg signed [20:0] mem3 [BITS:0][BITS:0]; //product matrix/hidden layer\\\\n\\\\n\\\\treg signed [20:0] mem4 [BITS:0][BITS:0]; //output matrix of hidden layer\\\\n\\\\treg signed [20:0] mem5 [BITS:0][BITS:0]; //weight matrix/outputlayer\\\\n\\\\treg signed [40:0] mem6 [BITS:0][BITS:0]; // product matrix/output layer\\\\n\\\\ninteger i;\\\\ninteger j;\\\\ninteger k;\\\\n\\\\ninteger p;\\\\ninteger q;\\\\n\\\\ninteger r;\\\\ninteger s;\\\\n\\\\ninteger a,b,c;\\\\n\\\\ninteger e,f;\\\\n//integer u,v, ready;\\\\nreg [2:0] index;\\\\n\\\\nreg signed [40:0] temp;\\\\nreg [2:0] temp1;\\\\n\\\\nreg [2:0] new;\\\\n\\\\nalways@(posedge clk)\\\\nbegin\\\\n\\\\n//input matrix\\\\n//mem1[0][0]=-4;\\\\n//mem1[0][1]= 15;\\\\n//mem1[1][0]=2;\\\\n//mem1[1][1]= 4;\\\\n\\\\nif(mat_sel==2'b00)\\\\nbegin\\\\n\\\\tmem1[adr]=w2;\\\\t\\\\n\\\\t\\\\nend\\\\n\\\\t\\\\n\\\\t\\\\n if(mat_sel==2'b01)\\\\n\\\\t\\\\t\\\\nbegin\\\\n\\\\t\\\\n\\\\tmem2[adr]=w2;\\\\t\\\\n\\\\t\\\\nend\\\\n\\\\t\\\\n\\\\t\\\\n\\\\t\\\\nif(mat_sel==2'b10)\\\\n\\\\t\\\\t\\\\nbegin\\\\n\\\\tmem5[adr]=w2;\\\\t\\\\n\\\\t\\\\nend\\\\n\\\\t\\\\n\\\\t\\\\n\\\\n// weight matrix hidden layer\\\\n//mem2[0][0]=20;\\\\n//mem2[0][1]= 15;\\\\n//mem2[1][0]=2;\\\\n//mem2[1][1]= 3;\\\\n\\\\n\\\\n\\\\n// weight matrix output layer\\\\n\\\\n\\\\n//mem5[0][0]=100;\\\\n//mem5[0][1]= -25;\\\\n//mem5[1][0]=25;\\\\n//mem5[1][1]= 3;\\\\n\\\\n\\\\n\\\\n\\\\n//hidden layer calculations\\\\n\\\\n\\\\n\\\\n//matrix initilization\\\\n\\\\tfor (p=0;p<=BITS-1;p=p+1)begin\\\\n \\\\n\\\\t\\\\tfor(q=0;q<=BITS-1;q=q+1)begin\\\\n \\\\n\\\\tmem3[p][q]=0;\\\\n\\\\tmem6[p][q]=0;\\\\n\\\\nend\\\\n\\\\n end\\\\n\\\\n\\\\n\\\\n//matrix multiplication\\\\n\\\\n\\\\tfor (k=0;k<=BITS-1;k=k+1) begin\\\\n\\\\n\\\\t\\\\tfor (i=0; i<=BITS-1;i=i+1)begin\\\\n \\\\n\\\\t\\\\t\\\\tfor (j=0;j<=BITS-1;j=j+1) begin\\\\n mem3[k][i]=mem3[k][i]+(mem1[k][j]*mem2[j][i]);\\\\n\\\\n end\\\\n\\\\n\\\\nend\\\\n\\\\nend\\\\n\\\\n\\\\n//out1=mem3[x][y];\\\\n\\\\n\\\\n//relu\\\\n\\\\n\\\\tfor(r=0;r<=BITS-1;r=r+1)begin\\\\n\\\\n\\\\t\\\\tfor (s=0;s<=BITS-1;s=s+1) begin\\\\n if(mem3[r][s]<=0)\\\\n\\\\t mem4[r][s]=0;\\\\n\\\\telse if(mem3[r][s]>=0)\\\\n\\\\t mem4[r][s]=mem3[r][s];\\\\n \\\\n\\\\n end\\\\n\\\\nend\\\\n\\\\n\\\\n\\\\n\\\\n//out2=mem4[x][y];\\\\n\\\\n\\\\n\\\\n// output layer calculations\\\\n\\\\n\\\\n\\\\n\\\\n//matrix multiplication\\\\n\\\\n\\\\n\\\\tfor (a=0;a<=BITS-1;a=a+1) begin\\\\n\\\\n\\\\t\\\\tfor (b=0; b<=BITS-1;b=b+1)begin\\\\n \\\\n\\\\t\\\\t\\\\tfor (c=0;c<=BITS-1;c=c+1) begin\\\\n mem6[a][b]=mem6[a][b]+(mem4[a][c]*mem5[c][b]);\\\\n\\\\n end\\\\n\\\\n\\\\nend\\\\n\\\\nend\\\\n\\\\n\\\\n\\\\n//out3=mem6[x][y];\\\\n\\\\n\\\\n\\\\n// decision using comparison\\\\n\\\\n\\\\n\\\\n\\\\n\\\\n\\\\n\\\\n\\\\n\\\\n\\\\n\\\\n\\\\ntemp=mem6[0][0];\\\\nindex=0;\\\\n\\\\tfor (e=0;e<=BITS-1;e=e+1) begin\\\\n \\\\n\\\\t\\\\tfor(f=0;f<=BITS-1;f=f+1) begin\\\\n index=index+1;\\\\n if (temp<=mem6[e][f]) begin\\\\n\\\\t\\\\n\\\\t //temp=mem6[e][f];\\\\n\\\\t temp1=index;\\\\n\\\\tend\\\\n else if(temp>=mem6[e][f]) begin\\\\n \\\\n temp=temp;\\\\n end\\\\n\\\\t\\\\n\\\\t\\\\nend\\\\n\\\\n\\\\nend\\\\n\\\\n//decision=temp1;\\\\n//out4=temp;\\\\n\\\\nnew=temp;\\\\ndecision=temp1;\\\\n\\\\n\\\\n\\\\nend\\\\n\\\\n\\\\n\\\\n\\\\nendmodule"]
["module DATA_PATH(DATA_OUT, ADDR, ZERO, INSTRUCTION, DATA_IN, CTRL, CLK, RST);\\\\n\\\\n// output list\\\\noutput [`ADDRESS_INDEX_LIMIT:0] ADDR;\\\\noutput ZERO;\\\\noutput [`DATA_INDEX_LIMIT:0] DATA_OUT, INSTRUCTION;\\\\n\\\\n// input list\\\\ninput [`CTRL_WIDTH_INDEX_LIMIT:0] CTRL;\\\\ninput CLK, RST;\\\\ninput [`DATA_INDEX_LIMIT:0] DATA_IN;\\\\n\\\\n//add wires\\\\nwire [31:0] pc_load,ir_load,sp_load, alu_out;\\\\nwire[31:0] op1_sel_1,md_sel_1;\\\\nwire [31:0] op2_sel_1,op2_sel_2,op2_sel_3,op2_sel_4;\\\\nwire [31:0] wd_sel_1,wd_sel_2,wd_sel_3;\\\\nwire [25:0] pc_sel_1,pc_sel_2,pc_sel_3;\\\\nwire[25:0] ma_sel_1;\\\\nwire[31:0] ma_sel_2;\\\\nwire [31:0] reg1, reg2;\\\\nwire [4:0] r1_sel_1,wa_sel_1,wa_sel_2,wa_sel_3;\\\\nwire[31:0] add_out1,add_out2;\\\\nwire not_needed;\\\\n\\\\nRC_ADD_SUB_32 adder1(.Y(add_out1), .CO(not_needed), .A(32'h01), .B(pc_load), .SnA(1'b0));\\\\n \\\\nRC_ADD_SUB_32 adder2(.Y(add_out2), .CO(not_needed), .A(add_out1), .B({{16{ir_load[15]}},ir_load[15:0]}), .SnA(1'b0));\\\\n\\\\n//26 bit multiplexer done in mux.v 2x1\\\\nMUX26_2x1 pc1_mux(.Y(pc_sel_1), .I0(reg1[25:0]), .I1(add_out2[25:0]), .S(CTRL[0])); //0\\\\nMUX26_2x1 pc2_mux(.Y(pc_sel_2),.I0(pc_sel_1),.I1(add_out1[25:0]),.S(CTRL[1]));//1\\\\nMUX26_2x1 pc3_mux(.Y(pc_sel_3),.I0(ir_load[25:0]),.I1(pc_sel_2),.S(CTRL[2]));//2\\\\n//r1_sel_1\\\\nMUX5_2x1 r1_sel1mux(.Y(r1_sel_1), .I0(ir_load[25:21]), .I1(5'b0), .S(CTRL[3]));//3\\\\n\\\\n//op1_sel_1\\\\nMUX32_2x1 op1_mux(.Y(op1_sel_1),.I0(reg1),.I1(sp_load),.S(CTRL[4])); //4\\\\n//op2_sel_#\\\\nMUX32_2x1 op2_sel_1mux(.Y(op2_sel_1),.I0(1),.I1({27'b0,ir_load[10:6]}),.S(CTRL[5])); //5\\\\nMUX32_2x1 op2_sel_2mux(.Y(op2_sel_2),.I0({{16'b0},ir_load[15:0]}),.I1({{16{ir_load[15]}},ir_load[15:0]}),.S(CTRL[6]));//6\\\\nMUX32_2x1 op2_sel_3mux(.Y(op2_sel_3),.I0(op2_sel_2),.I1(op2_sel_1),.S(CTRL[7]));//7\\\\nMUX32_2x1 op2_sel_4mux(.Y(op2_sel_4),.I0(op2_sel_3),.I1(reg2),.S(CTRL[8]));//8\\\\n//wa_sel_#\\\\n\\\\nMUX5_2x1 wa1_mux(.Y(wa_sel_1),.I0(ir_load[15:11]/*rd*/),.I1(ir_load[20:16]/*rt*/),.S(CTRL[9]));\\\\nMUX5_2x1 wa2_mux(.Y(wa_sel_2),.I0(0),.I1(31),.S(CTRL[10]));\\\\nMUX5_2x1 wa3_mux(.Y(wa_sel_3),.I0(wa_sel_2),.I1(wa_sel_1),.S(CTRL[11]));\\\\n\\\\n//PC REGISTER\\\\ndefparam PC.PATTERN=32'h00001000;\\\\nREG32_PP PC(.Q(pc_load),.D({6'b0,pc_sel_3}),.LOAD(CTRL[12]),.CLK(CLK),.RESET(RST));\\\\n//SP \\\\ndefparam SP.PATTERN=32'h03fffffff;\\\\nREG32_PP SP(.Q(sp_load),.D(alu_out),.LOAD(CTRL[23]),.CLK(CLK),.RESET(RST));\\\\n\\\\n//IR \\\\nREG32 inst_loadreg(.Q(ir_load), .D(DATA_IN),.LOAD(CTRL[13]), .CLK(CLK), .RESET(RST));\\\\n\\\\n//Register file\\\\nREGISTER_FILE_32x32 regfile(.DATA_R1(reg1), .DATA_R2(reg2), .ADDR_R1(r1_sel_1), .ADDR_R2(ir_load[20:16]/*rt*/), \\\\n .DATA_W(wd_sel_3), .ADDR_W(wa_sel_3), .READ(CTRL[14]), .WRITE(CTRL[15]), .CLK(CLK), .RST(RST));\\\\n\\\\n//ALU\\\\nALU alu(.OUT(alu_out), .ZERO(ZERO), .OP1(op1_sel_1), .OP2(op2_sel_4), .OPRN(CTRL[21:16]));\\\\n\\\\n//md_sel_1\\\\n\\\\nMUX32_2x1 md_mux(.Y(DATA_OUT),.I0(reg2),.I1(reg1),.S(CTRL[22]));\\\\n\\\\n\\\\n\\\\n//ma_sel_#\\\\nMUX32_2x1 ma_sel1mux(.Y(ma_sel_1),.I0(alu_out),.I1(sp_load),.S(CTRL[24]));\\\\nMUX26_2x1 ma_sel2mux(.Y(ma_sel_2),.I0(ma_sel_1),.I1(pc_load[25:0]),.S(CTRL[25]));\\\\n\\\\n//wd_sel_#\\\\nMUX32_2x1 wd_sel_1mux(.Y(wd_sel_1),.I0(alu_out),.I1(DATA_IN),.S(CTRL[26]));\\\\nMUX32_2x1 wd_sel2mux(.Y(wd_sel_2),.I0(wd_sel_1),.I1({ir_load[15:0],{16{ir_load[15]}}}),.S(CTRL[27]));\\\\nMUX32_2x1 wd_sel3mux(.Y(wd_sel_3),.I0(add_out2),.I1(wd_sel_2),.S(CTRL[28]));\\\\n\\\\n\\\\n\\\\n\\\\n\\\\n\\\\n\\\\nendmodule"]
["module nrf(clk,clk2mhz,reset,spi_sck,spi_ce,spi_csn,spi_miso,spi_mosi,nrf_out,spi_ss_b,sf_ce0,amp_cs,\\\\nfpga_init_b,dac_cs,ad_conv);\\\\n\\\\ninput clk,reset;\\\\noutput reg clk2mhz;\\\\noutput reg spi_sck,spi_csn,spi_ce;\\\\noutput reg spi_mosi;\\\\ninput spi_miso;\\\\noutput reg [7:0]nrf_out;\\\\n\\\\noutput spi_ss_b,sf_ce0,fpga_init_b,dac_cs,ad_conv,amp_cs; // DISABLING SIGNAL\\\\n\\\\n\\\\nreg [7:0]rx_address = 8'b11101101 ; // TX_ADDRESS=ED\\\\n\\\\n//reg [7:0]tx_address2 = 8'b11100111 ; // TX_ADDRESS=E7\\\\n//reg [7:0]tx_address3 = 8'b11100111 ; // TX_ADDRESS=E7\\\\n//reg [7:0]tx_address4 = 8'b11100111 ; // TX_ADDRESS=E7\\\\n//reg [7:0]tx_address5 = 8'b11100111 ; // TX_ADDRESS=E7\\\\n\\\\n\\\\n\\\\nreg [7:0]CONFIG_value=8'b00011111; // 0x1E--Enable CRC of 2 Byte and PWR_UP=1 i.e. PRX=1 ,Receiver\\\\n\\\\nreg [7:0]EN_AA_value =8'b00000000; // Disable Auto Acknowledgement\\\\nreg [7:0]EN_RXADDR_value =8'b00000001; // Enable data pipe 0\\\\nreg [7:0]SETUP_AW_value =8'b00000011; // Address width is 5 Bytes\\\\n\\\\nreg [7:0]RF_CH_value =8'b00000001; //RF channel registry 0b0000 0001 =2,401GHz (same in the TX RX)\\\\nreg [7:0]RF_SETUP_value =8'b00000111; //1Mbps,-0 dBm\\\\nreg [7:0]STATUS_value =8'b01000000; //Reset all IRQ in status register (to be able to listen again)\\\\nreg [7:0]RX_PW_P0_value =8'b00000001; //1 Byte Payload\\\\nreg [7:0]SETUP_RETR_value=8'b00000000;\\\\n\\\\n//reg [7:0]SETUP_RETR_value=8'b00011110;\\\\n//reg [7:0]CONFIG_value=8'b00011110;\\\\n//reg [7:0]RX_ADDR_P0_value=8'b00011110;\\\\n\\\\n\\\\nreg [7:0]payload1=8'b01110010; // 8 bit payload data \\\\nreg [7:0]payload2=8'b11101010;\\\\nreg [7:0]payload3=8'b00111010;\\\\n\\\\n\\\\n\\\\n\\\\n\\\\nreg [14:0]count_pwr_on_off=0; //counter for power off to power on state(12 ms)\\\\n\\\\nreg [9:0]count_pwr_down_pwr_up=0; // counter for power down to power up mode\\\\n\\\\nreg [7:0]count_pwr_up_tx_rx=0;\\\\n\\\\nreg [6:0]clk_count=0; // for dividing 50 mHZ TO 2 mHZ CLOCK\\\\nreg [3:0]reg_count=8; for shifting 8 bit SPI data \\\\nreg [3:0]status_count=8;\\\\nreg [3:0]status_clk=8;\\\\nreg [10:0]countm=0;\\\\nreg [7:0]ce_count=0; //CE count ,which is minimum 10 micro second\\\\nreg [10:0]count_standby=0; // counter for POWER DOWN to STANDBY (min. 2 milisecond)\\\\nreg [2:0]payload_count=0; // number of payload to be sent\\\\n\\\\n\\\\n\\\\nreg [8:0]state=000000000; // states of nrf24l01\\\\n\\\\n\\\\n// DISBALING OTHER PERIPHERAL COMMUNICATING WITH SPI BUS\\\\n\\\\nassign spi_ss_b=0; // Disable SPI Flash on spartan 3E \\\\nassign sf_ce0=1; //FLASH\\\\nassign fpga_init_b=1;\\\\nassign dac_cs=1; //DAC\\\\nassign ad_conv=0; //ADC\\\\nassign amp_cs=1; ADC\\\\n\\\\n// MEMORY MAP for WRITING into Nrf Register--W_REGISTER---[001A AAAA] FORMAT\\\\n\\\\nparameter \\\\tCONFIG_W =8'b00100000,//8'h0\\\\n \\\\t\\\\tEN_AA_W =8'b00100001,//8'h1\\\\n \\\\t\\\\tEN_RXADDR_W =8'b00100010,//8'h2\\\\n \\\\t\\\\tSETUP_AW_W =8'b00100011,//8'h3\\\\n \\\\t\\\\tSETUP_RETR_W =8'b00100100,//8'h4\\\\n \\\\t\\\\tRF_CH_W =8'b00100101,//8'h5\\\\n \\\\t\\\\tRF_SETUP_W =8'b00100110,//8'h6\\\\n \\\\t\\\\tSTATUS_W =8'b00100111,//8'h7\\\\n \\\\t\\\\tOBSERVE_TX_W =8'b00101000,//8'h8\\\\n \\\\t\\\\tCD_W =8'b00101001,//8'h9\\\\n \\\\t\\\\tRX_ADDR_P0_W =8'b00101010,//8'hA\\\\n \\\\t\\\\tRX_ADDR_P1_W =8'b00101011,//8'hB\\\\n \\\\t\\\\tRX_ADDR_P2_W =8'b00101100,//8'hC\\\\n \\\\t\\\\tRX_ADDR_P3_W =8'b00101101,//8'hD\\\\n \\\\t\\\\tRX_ADDR_P4_W =8'b00101110,//8'hE\\\\n \\\\t\\\\tRX_ADDR_P5_W =8'b00101111,//8'hF\\\\n \\\\t\\\\tTX_ADDR_W =8'b00110000,//8'h10\\\\n \\\\t\\\\tRX_PW_P0_W =8'b00110001,//8'h11\\\\n \\\\t\\\\tRX_PW_P1_W =8'b00110010,//8'h12\\\\n \\\\t\\\\tRX_PW_P2_W =8'b00110011,//8'h13\\\\n \\\\t\\\\tRX_PW_P3_W =8'b00110100,//8'h14\\\\n \\\\t\\\\tRX_PW_P4_W =8'b00110101,//8'h15\\\\n \\\\t\\\\tRX_PW_P5_W =8'b00110110,//8'h16\\\\n \\\\t\\\\tFIFO_STATUS_W =8'b00110111;//8'h17\\\\n \\\\t\\\\t\\\\n \\\\t\\\\t\\\\n// MEMORY MAP FOR READING Nrf REGISTER----R_REGISTER---[000A AAAA] FORMAT\\\\n\\\\nparameter \\\\tCONFIG_R =8'b00000000,//8'h0\\\\n \\\\t\\\\tEN_AA_R =8'b00000001,//8'h1\\\\n \\\\t\\\\tEN_RXADDR_R =8'b00000010,//8'h2\\\\n \\\\t\\\\tSETUP_AW_R =8'b00000011,//8'h3\\\\n \\\\t\\\\tSETUP_RETR_R =8'b00000100,//8'h4\\\\n \\\\t\\\\tRF_CH_R =8'b00000101,//8'h5\\\\n \\\\t\\\\tRF_SETUP_R =8'b00000110,//8'h6\\\\n \\\\t\\\\tSTATUS_R =8'b00000111,//8'h7\\\\n \\\\t\\\\tOBSERVE_TX_R =8'b00001000,//8'h8\\\\n \\\\t\\\\tCD_R =8'b00001001,//8'h9\\\\n \\\\t\\\\tRX_ADDR_P0_R =8'b00001010,//8'hA\\\\n \\\\t\\\\tRX_ADDR_P1_R =8'b00001011,//8'hB\\\\n \\\\t\\\\tRX_ADDR_P2_R =8'b00001100,//8'hC\\\\n \\\\t\\\\tRX_ADDR_P3_R =8'b00001101,//8'hD\\\\n \\\\t\\\\tRX_ADDR_P4_R =8'b00001110,//8'hE\\\\n \\\\t\\\\tRX_ADDR_P5_R =8'b00001111,//8'hF\\\\n \\\\t\\\\tTX_ADDR_R =8'b00010000,//8'h10\\\\n \\\\t\\\\tRX_PW_P0_R =8'b00010001,//8'h11\\\\n \\\\t\\\\tRX_PW_P1_R =8'b00010010,//8'h12\\\\n \\\\t\\\\tRX_PW_P2_R =8'b00010011,//8'h13\\\\n \\\\t\\\\tRX_PW_P3_R =8'b00010100,//8'h14\\\\n \\\\t\\\\tRX_PW_P4_R =8'b00010101,//8'h15\\\\n \\\\t\\\\tRX_PW_P5_R =8'b00010110,//8'h16\\\\n \\\\t\\\\tFIFO_STATUS_R =8'b00010111;//8'h17\\\\n\\\\n\\\\n// SPI INSTRUCTION\\\\nparameter \\\\tR_REGISTER =8'b00000000,//8'h0\\\\n \\\\t\\\\tW_REGISTER =8'b00100000,//8'h20\\\\n \\\\t\\\\tREGISTER_MASK =8'b00011111,//8'h1F\\\\n \\\\t\\\\tR_RX_PAYLOAD =8'b01100001,//8'h61\\\\n \\\\t\\\\tW_TX_PAYLOAD =8'b10100000,//8'hA0\\\\n \\\\t\\\\tFLUSH_TX =8'b11100001,//8'hE1\\\\n \\\\t\\\\tFLUSH_RX =8'b11100010,//8'hE2\\\\n \\\\t\\\\tREUSE_TX_PL =8'b11100011,//8'hE3\\\\n \\\\t\\\\tNOP =8'b11111111;//8'hFF\\\\n\\\\n//////////////// 50 mhz to 2 Mhz division /////////////////////////////////\\\\n\\\\n\\\\nalways@(posedge clk ) // 2 Mhz clock\\\\n \\\\nbegin\\\\nif((clk_count>=25)&& (clk_count<50))\\\\nbegin\\\\nclk2mhz<=1;\\\\nclk_count<=clk_count+1;\\\\nend\\\\nelse\\\\nbegin\\\\nclk2mhz<=0;\\\\nclk_count<=clk_count+1;\\\\nend\\\\nif(clk_count>=50)\\\\n begin\\\\n clk_count<=0;\\\\n \\\\n end\\\\nend\\\\n\\\\n\\\\nalways @(posedge clk2mhz or posedge reset)\\\\nbegin\\\\n\\\\nif(reset)\\\\n\\\\nbegin\\\\nspi_mosi<=0;\\\\nspi_csn<=1;\\\\nspi_ce<=0;\\\\nspi_sck<=0;\\\\nstate<=1;\\\\nnrf_out<=8'b01111110; // default nrf output (user define)\\\\nend\\\\n\\\\n\\\\nelse \\\\nbegin\\\\ncase(state) /////// NRF states start here\\\\n\\\\n1:begin\\\\nif(count_pwr_on_off==6000) //12 Ms //A 10.3 ms delay is required between power off and power on states (controlled by 3.3 V supply)\\\\nbegin\\\\ncount_pwr_on_off<=0;\\\\nstate<=state+1;\\\\nend\\\\nelse\\\\ncount_pwr_on_off<=count_pwr_on_off+1;\\\\nspi_sck<=0;\\\\nend\\\\n\\\\n\\\\n2:begin\\\\nspi_csn<=0;\\\\nspi_ce<=1;\\\\nspi_sck<=0;\\\\nstate<=state+1;\\\\nend\\\\n\\\\n3:begin\\\\nspi_csn<=0;\\\\nspi_sck<=0;\\\\nspi_mosi<=CONFIG_W[reg_count-1]; // Configuration of CONFIG REGISTER for CRC,EN_CRC,PWR_UP,PRIM_RX_TX\\\\nreg_count<=reg_count-1;\\\\nstate<=state+1;\\\\nend\\\\n\\\\n4:begin\\\\n\\\\nspi_sck<=1;\\\\nif(reg_count>0) // SHIFTING 8 BIT DATA THROUGH SPI\\\\nbegin\\\\nstate<=3;\\\\nend\\\\n\\\\nelse\\\\n\\\\nbegin\\\\nspi_sck<=1;\\\\nspi_csn<=0;\\\\nstate<=state+1;\\\\nreg_count<=8;\\\\nend\\\\nend\\\\n\\\\n5:begin\\\\nif(countm==5) //waiting for sometime between CONFIG write and CONFIG_VALUE write\\\\nbegin\\\\ncountm<=0;\\\\nstate<=state+1;\\\\nend\\\\nelse\\\\ncountm<=countm+1;\\\\nspi_sck<=0;\\\\nend\\\\n\\\\n6:begin\\\\n\\\\nspi_sck<=0;\\\\nspi_mosi<=CONFIG_value[reg_count-1]; //writing data into CONFIG REGISTER .\\\\nreg_count<=reg_count-1;\\\\nstate<=state+1;\\\\nend\\\\n\\\\n7:begin\\\\n\\\\nspi_sck<=1;\\\\nif(reg_count>0) // SHIFTING 8 BIT DATA THROUGH SPI\\\\nbegin\\\\nstate<=6;\\\\nend\\\\n\\\\nelse\\\\n\\\\nbegin\\\\nspi_sck<=1;\\\\nspi_csn<=0;\\\\nstate<=state+1;\\\\nreg_count<=8;\\\\nend\\\\nend\\\\n\\\\n8:begin\\\\nif(countm==5) //delay for next configuration\\\\nbegin\\\\ncountm<=0;\\\\nstate<=state+1;\\\\nend\\\\nelse\\\\ncountm<=countm+1;\\\\nspi_sck<=0;\\\\nend\\\\n\\\\n9:begin\\\\nspi_sck<=0;\\\\nspi_csn<=1;\\\\nstate<=state+1;\\\\nend\\\\n\\\\n10:begin\\\\nspi_sck<=0;\\\\nspi_csn<=1;\\\\nstate<=state+1;\\\\nend\\\\n\\\\n11:begin\\\\nspi_sck<=0;\\\\nspi_csn<=1;\\\\nstate<=12;\\\\nend\\\\n\\\\n\\\\n12:begin\\\\nspi_csn<=0;\\\\nspi_sck<=0;\\\\nstate<=state+1;\\\\nend\\\\n\\\\n\\\\n\\\\n\\\\n13:begin\\\\nspi_csn<=0;\\\\nspi_sck<=0;\\\\nspi_mosi<=EN_AA_W[reg_count-1]; // Configuration of EN_AA REGISTER for Enable \\\\u2018Auto Acknowledgment\\\\nreg_count<=reg_count-1;\\\\nstate<=state+1;\\\\nend\\\\n\\\\n14:begin\\\\n\\\\nspi_sck<=1;\\\\nif(reg_count>0) // SHIFTING 8 BIT DATA THROUGH SPI\\\\nbegin\\\\nstate<=13;\\\\nend\\\\n\\\\nelse\\\\n\\\\nbegin\\\\nspi_sck<=1;\\\\nspi_csn<=0;\\\\nstate<=state+1;\\\\nreg_count<=8;\\\\nend\\\\nend\\\\n\\\\n15:begin\\\\nif(countm==5) //DELAY BETWEEN data given into EN_AA Register\\\\nbegin\\\\ncountm<=0;\\\\nstate<=state+1;\\\\nend\\\\nelse\\\\ncountm<=countm+1;\\\\nspi_sck<=0;\\\\nend\\\\n\\\\n16:begin\\\\n\\\\nspi_sck<=0;\\\\nspi_mosi<=EN_AA_value[reg_count-1]; // writing data into EN_AA Register i.e disabling auto acknowledgment\\\\nreg_count<=reg_count-1;\\\\nstate<=state+1;\\\\nend\\\\n\\\\n17:begin\\\\n\\\\nspi_sck<=1;\\\\nif(reg_count>0) // SHIFTING 8 BIT DATA THROUGH SPI\\\\nbegin\\\\nstate<=16;\\\\nend\\\\n\\\\nelse\\\\n\\\\nbegin\\\\nspi_sck<=1;\\\\nspi_csn<=0;\\\\nstate<=state+1;\\\\nreg_count<=8;\\\\nend\\\\nend\\\\n\\\\n18:begin\\\\nif(countm==5) //delay for next configuration\\\\nbegin\\\\ncountm<=0;\\\\nstate<=state+1;\\\\nend\\\\nelse\\\\ncountm<=countm+1;\\\\nspi_sck<=0;\\\\nend\\\\n\\\\n19:begin\\\\nspi_sck<=0;\\\\nspi_csn<=1;\\\\nstate<=state+1;\\\\nend\\\\n\\\\n20:begin\\\\nspi_sck<=0;\\\\nspi_csn<=1;\\\\nstate<=state+1;\\\\nend\\\\n\\\\n21:begin\\\\nspi_sck<=0;\\\\nspi_csn<=1;\\\\nstate<=state+1;\\\\nend\\\\n\\\\n\\\\n22:begin\\\\nspi_csn<=0;\\\\nspi_sck<=0;\\\\nstate<=state+1;\\\\nend\\\\n\\\\n\\\\n\\\\n\\\\n23:begin\\\\nspi_csn<=0;\\\\nspi_sck<=0;\\\\nspi_mosi<=EN_RXADDR_W[reg_count-1]; // Configuration of EN_RXADDR REGISTER TO ENABLE particular PIPE\\\\nreg_count<=reg_count-1;\\\\nstate<=state+1;\\\\nend\\\\n\\\\n24:begin\\\\n\\\\nspi_sck<=1;\\\\nif(reg_count>0) // SHIFTING 8 BIT DATA THROUGH SPI\\\\nbegin\\\\nstate<=23;\\\\nend\\\\n\\\\nelse\\\\n\\\\nbegin\\\\nspi_sck<=1;\\\\nspi_csn<=0;\\\\nstate<=state+1;\\\\nreg_count<=8;\\\\nend\\\\nend\\\\n\\\\n25:begin\\\\nif(countm==5) //DELAY BETWEEN data given into EN_RXADDR Register\\\\nbegin\\\\ncountm<=0;\\\\nstate<=state+1;\\\\nend\\\\nelse\\\\ncountm<=countm+1;\\\\nspi_sck<=0;\\\\nend\\\\n\\\\n26:begin\\\\n\\\\nspi_sck<=0;\\\\nspi_mosi<=EN_RXADDR_value[reg_count-1]; // writing data into EN_RXADDR Register\\\\nreg_count<=reg_count-1;\\\\nstate<=state+1;\\\\nend\\\\n\\\\n27:begin\\\\n\\\\nspi_sck<=1;\\\\nif(reg_count>0) // SHIFTING 8 BIT DATA THROUGH SPI\\\\nbegin\\\\nstate<=26;\\\\nend\\\\n\\\\nelse\\\\n\\\\nbegin\\\\nspi_sck<=1;\\\\nspi_csn<=0;\\\\nstate<=state+1;\\\\nreg_count<=8;\\\\nend\\\\nend\\\\n\\\\n28:begin\\\\nif(countm==5) //DELAY for next configuration register\\\\nbegin\\\\ncountm<=0;\\\\nstate<=state+1;\\\\nend\\\\nelse\\\\ncountm<=countm+1;\\\\nspi_sck<=0;\\\\nend\\\\n\\\\n29:begin\\\\nspi_sck<=0;\\\\nspi_csn<=1;\\\\nstate<=state+1;\\\\nend\\\\n\\\\n30:begin\\\\nspi_sck<=0;\\\\nspi_csn<=1;\\\\nstate<=state+1;\\\\nend\\\\n\\\\n31:begin\\\\nspi_sck<=0;\\\\nspi_csn<=1;\\\\nstate<=33;\\\\nend\\\\n\\\\n\\\\n33:begin\\\\nspi_csn<=0;\\\\nspi_sck<=0;\\\\nstate<=state+1;\\\\nend\\\\n\\\\n\\\\n\\\\n34:begin\\\\nspi_csn<=0;\\\\nspi_sck<=0;\\\\nspi_mosi<=SETUP_AW_W[reg_count-1]; // Configuration of SETUP_AW REGISTER for setting address width\\\\nreg_count<=reg_count-1;\\\\nstate<=state+1;\\\\nend\\\\n\\\\n35:begin\\\\n\\\\nspi_sck<=1;\\\\nif(reg_count>0) // SHIFTING 8 BIT DATA THROUGH SPI\\\\nbegin\\\\nstate<=34;\\\\nend\\\\n\\\\nelse\\\\n\\\\nbegin\\\\nspi_sck<=1;\\\\nspi_csn<=0;\\\\nstate<=state+1;\\\\nreg_count<=8;\\\\nend\\\\nend\\\\n\\\\n36:begin\\\\nif(countm==5) //DELAY BETWEEN data given into SETUP_AW REGISTER\\\\nbegin\\\\ncountm<=0;\\\\nstate<=state+1;\\\\nend\\\\nelse\\\\ncountm<=countm+1;\\\\nspi_sck<=0;\\\\nend\\\\n\\\\n37:begin\\\\n\\\\nspi_sck<=0;\\\\nspi_mosi<=SETUP_AW_value[reg_count-1]; // writing data into SETUP_AW Register\\\\nreg_count<=reg_count-1;\\\\nstate<=state+1;\\\\nend\\\\n\\\\n38:begin\\\\n\\\\nspi_sck<=1;\\\\nif(reg_count>0) // SHIFTING 8 BIT DATA THROUGH SPI\\\\nbegin\\\\nstate<=37;\\\\nend\\\\n\\\\nelse\\\\n\\\\nbegin\\\\nspi_sck<=1;\\\\nspi_csn<=0;\\\\nstate<=state+1;\\\\nreg_count<=8;\\\\nend\\\\nend\\\\n\\\\n39:begin\\\\nif(countm==5) //DELAY for next configuration register\\\\nbegin\\\\ncountm<=0;\\\\nstate<=state+1;\\\\nend\\\\nelse\\\\ncountm<=countm+1;\\\\nspi_sck<=0;\\\\nend\\\\n\\\\n40:begin\\\\nspi_sck<=0;\\\\nspi_csn<=1;\\\\nstate<=state+1;\\\\nend\\\\n\\\\n41:begin\\\\nspi_sck<=0;\\\\nspi_csn<=1;\\\\nstate<=state+1;\\\\nend\\\\n\\\\n42:begin\\\\nspi_sck<=0;\\\\nspi_csn<=1;\\\\nstate<=state+1;\\\\nend\\\\n\\\\n\\\\n43:begin\\\\nspi_csn<=0;\\\\nspi_sck<=0;\\\\nstate<=state+1;\\\\nend\\\\n\\\\n\\\\n44:begin\\\\nspi_csn<=0;\\\\nspi_sck<=0;\\\\nspi_mosi<=RF_CH_W[reg_count-1]; // Configuration of RF_CH REGISTER TO set freq of channel\\\\nreg_count<=reg_count-1;\\\\nstate<=state+1;\\\\nend\\\\n\\\\n45:begin\\\\n\\\\nspi_sck<=1;\\\\nif(reg_count>0) // SHIFTING 8 BIT DATA THROUGH SPI\\\\nbegin\\\\nstate<=44;\\\\nend\\\\n\\\\nelse\\\\n\\\\nbegin\\\\nspi_sck<=1;\\\\nspi_csn<=0;\\\\nstate<=state+1;\\\\nreg_count<=8;\\\\nend\\\\nend\\\\n\\\\n46:begin\\\\nif(countm==5) //DELAY BETWEEN data given into RF_CH Register\\\\nbegin\\\\ncountm<=0;\\\\nstate<=state+1;\\\\nend\\\\nelse\\\\ncountm<=countm+1;\\\\nspi_sck<=0;\\\\nend\\\\n\\\\n47:begin\\\\n\\\\nspi_sck<=0;\\\\nspi_mosi<=RF_CH_value[reg_count-1]; // writing data into RF_CH Register\\\\nreg_count<=reg_count-1;\\\\nstate<=state+1;\\\\nend\\\\n\\\\n48:begin\\\\n\\\\nspi_sck<=1;\\\\nif(reg_count>0) // SHIFTING 8 BIT DATA THROUGH SPI\\\\nbegin\\\\nstate<=47;\\\\nend\\\\n\\\\nelse\\\\n\\\\nbegin\\\\nspi_sck<=1;\\\\nspi_csn<=0;\\\\nstate<=state+1;\\\\nreg_count<=8;\\\\nend\\\\nend\\\\n\\\\n49:begin\\\\nif(countm==5) //DELAY for next configuration register\\\\nbegin\\\\ncountm<=0;\\\\nstate<=state+1;\\\\nend\\\\nelse\\\\ncountm<=countm+1;\\\\nspi_sck<=0;\\\\nend\\\\n\\\\n50:begin\\\\nspi_sck<=0;\\\\nspi_csn<=1;\\\\nstate<=state+1;\\\\nend\\\\n\\\\n51:begin\\\\nspi_sck<=0;\\\\nspi_csn<=1;\\\\nstate<=state+1;\\\\nend\\\\n\\\\n52:begin\\\\nspi_sck<=0;\\\\nspi_csn<=1;\\\\nstate<=state+1;\\\\nend\\\\n\\\\n\\\\n53:begin\\\\nspi_csn<=0;\\\\n//spi_ce<=0;\\\\nspi_sck<=0;\\\\nstate<=state+1;\\\\nend\\\\n\\\\n\\\\n\\\\n54:begin\\\\nspi_csn<=0;\\\\nspi_sck<=0;\\\\nspi_mosi<=RF_SETUP_W[reg_count-1]; // Configuration of RF_SETUP REGISTER TO set RF output power,data rate\\\\nreg_count<=reg_count-1;\\\\nstate<=state+1;\\\\nend\\\\n\\\\n55:begin\\\\n\\\\nspi_sck<=1;\\\\nif(reg_count>0) // SHIFTING 8 BIT DATA THROUGH SPI\\\\nbegin\\\\nstate<=54;\\\\nend\\\\n\\\\nelse\\\\n\\\\nbegin\\\\nspi_sck<=1;\\\\nspi_csn<=0;\\\\nstate<=state+1;\\\\nreg_count<=8;\\\\nend\\\\nend\\\\n\\\\n56:begin\\\\nif(countm==5) //DELAY BETWEEN data given into RF_SETUP Register\\\\nbegin\\\\ncountm<=0;\\\\nstate<=state+1;\\\\nend\\\\nelse\\\\ncountm<=countm+1;\\\\nspi_sck<=0;\\\\nend\\\\n\\\\n57:begin\\\\n\\\\nspi_sck<=0;\\\\nspi_mosi<=RF_SETUP_value[reg_count-1]; // writing data into RF_SETUP Register\\\\nreg_count<=reg_count-1;\\\\nstate<=state+1;\\\\nend\\\\n\\\\n58:begin\\\\n\\\\nspi_sck<=1;\\\\nif(reg_count>0) // SHIFTING 8 BIT DATA THROUGH SPI\\\\nbegin\\\\nstate<=57;\\\\nend\\\\n\\\\nelse\\\\n\\\\nbegin\\\\nspi_sck<=1;\\\\nspi_csn<=0;\\\\nstate<=state+1;\\\\nreg_count<=8;\\\\nend\\\\nend\\\\n\\\\n59:begin\\\\nif(countm==5) //DELAY for next configuration register\\\\nbegin\\\\ncountm<=0;\\\\nstate<=state+1;\\\\nend\\\\nelse\\\\ncountm<=countm+1;\\\\nspi_sck<=0;\\\\nend\\\\n\\\\n60:begin\\\\nspi_sck<=0;\\\\nspi_csn<=1;\\\\nstate<=state+1;\\\\nend\\\\n\\\\n61:begin\\\\nspi_sck<=0;\\\\nspi_csn<=1;\\\\nstate<=state+1;\\\\nend\\\\n\\\\n62:begin\\\\nspi_sck<=0;\\\\nspi_csn<=1;\\\\nstate<=state+1;\\\\nend\\\\n\\\\n\\\\n63:begin\\\\nspi_csn<=0;\\\\nspi_sck<=0;\\\\nstate<=state+1;\\\\nend\\\\n\\\\n\\\\n\\\\n64:begin\\\\nspi_csn<=0;\\\\nspi_sck<=0;\\\\nspi_mosi<=SETUP_RETR_W[reg_count-1]; // Configuration of SETUP_RETR REGISTER for Setting up of Automatic Retransmission\\\\nreg_count<=reg_count-1;\\\\nstate<=state+1;\\\\nend\\\\n\\\\n65:begin\\\\n\\\\nspi_sck<=1;\\\\nif(reg_count>0) // SHIFTING 8 BIT DATA THROUGH SPI\\\\nbegin\\\\nstate<=64;\\\\nend\\\\n\\\\nelse\\\\n\\\\nbegin\\\\nspi_sck<=1;\\\\nspi_csn<=0;\\\\nstate<=state+1;\\\\nreg_count<=8;\\\\nend\\\\nend\\\\n\\\\n66:begin\\\\nif(countm==5) //DELAY BETWEEN data given into SETUP_RETR Register\\\\nbegin\\\\ncountm<=0;\\\\nstate<=state+1;\\\\nend\\\\nelse\\\\ncountm<=countm+1;\\\\nspi_sck<=0;\\\\nend\\\\n\\\\n67:begin\\\\n\\\\nspi_sck<=0;\\\\nspi_mosi<=SETUP_RETR_value[reg_count-1]; // writing data into SETUP_RETR Register\\\\nreg_count<=reg_count-1;\\\\nstate<=state+1;\\\\nend\\\\n\\\\n68:begin\\\\n\\\\nspi_sck<=1;\\\\nif(reg_count>0) // SHIFTING 8 BIT DATA THROUGH SPI\\\\nbegin\\\\nstate<=67;\\\\nend\\\\n\\\\nelse\\\\n\\\\nbegin\\\\nspi_sck<=1;\\\\nspi_csn<=0;\\\\nstate<=state+1;\\\\nreg_count<=8;\\\\nend\\\\nend\\\\n\\\\n69:begin\\\\nif(countm==5) //DELAY for next configuration register\\\\nbegin\\\\ncountm<=0;\\\\nstate<=state+1;\\\\nend\\\\nelse\\\\ncountm<=countm+1;\\\\nspi_sck<=0;\\\\nend\\\\n\\\\n\\\\n\\\\n70:begin\\\\nspi_sck<=0;\\\\nspi_csn<=1;\\\\nstate<=state+1;\\\\nend\\\\n\\\\n71:begin\\\\nspi_sck<=0;\\\\nspi_csn<=1;\\\\nstate<=state+1;\\\\nend\\\\n\\\\n72:begin\\\\nspi_sck<=0;\\\\nspi_csn<=1;\\\\nstate<=state+1;\\\\nend\\\\n\\\\n\\\\n73:begin\\\\nspi_csn<=0;\\\\nspi_sck<=0;\\\\nstate<=state+1;\\\\nend\\\\n\\\\n\\\\n\\\\n\\\\n\\\\n74:begin\\\\nspi_csn<=0;\\\\nspi_sck<=0;\\\\nspi_mosi<=RX_PW_P0_W[reg_count-1]; // Configuration of RX_PW_P0 REGISTER TO set RX payload width\\\\nreg_count<=reg_count-1;\\\\nstate<=state+1;\\\\nend\\\\n\\\\n75:begin\\\\n\\\\nspi_sck<=1;\\\\nif(reg_count>0) // SHIFTING 8 BIT DATA THROUGH SPI\\\\nbegin\\\\nstate<=74;\\\\nend\\\\n\\\\nelse\\\\n\\\\nbegin\\\\nspi_sck<=1;\\\\nspi_csn<=0;\\\\nstate<=state+1;\\\\nreg_count<=8;\\\\nend\\\\nend\\\\n\\\\n76:begin\\\\nif(countm==5) //DELAY BETWEEN data given into RX_PW_P0 Register\\\\nbegin\\\\ncountm<=0;\\\\nstate<=state+1;\\\\nend\\\\nelse\\\\ncountm<=countm+1;\\\\nspi_sck<=0;\\\\nend\\\\n\\\\n77:begin\\\\n\\\\nspi_sck<=0;\\\\nspi_mosi<=RX_PW_P0_value[reg_count-1]; // writing data into RX_PW_P0 Register (1 byte)\\\\nreg_count<=reg_count-1;\\\\nstate<=state+1;\\\\nend\\\\n\\\\n78:begin\\\\n\\\\nspi_sck<=1;\\\\nif(reg_count>0) // SHIFTING 8 BIT DATA THROUGH SPI\\\\nbegin\\\\nstate<=77;\\\\nend\\\\n\\\\nelse\\\\n\\\\nbegin\\\\nspi_sck<=1;\\\\nspi_csn<=0;\\\\nstate<=state+1;\\\\nreg_count<=8;\\\\nend\\\\nend\\\\n\\\\n79:begin\\\\nif(countm==5) //DELAY for next configuration register\\\\nbegin\\\\ncountm<=0;\\\\nstate<=state+1;\\\\nend\\\\nelse\\\\ncountm<=countm+1;\\\\nspi_sck<=0;\\\\nend\\\\n\\\\n80:begin\\\\nspi_sck<=0;\\\\nspi_csn<=1;\\\\nstate<=state+1;\\\\nend\\\\n\\\\n81:begin\\\\nspi_sck<=0;\\\\nspi_csn<=1;\\\\nstate<=state+1;\\\\nend\\\\n\\\\n82:begin\\\\nspi_sck<=0;\\\\nspi_csn<=1;\\\\nstate<=state+1;\\\\nend\\\\n\\\\n\\\\n83:begin\\\\nspi_csn<=0;\\\\nspi_sck<=0;\\\\nstate<=state+1;\\\\nend\\\\n\\\\n\\\\n84:begin\\\\nspi_csn<=0;\\\\nspi_sck<=0;\\\\nspi_mosi<=RX_ADDR_P0_W[reg_count-1]; // Configuration of RX_ADDR_PO WHICH IS EQUAL TO tx_addr address\\\\nreg_count<=reg_count-1;\\\\nstate<=state+1;\\\\nend\\\\n\\\\n85:begin\\\\n\\\\nspi_sck<=1;\\\\nif(reg_count>0) // SHIFTING 8 BIT DATA THROUGH SPI\\\\nbegin\\\\nstate<=84;\\\\nend\\\\n\\\\nelse\\\\n\\\\nbegin\\\\nspi_sck<=1;\\\\nspi_csn<=0;\\\\nstate<=state+1;\\\\nreg_count<=8;\\\\nend\\\\nend\\\\n\\\\n86:begin\\\\nif(countm==5) //DELAY BETWEEN data given into TX_ADDR Register\\\\nbegin\\\\ncountm<=0;\\\\nstate<=state+1;\\\\nend\\\\nelse\\\\ncountm<=countm+1;\\\\nspi_sck<=0;\\\\nend\\\\n\\\\n87:begin\\\\n\\\\nspi_sck<=0;\\\\nspi_mosi<=rx_address[reg_count-1]; // writing address into RX_ADDR_P0 Register (1 byte 5 times)(ED_ED_ED_ED_ED=TX_ADDR)\\\\nreg_count<=reg_count-1;\\\\nstate<=state+1;\\\\nend\\\\n\\\\n88:begin\\\\n\\\\nspi_sck<=1;\\\\nif(reg_count>0) // SHIFTING 8 BIT DATA THROUGH SPI\\\\nbegin\\\\nstate<=87;\\\\nend\\\\n\\\\nelse\\\\n\\\\nbegin\\\\nspi_sck<=1;\\\\nspi_csn<=0;\\\\nstate<=state+1;\\\\nreg_count<=8;\\\\nend\\\\nend\\\\n\\\\n\\\\n\\\\n\\\\n89:begin\\\\nif(countm==4) //for 40 bit addressing ,this loop is used 5 times for RX_ADDRESS=ED\\\\nbegin\\\\ncountm<=0;\\\\nstate<=state+1;\\\\nend\\\\nelse\\\\nbegin\\\\ncountm<=countm+1;\\\\nspi_sck<=0;\\\\nstate<=87; //repetation till 40 bit RX Address address is completed\\\\nend\\\\nend\\\\n\\\\n\\\\n90:begin\\\\nif(countm==5) //DELAY for next configuration register\\\\nbegin\\\\ncountm<=0;\\\\nstate<=state+1;\\\\nend\\\\nelse\\\\nbegin\\\\ncountm<=countm+1;\\\\nspi_sck<=0;\\\\nend\\\\nend\\\\n\\\\n\\\\n\\\\n91:begin\\\\nspi_sck<=0;\\\\nspi_csn<=1;\\\\nstate<=state+1;\\\\nend\\\\n\\\\n92:begin\\\\nspi_sck<=0;\\\\nspi_csn<=1;\\\\nstate<=state+1;\\\\nend\\\\n\\\\n93:begin\\\\nspi_sck<=0;\\\\nspi_csn<=1;\\\\nstate<=state+1;\\\\nend\\\\n\\\\n\\\\n94:begin\\\\nspi_csn<=0;\\\\n//spi_ce<=0;\\\\nspi_sck<=0;\\\\nstate<=state+1;\\\\nend\\\\n\\\\n\\\\n\\\\n95:begin\\\\nspi_csn<=0;\\\\nspi_sck<=0;\\\\nstate<=state+1;\\\\nend\\\\n\\\\n96:begin\\\\nspi_csn<=0;\\\\nspi_sck<=0;\\\\nspi_mosi<=FLUSH_RX[reg_count-1]; // flush RX fifo which removeS all the data from RX FIFO permanently\\\\nreg_count<=reg_count-1;\\\\nstate<=state+1;\\\\nend\\\\n\\\\n97:begin\\\\n\\\\nspi_sck<=1;\\\\nif(reg_count>0) // SHIFTING 8 BIT DATA THROUGH SPI\\\\nbegin\\\\nstate<=96;\\\\nend\\\\n\\\\nelse\\\\n\\\\nbegin\\\\nspi_sck<=1;\\\\nspi_csn<=0;\\\\nstate<=state+1;\\\\nreg_count<=8;\\\\nend\\\\nend\\\\n\\\\n\\\\n\\\\n98:begin\\\\nif(countm==5) //Delay for next configuration\\\\nbegin\\\\ncountm<=0;\\\\nstate<=state+1;\\\\nend\\\\nelse\\\\ncountm<=countm+1;\\\\nspi_sck<=0;\\\\nend\\\\n\\\\n\\\\n\\\\n99:begin\\\\nspi_sck<=0;\\\\nspi_csn<=1;\\\\nstate<=state+1;\\\\nend\\\\n\\\\n100:begin\\\\nspi_sck<=0;\\\\nspi_csn<=1;\\\\nstate<=state+1;\\\\nend\\\\n\\\\n101:begin\\\\nspi_sck<=0;\\\\nspi_csn<=1;\\\\nstate<=state+1;\\\\nend\\\\n\\\\n102:begin\\\\nspi_sck<=0;\\\\nspi_csn<=0;\\\\nstate<=state+1;\\\\nend\\\\n\\\\n\\\\n103:begin\\\\nspi_csn<=0;\\\\nspi_sck<=0;\\\\nspi_mosi<=STATUS_W[reg_count-1]; // Configuration of STATUS REGISTER TO clear all the FLAGS\\\\nreg_count<=reg_count-1;\\\\nstate<=state+1;\\\\nend\\\\n\\\\n104:begin\\\\n\\\\nspi_sck<=1;\\\\nif(reg_count>0) // SHIFTING 8 BIT DATA THROUGH SPI\\\\nbegin\\\\nstate<=103;\\\\nend\\\\n\\\\nelse\\\\n\\\\nbegin\\\\nspi_sck<=1;\\\\nspi_csn<=0;\\\\nstate<=state+1;\\\\nreg_count<=8;\\\\nend\\\\nend\\\\n\\\\n105:begin\\\\nif(countm==5) //DELAY BETWEEN data given into STATUS Register\\\\nbegin\\\\ncountm<=0;\\\\nstate<=state+1;\\\\nend\\\\nelse\\\\ncountm<=countm+1;\\\\nspi_sck<=0;\\\\nend\\\\n\\\\n106:begin\\\\n\\\\nspi_sck<=0;\\\\nspi_mosi<=STATUS_value[reg_count-1]; // writing data into STATUS Register\\\\nreg_count<=reg_count-1;\\\\nstate<=state+1;\\\\nend\\\\n\\\\n107:begin\\\\n\\\\nspi_sck<=1;\\\\nif(reg_count>0) // SHIFTING 8 BIT DATA THROUGH SPI\\\\nbegin\\\\nstate<=106;\\\\nend\\\\n\\\\nelse\\\\n\\\\nbegin\\\\nspi_sck<=1;\\\\nspi_csn<=0;\\\\nstate<=state+1;\\\\nreg_count<=8;\\\\nend\\\\nend\\\\n\\\\n108:begin\\\\nif(countm==5) // DELAY FOR next operartion\\\\nbegin\\\\ncountm<=0;\\\\nstate<=state+1;//////////////////////////////\\\\n//state<=121;\\\\nend\\\\nelse\\\\ncountm<=countm+1;\\\\nspi_sck<=0;\\\\nend\\\\n\\\\n\\\\n\\\\n////////////////////////// TO READ DATA FROM RX_FIFO TX FIFO //////////////////////\\\\n109:begin\\\\nspi_sck<=0;\\\\npayload_count<=payload_count+1; //////////////////////////\\\\nspi_csn<=1;\\\\nstate<=state+1;\\\\nend\\\\n\\\\n110:begin\\\\nspi_sck<=0;\\\\nspi_csn<=1;\\\\nstate<=state+1;\\\\nend\\\\n\\\\n111:begin\\\\nspi_sck<=0;\\\\nspi_csn<=1;\\\\nstate<=state+1;\\\\nend\\\\n\\\\n\\\\n112:begin\\\\nspi_csn<=0;\\\\nspi_sck<=0;\\\\nstate<=state+1;\\\\nend\\\\n\\\\n113:begin\\\\n\\\\nspi_sck<=0;\\\\nspi_mosi<=R_RX_PAYLOAD[reg_count-1]; // Read RX_PAYLOAD command\\\\nreg_count<=reg_count-1;\\\\nstate<=state+1;\\\\nend\\\\n\\\\n114:begin\\\\n\\\\nspi_sck<=1;\\\\nif(reg_count>0) // SHIFTING 8 BIT DATA THROUGH SPI\\\\nbegin\\\\nstate<=113;\\\\nend\\\\n\\\\nelse\\\\n\\\\nbegin\\\\nspi_sck<=1;\\\\nspi_csn<=0;\\\\nstate<=state+1;\\\\nreg_count<=8;\\\\nend\\\\nend\\\\n\\\\n\\\\n115:begin\\\\nspi_sck<=0;\\\\nspi_csn<=0;\\\\nstate<=state+1;\\\\nend\\\\n\\\\n116:begin\\\\nspi_sck<=0;\\\\nspi_csn<=0;\\\\nstate<=state+1;\\\\n//payload_count<=payload_count+1;\\\\nend\\\\n\\\\n\\\\n117:begin\\\\n\\\\nspi_sck<=0;\\\\nspi_mosi<=payload1[reg_count-1]; // give any 1 byte data (as WIDTH OF PAYLOAD was set to 1 Byte IN TX and RX)\\\\nreg_count<=reg_count-1;\\\\nstate<=state+1;\\\\n\\\\nend\\\\n\\\\n118:begin\\\\n\\\\nspi_sck<=1;\\\\nif(reg_count>0) // SHIFTING 8 BIT DATA THROUGH SPI\\\\nbegin\\\\nstate<=117;\\\\nend\\\\n\\\\nelse\\\\n\\\\nbegin\\\\nspi_sck<=1;\\\\nspi_csn<=0;\\\\nstate<=state+1;\\\\nreg_count<=8;\\\\nend\\\\nend\\\\n\\\\n119:begin\\\\nspi_sck<=0;\\\\nspi_csn<=0;\\\\nstate<=state+1;\\\\nend\\\\n\\\\n\\\\n\\\\n\\\\n120:begin\\\\nif(payload_count<4) /////////////// reading 3 byte payload 1 after another\\\\nbegin///////////////////////\\\\nspi_sck<=0;\\\\nspi_csn<=0;\\\\nstate<=109; // it REPEATES R_RX_PAYLOAD COMMAND to read RX_FIFO 3 TIMES\\\\nend\\\\nelse\\\\nstate<=state+1;\\\\nend\\\\n\\\\n\\\\n\\\\n///////////////OUT OF POWER DOWN MODE/////////////////////////////\\\\n\\\\n121:begin\\\\nif(count_standby==1024) //2 Ms between POWER DOWN and STANDBY MODE controlled by PWR_UP bit\\\\nbegin\\\\ncount_standby<=0;\\\\nstate<=state+1;\\\\nend\\\\nelse\\\\ncount_standby<=count_standby+1;\\\\nspi_sck<=0;\\\\nend\\\\n\\\\n\\\\n122:begin\\\\nspi_sck<=0;\\\\nspi_ce<=1;\\\\nstate<=state+1;\\\\nend\\\\n\\\\n123:begin\\\\n//spi_ce<=1;\\\\nif(ce_count==100) //min CE High=10 us \\\\nbegin\\\\nce_count<=0;\\\\n//state<=state+1;/////////////////////////////////\\\\nstate<=134;\\\\nend\\\\nelse\\\\nce_count<=ce_count+1;\\\\nspi_sck<=0;\\\\nend\\\\n\\\\n\\\\n\\\\n\\\\n\\\\n134:begin\\\\nif(countm==10) //DELAY is providded before reading out NRF returned data\\\\nbegin\\\\ncountm<=0;\\\\nstate<=state+1;\\\\nend\\\\nelse\\\\ncountm<=countm+1;\\\\nspi_sck<=0;\\\\nend\\\\n\\\\n\\\\n135:begin\\\\nspi_sck<=0;\\\\nspi_csn<=0;\\\\nstate<=state+1;\\\\nend\\\\n\\\\n\\\\n136:begin\\\\nspi_sck<=1;\\\\nif(status_clk>0)\\\\nbegin\\\\nnrf_out[status_count-1]<=spi_miso; // NRF returns data stored in RX_FIFO\\\\nstatus_count<=status_count-1;\\\\nstatus_clk<=status_clk-1;\\\\nstate<=135;\\\\nend\\\\nelse\\\\nbegin\\\\nspi_sck<=1;\\\\nstate<=state+1;\\\\nspi_csn<=0;\\\\nend\\\\nend\\\\n\\\\n137:begin\\\\nif(countm==500) // DELAY for next operation\\\\nbegin\\\\ncountm<=0;\\\\nstate<=state+1;\\\\nend\\\\nelse\\\\ncountm<=countm+1;\\\\nspi_sck<=0;\\\\nend\\\\n\\\\n\\\\n138:begin\\\\nspi_sck<=0;\\\\nspi_csn<=1;\\\\nstate<=state+1;\\\\nend\\\\n\\\\n139:begin\\\\nspi_sck<=0;\\\\nspi_csn<=1;\\\\n//state<=109; // to read data continiously from NRF\\\\nstate<=92; \\\\nend\\\\n\\\\n\\\\nendcase\\\\nend\\\\nend\\\\nendmodule"]
['module dff(clock,d,q);\\\\ninput clock, d;\\\\noutput q;\\\\nreg q=0;\\\\nalways @(posedge clock)\\\\nbegin\\\\nq<=d;\\\\nend\\\\nendmodule', 'module dff(clock,d,q);\\\\ninput clock, d;\\\\noutput q;\\\\nreg q=0;\\\\nalways @(posedge clock)\\\\nbegin\\\\nq<=d;\\\\nend\\\\nendmodule', 'module pes_icg (in,clk,d0,d1,q0,q1);\\\\ninput in,d0,d1;\\\\ninput clk;\\\\noutput q0,q1;\\\\n\\\\nreg q0=0;\\\\nreg q1=0;\\\\n//reg q_l=0;\\\\n\\\\nwire cgclk;\\\\nwire n1,n2,n3,n4,n5,clk_n,q_l;\\\\nwire en;\\\\n\\\\ndff dff1 (clk,in,n1);\\\\n\\\\nassign n2 = ~n1;\\\\n//not g1 (n2,n1);\\\\n\\\\nassign n3 = ~n2;\\\\n//not g2 (n3,n2);\\\\n\\\\nassign n4 = ~(n1 & n3);\\\\n//nand g3 (n4,n1,n3);\\\\n\\\\nassign n5 = (n3 & n2);\\\\n//and g4 (n5,n3,n2);\\\\n\\\\nassign en = n4 | n5;\\\\n//or g5 (en,n4,n5);\\\\n\\\\nassign clk_n = ~ clk;\\\\n//not (clk_n, clk);\\\\n\\\\ndff dff2 (clk_n,en,q_l);\\\\n\\\\nassign cgclk = clk & q_l;\\\\n//and (cgclk,clk,q_l);\\\\n\\\\nalways@(posedge cgclk)\\\\nbegin\\\\nq0 <= d0;\\\\nq1 <=d1;\\\\nend\\\\n\\\\nendmodule']
["module pipeline(clock,reset);\\\\n\\\\tinput clock;\\\\n\\\\tinput reset;\\\\n\\\\t//if stage\\\\n\\\\twire [31:0]PC_if;\\\\n\\\\twire RegDst,Jump,Branch,bne,MemRead,MemtoReg,ALUop,MemWrite,ALUSrc,RegWrite;//controlunit\\\\n\\\\twire IFIDWrite,PCWrite,IDFlush;//Hazard detection lw\\\\n\\\\twire [31:0]ReadData1; //= regfile[readReg1];\\\\n\\\\twire [31:0]ReadData2; //= regfile[readReg2];\\\\n\\\\twire [31:0]ReadData;\\\\n\\\\t//reg [4:0]WriteReg;//which register to write back\\\\n\\\\twire [31:0]WriteData;\\\\n\\\\twire [31:0]extendedIm;\\\\n\\\\twire [31:0]ALUsrc2,ALUsrc1; //input of ALU\\\\n\\\\twire [3:0]aluControl;\\\\n\\\\twire [31:0]ALUresult;\\\\n\\\\twire [4:0] WriteReg;\\\\n\\\\twire [31:0]targetPC1,targetPC2;\\\\n\\\\twire [31:0]targetPC;\\\\n\\\\twire [31:0] ReadData2_temp;\\\\n\\\\t//wire ifbranch;\\\\n\\\\t//or gate4(ifbranch,temp1,temp3);\\\\n\\\\twire[31:0] NextPC_if;\\\\n\\\\twire[31:0] Instruction_if;\\\\n\\\\t\\\\n\\\\t//IF/ID wires\\\\n\\\\twire[31:0] NextPC_id;//newPC from previous\\\\n\\\\twire[31:0] Instruction_id;\\\\n\\\\twire[31:0] NextPC_temp;//data hazard lw bubble\\\\n\\\\t/****************************************/\\\\n\\\\t//ID/EX wires\\\\n\\\\twire RegDst_ex,MemRead_ex,MemtoReg_ex,MemWrite_ex,ALUSrc_ex,RegWrite_ex;\\\\n\\\\twire[1:0] ALUop_ex;\\\\n\\\\twire[31:0] Instuction_ex;\\\\n\\\\twire[31:0] ReadData1_ex;\\\\n\\\\twire[31:0] ReadData2_ex;\\\\n\\\\twire[31:0] Extended_ex;\\\\n\\\\twire[4:0] rs_ex;//[25:21]\\\\n\\\\twire[4:0] rt_ex;//[20:16]\\\\n\\\\twire[4:0] rd_ex;//[15:11]\\\\n\\\\twire[1:0] forward1,forward2;\\\\n\\\\t/*****************************************/\\\\n\\\\t//EX/MEM wires\\\\n\\\\twire MemRead_mem,MemtoReg_mem,MemWrite_mem,RegWrite_mem;\\\\n\\\\twire[31:0] ALUresult_mem;\\\\n\\\\twire[31:0] ReadData2_mem;\\\\n\\\\twire[4:0] WriteReg_mem;\\\\n\\\\t/****************************************/\\\\n\\\\t//MEM/WB wires\\\\n\\\\twire MemtoReg_wb,RegWrite_wb;\\\\n\\\\twire[31:0] ALUresult_wb;\\\\n\\\\twire[4:0] WriteReg_wb;//writeback register\\\\n\\\\twire[31:0] ReadData_wb;//data to write back\\\\n\\\\t/****************************************/\\\\n\\\\tmux2_1 mux_pc2(NextPC_if,targetPC,CHmux,targetPC1);\\\\n\\\\tmux2_1 mux_pc1(targetPC1,PC_if,PCWrite,targetPC2);\\\\n\\\\tpc PC_counter(targetPC2,reset,clock,PC_if);\\\\n\\\\tInstructionMemory IM(PC_if,Instruction_if);\\\\n\\\\tmux2_1 mux_Ins(Instruction_if,Instruction_id,IFIDWrite,Instruction_temp);\\\\n\\\\tAdder_32b adder1(PC_if,4,NextPC_if);\\\\n\\\\tmux2_1 mux_Next(NextPC_if,NextPC_id,IFIDWrite,NextPC_temp);\\\\n\\\\t/*****************************************************************************/\\\\t\\\\t\\\\t\\\\t\\\\t\\\\n\\\\t//IF/ID\\\\n\\\\tIF_ID II(clock,reset,IFFlush,NextPC_temp,Instruction_temp,Instruction_id,NextPC_id);\\\\n\\\\tHazard_Detection HD(rt_ex,Instruction_id[25:21],Instruction_id[20:16],MemRead_ex,IDFlush,PCWrite,IFIDWrite);\\\\n\\\\tcontrol controlUnit(Instruction_id[31:26],RegDst,Jump,Branch,bne,MemRead,MemtoReg,ALUop,MemWrite,ALUSrc,RegWrite);\\\\n\\\\tRegFile RF(clock,Instruction_id[25:21],Instruction_id[20:16],WriteReg_wb,WriteData,RegWrite_wb,ReadData1,ReadData2);\\\\n\\\\tsignExtension ImExtend(Instruction_id[15:0],extendedIm);\\\\n\\\\twire [31:0] JumpAddress = {NextPC_id[31:28],Instruction_id[25:0],2'b00};\\\\n\\\\twire [31:0] BranchAddr = NextPC_id + extendedIm*4;\\\\n\\\\tmux2_1 mux_Branch_Jump(BranchAddr,JumpAddress,Jump,targetPC);\\\\n\\\\tControl_Hazard CH(Jump,Branch,bne,WriteReg,WriteReg_mem,MemRead_ex,MemRead_mem,RegWrite_ex,RegWrite_mem,Instruction_id,ReadData1,ReadData2,ReadData,ALUresult,ALUresult_mem,CHmux,IFFlush);\\\\n\\\\t//control hazard\\\\n\\\\t/*******************************************************************************/\\\\n\\\\t//ID/EX\\\\n\\\\tID_EX IE(clock,reset,IDFlush,Instruction_id,ReadData1,ReadData2,extendedIm,RegDst,MemRead,MemtoReg,MemWrite,ALUSrc,RegWrite,ALUop,RegDst_ex,MemRead_ex,MemtoReg_ex,MemWrite_ex,ALUSrc_ex,RegWrite_ex,ALUop_ex,Instuction_ex,ReadData1_ex,ReadData2_ex,Extended_ex,rt_ex,rs_ex,rd_ex);\\\\n\\\\tALUcontrol alu_control(Extended_ex[5:0],ALUop_ex,aluControl);\\\\n\\\\t\\\\n\\\\tmux3_1 mux_alu3_rs(ReadData1_ex,WriteData,ALUresult_mem,forward1,ALUsrc1);\\\\n\\\\t\\\\n\\\\tmux3_1 mux_alu3_rt(ReadData2_ex,WriteData,ALUresult_mem,forward2,ReadData2_temp);\\\\n\\\\t\\\\n\\\\tmux2_1 mux_alu(ReadData2_temp,Extended_ex,ALUSrc_ex,ALUsrc2);\\\\n\\\\n\\\\tmux5bit mux_writeReg(rt_ex,rd_ex,RegDst_ex,WriteReg);\\\\n\\\\t\\\\n\\\\tALU alu_1(ALUsrc1,ALUsrc2,aluControl,ALUresult);\\\\n\\\\t\\\\n\\\\tForwardUnit FU(rt_ex,rs_ex,WriteReg_mem,WriteReg_wb,RegWrite_mem,RegWrite_wb,forward1,forward2);\\\\n\\\\t/**********************************************************************************/\\\\n\\\\t//EX/MEM\\\\n\\\\tEX_MEM EM(clock,reset,MemRead_ex,MemtoReg_ex,MemWrite_ex,RegWrite_ex,ALUresult,ReadData2_temp,WriteReg,MemRead_mem,MemtoReg_mem,MemWrite_mem,RegWrite_mem,ALUresult_mem,ReadData2_mem,WriteReg_mem);\\\\n\\\\t\\\\n\\\\tDataMem DM(clock,ALUresult_mem,ReadData2_mem,MemWrite_mem,MemRead_mem,ReadData);\\\\n\\\\t/***********************************************************************************/\\\\n\\\\t//MEM/WB\\\\n\\\\tMEM_WB MW(clock,reset,MemtoReg_mem,RegWrite_mem,ALUresult_mem,ReadData,WriteReg_mem,MemtoReg_wb,RegWrite_wb,ALUresult_wb,WriteReg_wb,ReadData_wb);\\\\n\\\\t\\\\n\\\\tmux2_1 mux_writeback(ALUresult_wb,ReadData_wb,MemtoReg_wb,WriteData);\\\\n\\\\t\\\\nendmodule"]
["module alu(data_operandA, data_operandB, ctrl_ALUopcode, ctrl_shiftamt, data_result, isNotEqual, isLessThan, overflow);\\\\n\\\\n input [31:0] data_operandA, data_operandB;\\\\n input [4:0] ctrl_ALUopcode, ctrl_shiftamt;\\\\n\\\\n output [31:0] data_result;\\\\n output isNotEqual, isLessThan, overflow;\\\\n\\\\n\\\\t// Bitwise AND\\\\n\\\\t\\\\n\\\\twire [31:0] andWire;\\\\n\\\\t\\\\n\\\\tgenvar i;\\\\n\\\\tgenerate\\\\n\\\\t\\\\tfor (i = 0; i < 32; i = i+1)\\\\n\\\\t\\\\tbegin : bitAND\\\\n\\\\t\\\\t\\\\tand andGate(andWire[i], data_operandA[i], data_operandB[i]);\\\\n\\\\t\\\\tend\\\\n\\\\tendgenerate\\\\n\\\\t\\\\n\\\\t// Bitwise OR\\\\n\\\\t\\\\n\\\\twire [31:0] orWire;\\\\n\\\\t\\\\n\\\\tgenerate\\\\n\\\\t\\\\tfor (i = 0; i < 32; i = i+1)\\\\n\\\\t\\\\tbegin : bitOR\\\\n\\\\t\\\\t\\\\tor orGate(orWire[i], data_operandA[i], data_operandB[i]);\\\\n\\\\t\\\\tend\\\\n\\\\tendgenerate\\\\n\\\\t\\\\n\\\\t// Adder\\\\n\\\\t\\\\n\\\\twire C0, C1;\\\\n\\\\twire w1, w2;\\\\n\\\\twire O1;\\\\n\\\\t\\\\n\\\\twire [31:0] addWire;\\\\n\\\\t\\\\n\\\\tnot not1(w1, ctrl_ALUopcode[2]);\\\\n\\\\tnot not2(w2, ctrl_ALUopcode[1]);\\\\n\\\\tand subCarry(C0, w1, w2, ctrl_ALUopcode[0]);\\\\n\\\\t\\\\n\\\\twire [31:0] opB;\\\\n\\\\t\\\\n\\\\tgenerate\\\\n\\\\tfor (i = 0; i < 32; i = i + 1)\\\\n\\\\tbegin : subtract\\\\n\\\\t\\\\twire w;\\\\n\\\\t\\\\tnot notGate(w, data_operandB[i]);\\\\n\\\\t\\\\tassign opB[i] = C0 ? w : data_operandB[i];\\\\n\\\\tend\\\\n\\\\tendgenerate\\\\n\\\\t\\\\n\\\\tcsa32 csacsa(data_operandA, opB, C0, addWire, C1, O1);\\\\n\\\\t\\\\n\\\\t// Barrel Shifter\\\\n\\\\t\\\\n\\\\t// sll\\\\n\\\\t\\\\n\\\\twire [31:0] s1, s2, s3, s4, s5, s6, s7, s8, s9;\\\\n\\\\twire [31:0] shiftLWire;\\\\n\\\\t\\\\n\\\\tshiftLeft16 sl16(data_operandA, s1);\\\\n\\\\t\\\\n\\\\tassign s2 = ctrl_shiftamt[4] ? s1 : data_operandA;\\\\n\\\\t\\\\n\\\\tshiftLeft8 sl8(s2, s3);\\\\n\\\\t\\\\n\\\\tassign s4 = ctrl_shiftamt[3] ? s3 : s2;\\\\n\\\\t\\\\n\\\\tshiftLeft4 sl4(s4, s5);\\\\n\\\\t\\\\n\\\\tassign s6 = ctrl_shiftamt[2] ? s5 : s4;\\\\n\\\\t\\\\n\\\\tshiftLeft2 sl2(s6, s7);\\\\n\\\\t\\\\n\\\\tassign s8 = ctrl_shiftamt[1] ? s7 : s6;\\\\n\\\\t\\\\n\\\\tshiftLeft1 sl1(s8, s9);\\\\n\\\\t\\\\n\\\\tassign shiftLWire = ctrl_shiftamt[0] ? s9 : s8;\\\\n\\\\t\\\\n\\\\t// sra\\\\n\\\\t\\\\n\\\\twire [31:0] r1, r2, r3, r4, r5, r6, r7, r8, r9;\\\\n\\\\twire [31:0] shiftRWire;\\\\n\\\\t\\\\n\\\\tshiftRight16 sr16(data_operandA, r1);\\\\n\\\\t\\\\n\\\\tassign r2 = ctrl_shiftamt[4] ? r1 : data_operandA;\\\\n\\\\t\\\\n\\\\tshiftRight8 sr8(r2, r3);\\\\n\\\\t\\\\n\\\\tassign r4 = ctrl_shiftamt[3] ? r3 : r2;\\\\n\\\\t\\\\n\\\\tshiftRight4 sr4(r4, r5);\\\\n\\\\t\\\\n\\\\tassign r6 = ctrl_shiftamt[2] ? r5 : r4;\\\\n\\\\t\\\\n\\\\tshiftRight2 sr2(r6, r7);\\\\n\\\\t\\\\n\\\\tassign r8 = ctrl_shiftamt[1] ? r7 : r6;\\\\n\\\\t\\\\n\\\\tshiftRight1 sr1(r8, r9);\\\\n\\\\t\\\\n\\\\tassign shiftRWire = ctrl_shiftamt[0] ? r9 : r8;\\\\t\\\\n\\\\t\\\\n\\\\t// Mux\\\\n\\\\t\\\\n\\\\twire m1, m2, m3, m4, m5, m6, m7, m8;\\\\n\\\\t\\\\n\\\\tnot notm1(m1, ctrl_ALUopcode[2]);\\\\n\\\\tnot notm2(m2, ctrl_ALUopcode[1]);\\\\n\\\\tnot notm3(m3, ctrl_ALUopcode[0]);\\\\n\\\\t\\\\n\\\\t// add or sub opcode\\\\n\\\\t\\\\n\\\\tand addSub(m4, m1, m2);\\\\n\\\\t\\\\n\\\\t// bitwise AND opcode\\\\n\\\\t\\\\n\\\\tand andOP(m5, ctrl_ALUopcode[1], m3);\\\\n\\\\t\\\\n\\\\t// bitwise OR opcode\\\\n\\\\t\\\\n\\\\tand orOP(m6, ctrl_ALUopcode[1], ctrl_ALUopcode[0]);\\\\n\\\\t\\\\n\\\\t// sll opcode\\\\n\\\\t\\\\n\\\\tand sll(m7, ctrl_ALUopcode[2], m3);\\\\n\\\\t\\\\n\\\\t//sra opcode\\\\n\\\\t\\\\n\\\\tand sra(m8, ctrl_ALUopcode[2], ctrl_ALUopcode[0]);\\\\n\\\\t\\\\n\\\\tassign data_result = m5 ? andWire : 32'bz;\\\\n\\\\tassign data_result = m6 ? orWire : 32'bz;\\\\n\\\\tassign data_result = m4 ? addWire : 32'bz;\\\\n\\\\tassign data_result = m7 ? shiftLWire : 32'bz;\\\\n\\\\tassign data_result = m8 ? shiftRWire : 32'bz;\\\\n\\\\t\\\\n\\\\t// isNotEqual\\\\n\\\\t\\\\n\\\\twire [31:0] t;\\\\n\\\\twire t1, t2, t3, t4, t5, t6, t7, t8, t9, t10;\\\\n\\\\t\\\\n\\\\tgenerate\\\\n\\\\tfor (i = 0; i < 32; i = i + 1)\\\\n\\\\tbegin : notEq\\\\n\\\\t\\\\txor xorGate(t[i], data_operandA[i], data_operandB[i]);\\\\n\\\\tend\\\\n\\\\tendgenerate\\\\n\\\\t\\\\n\\\\tor nor1(t1, t[0], t[1], t[2], t[3]);\\\\n\\\\tor nor2(t2, t[8], t[9], t[10], t[11]);\\\\n\\\\tor nor3(t3, t[16], t[17], t[18], t[19]);\\\\n\\\\tor nor4(t4, t[24], t[25], t[26], t[27]);\\\\n\\\\tor por1(t5, t[4], t[5], t[6], t[7]);\\\\n\\\\tor por2(t6, t[12], t[13], t[14], t[15]);\\\\n\\\\tor por3(t7, t[20], t[21], t[22], t[23]);\\\\n\\\\tor por4(t8, t[28], t[29], t[30], t[31]);\\\\n\\\\tor nor6(t9, t1, t2, t3, t4);\\\\n\\\\tor nor7(t10, t5, t6, t7, t8);\\\\n\\\\tor nor5(isNotEqual, t9, t10);\\\\n\\\\t\\\\n\\\\t// isLessThan\\\\n\\\\t\\\\n\\\\twire l1;\\\\n\\\\t\\\\n\\\\tand lt1(l1, O1, data_operandA[31]);\\\\n\\\\tassign isLessThan = O1 ? l1 : data_result[31];\\\\n\\\\t\\\\n\\\\t// overflow\\\\n\\\\t\\\\n\\\\tassign overflow = O1;\\\\n\\\\nendmodule"]
["module lattice_on(clk,start,direction1,direction2,direction3,direction4,row,g_col,r_col);\\\\n\\\\tinput clk;\\\\n\\\\tinput start;\\\\n\\\\tinput direction1;\\\\n\\\\tinput direction2;\\\\n\\\\tinput direction3;\\\\n\\\\tinput direction4;\\\\n\\\\n\\\\toutput reg [7:0] row;\\\\n\\\\toutput reg [7:0] g_col;\\\\n\\\\toutput reg [7:0] r_col;\\\\n\\\\n\\\\treg [2:0] terminal_point_row=3'b000;\\\\n\\\\treg [2:0] terminal_point_col=3'b000;\\\\n\\\\treg [2:0] start_point_row=3'b110;\\\\t\\\\n\\\\treg [2:0] start_point_col=3'b111;\\\\n\\\\treg [5:0] start_point_1=6'b110_111;\\\\t\\\\n\\\\treg [5:0] terminal_point_1=6'b000_000;\\\\n\\\\treg [5:0] start_point_2=6'b111_110;\\\\n\\\\treg [5:0] terminal_point_2=6'b001_111;\\\\n\\\\n\\\\treg [2:0] location_row_num;\\\\n\\\\treg [2:0] location_col_num;\\\\n\\\\n\\\\n\\\\twire start_lock;\\\\n\\\\tsw a1(.clk(clk),.sw(start),.lo_sw(start_lock));\\\\n\\\\t\\\\n\\\\twire direction_lock1;\\\\n\\\\twire direction_lock2;\\\\n\\\\twire direction_lock3;\\\\n\\\\twire direction_lock4;\\\\n\\\\n\\\\t\\\\n\\\\t/*debounce m0(clk,rst,direction1,direction2,direction3,direction4,direction_lock1,direction_lock2,direction_lock3,direction_lock4);\\\\n\\\\t\\\\n\\\\n\\\\talways @(posedge clk)\\\\t//\\\\u7039\\\\u6c2b\\\\u7b9fdirection[0]\\\\u6d93\\\\u54c4\\\\u609c\\\\u6d93\\\\u5a43\\\\u5e36\\\\u9352\\\\u5815\\\\u656dposedge direction_lock1 or posedge direction_lock2 or posedge direction_lock3 or posedge direction_lock4 \\\\n\\\\tbegin\\\\n\\\\n\\\\tif(start_lock==1) begin\\\\n\\\\t\\\\tstep_cnt<=7'b0000000;\\\\n\\\\t\\\\tlocation_row_num<=start_point_row;\\\\n\\\\t\\\\tlocation_col_num<=start_point_col;\\\\n\\\\tend\\\\n\\\\tif(direction_lock1||direction_lock2||direction_lock3||direction_lock4)\\\\tbegin\\\\n\\\\t\\\\tif(location_row_num!=terminal_point_row||location_col_num!=terminal_point_col)\\\\n\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\tif(location_row_num<7 &&direction_lock1)\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tif(!map_row[location_row_num+1][location_col_num])\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tstep_cnt<=step_cnt+1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tlocation_row_num<=location_row_num+1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t\\\\tif(location_row_num>0&&direction_lock2)\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tif(!map_row[location_row_num-1][location_col_num])\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tstep_cnt<=step_cnt+1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tlocation_row_num<=location_row_num-1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\tend\\\\n\\\\t\\\\tif(location_col_num!=terminal_point_col||location_row_num!=terminal_point_row)\\\\n\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\tif(location_col_num>0&&direction_lock3)\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tif(!map_row[location_row_num][location_col_num-1])\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tstep_cnt<=step_cnt+1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tlocation_col_num<=location_col_num-1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t\\\\tif(location_col_num<7&&direction_lock4)\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tif(!map_row[location_row_num][location_col_num+1])\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tstep_cnt<=step_cnt+1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tlocation_col_num<=location_col_num+1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\n\\\\tend\\\\n\\\\n\\\\tend*/\\\\n\\\\t//debounce debounce1(clk,rst,direction1,direction2,direction3,direction4,direction_lock1,direction_lock2,direction_lock3,direction_lock4);\\\\n\\\\tsw c1(clk,direction1,direction_lock1);\\\\n\\\\tsw c2(clk,direction2,direction_lock2);\\\\n\\\\tsw c3(clk,direction3,direction_lock3);\\\\n\\\\tsw c4(clk,direction4,direction_lock4);\\\\n\\\\nalways @(posedge clk or posedge start_lock)\\\\n\\\\tbegin\\\\n\\\\t\\\\tif(start_lock)\\\\n\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\tlocation_row_num<=start_point_row;\\\\n\\\\t\\\\t\\\\t\\\\tlocation_col_num<=start_point_col;\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\t else if(location_row_num!=terminal_point_row||location_col_num!=terminal_point_col) begin\\\\n\\\\n\\\\t if(location_row_num<7 &&direction_lock1)\\\\n\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tlocation_row_num<=location_row_num+1;\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\telse if(location_row_num>0&&direction_lock2)\\\\n\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tlocation_row_num<=location_row_num-1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\telse if(location_col_num>0&&direction_lock3)\\\\n\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tlocation_col_num<=location_col_num-1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\telse if(location_col_num<7&&direction_lock4)\\\\n\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tlocation_col_num<=location_col_num+1;\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\tend\\\\n\\\\tend\\\\n\\\\n\\\\treg [31:0] count=32'd0;\\\\n\\\\treg clk_1kHz;\\\\n\\\\n\\\\talways @(posedge clk) begin //1k\\\\u9891\\\\u7387\\\\u7684\\\\u65f6\\\\u949f\\\\n\\\\t\\\\tif(count==50000) begin\\\\n\\\\t\\\\t\\\\tcount<=32'd0;\\\\n\\\\t\\\\t\\\\tclk_1kHz<=~clk_1kHz;\\\\n\\\\t\\\\tend\\\\n\\\\t\\\\telse begin\\\\n\\\\t\\\\t\\\\tcount<=count+1;\\\\n\\\\t\\\\tend\\\\n\\\\tend\\\\n\\\\n\\\\treg [3:0] row_num=4'b0000; \\\\n\\\\t\\\\n\\\\talways @(posedge clk_1kHz) begin\\\\n\\\\tif(row_num!=4'b0111) begin\\\\n\\\\t\\\\trow_num<=row_num+1;\\\\n\\\\tend\\\\n\\\\telse row_num<=4'b0000;\\\\n\\\\tend\\\\n\\\\n\\\\talways @(posedge clk_1kHz) begin\\\\n\\\\tcase(row_num)\\\\n\\\\t4'h0: begin\\\\n\\\\t\\\\trow<=8'b1111_1110;\\\\n\\\\tend\\\\n\\\\t4'h1: begin\\\\n\\\\t\\\\trow<=8'b1111_1101;\\\\n\\\\tend\\\\n\\\\t4'h2: begin\\\\n\\\\t\\\\trow<=8'b1111_1011;\\\\n\\\\tend\\\\n\\\\t4'h3: begin\\\\n\\\\t\\\\trow<=8'b1111_0111;\\\\n\\\\tend\\\\n\\\\t4'h4: begin\\\\n\\\\t\\\\trow<=8'b1110_1111;\\\\n\\\\tend\\\\n\\\\t4'h5: begin\\\\n\\\\t\\\\trow<=8'b1101_1111;\\\\n\\\\tend\\\\n\\\\t4'h6: begin\\\\n\\\\t\\\\trow<=8'b1011_1111;\\\\n\\\\tend\\\\n\\\\t4'h7: begin\\\\n\\\\t\\\\trow<=8'b0111_1111;\\\\n\\\\tend\\\\n\\\\tendcase\\\\n\\\\tend\\\\n\\\\talways @(posedge clk_1kHz) begin\\\\n\\\\t\\\\tif(row_num==location_row_num) begin\\\\n\\\\t\\\\t\\\\tcase(location_col_num)\\\\n\\\\t\\\\t\\\\t\\\\t3'd0:g_col<=8'b0000_0001;\\\\n\\\\t\\\\t\\\\t\\\\t3'd1:g_col<=8'b0000_0010;\\\\n\\\\t\\\\t\\\\t\\\\t3'd2:g_col<=8'b0000_0100;\\\\n\\\\t\\\\t\\\\t\\\\t3'd3:g_col<=8'b0000_1000;\\\\n\\\\t\\\\t\\\\t\\\\t3'd4:g_col<=8'b0001_0000;\\\\n\\\\t\\\\t\\\\t\\\\t3'd5:g_col<=8'b0010_0000;\\\\n\\\\t\\\\t\\\\t\\\\t3'd6:g_col<=8'b0100_0000;\\\\n\\\\t\\\\t\\\\t\\\\t3'd7:g_col<=8'b1000_0000;\\\\n\\\\t\\\\t\\\\tendcase\\\\n\\\\t\\\\tend\\\\n\\\\t\\\\tif((row_num)!=location_row_num)\\\\n\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\tg_col<=8'b0000_0000;\\\\n\\\\t\\\\tend\\\\n\\\\tend\\\\n\\\\nendmodule"]
["module AESEncryptionMain(\\\\n input clk, reset,\\\\n input [127:0] plaintext, key, //128-bit input and key\\\\n output [127:0] encrypted_text, //128-bit encrypted output\\\\n );\\\\n \\\\nreg [7:0] state_key [3:0][3:0];\\\\n\\\\nKeyStateConvertor convert_1(.clk(clk), .reset(reset), .binary_key(key), .state_key(state_key));\\\\n\\\\n//key state itself is key 0 for round 0 \\\\n//further keys are generated using key 0 and RCON table\\\\nreg [7:0] key_1 [3:0][3:0]; \\\\nreg [7:0] key_2 [3:0][3:0]; \\\\nreg [7:0] key_3 [3:0][3:0]; \\\\nreg [7:0] key_4 [3:0][3:0]; \\\\nreg [7:0] key_5 [3:0][3:0]; \\\\nreg [7:0] key_6 [3:0][3:0]; \\\\nreg [7:0] key_7 [3:0][3:0]; \\\\nreg [7:0] key_8 [3:0][3:0]; \\\\nreg [7:0] key_9 [3:0][3:0]; \\\\nreg [7:0] key_10 [3:0][3:0];\\\\n\\\\nKeyGenerationModule m1(.clk(clk), .reset(reset), .input_key(state_key), .round_key(key_1), .round_number(4'h1));\\\\nKeyGenerationModule m2(.clk(clk), .reset(reset), .input_key(key_1), .round_key(key_2), .round_number(4'h2));\\\\nKeyGenerationModule m3(.clk(clk), .reset(reset), .input_key(key_2), .round_key(key_3), .round_number(4'h3));\\\\nKeyGenerationModule m4(.clk(clk), .reset(reset), .input_key(key_3), .round_key(key_4), .round_number(4'h4));\\\\nKeyGenerationModule m5(.clk(clk), .reset(reset), .input_key(key_4), .round_key(key_5), .round_number(4'h5));\\\\nKeyGenerationModule m6(.clk(clk), .reset(reset), .input_key(key_5), .round_key(key_6), .round_number(4'h6));\\\\nKeyGenerationModule m7(.clk(clk), .reset(reset), .input_key(key_6), .round_key(key_7), .round_number(4'h7));\\\\nKeyGenerationModule m8(.clk(clk), .reset(reset), .input_key(key_7), .round_key(key_8), .round_number(4'h8));\\\\nKeyGenerationModule m9(.clk(clk), .reset(reset), .input_key(key_8), .round_key(key_9), .round_number(4'h9));\\\\nKeyGenerationModule m10(.clk(clk), .reset(reset), .input_key(key_9), .round_key(key_10), .round_number(4'ha));\\\\n\\\\n\\\\n\\\\n\\\\n\\\\nendmodule"]
["module main_com_master(\\\\nclk,\\\\nrst,\\\\nfpga_out,\\\\nfpga_in,\\\\nSstart,\\\\nsync_slave,\\\\ndspace_upper,\\\\nrst_slave,\\\\nfrate_slave,\\\\nVpa,\\\\nVpb,\\\\nVpc,\\\\nfin,\\\\nsw\\\\n);\\\\n\\\\n//parameter dspace_rate = 750;//750 para 15 us casa 250 agrego o quito 5 us\\\\n\\\\nparameter begin_trans = 4'd0;\\\\nparameter send_1 = 4'd1;\\\\nparameter send_2 = 4'd2;\\\\nparameter send_3 = 4'd3;\\\\nparameter send_4 = 4'd4;\\\\nparameter send_5 = 4'd5;\\\\nparameter send_6 = 4'd6;\\\\nparameter end_trans=4'd7;\\\\nparameter other_one=4'd8;\\\\n\\\\n//parameter volt1 =8'd43;//1101_1101\\\\n//parameter volt2 = 8'd86;//0001_1010\\\\n//parameter volt3 = 8'd129;//1000_0111\\\\n//parameter volt4 = 8'd172;//0101_1110\\\\n//parameter volt5 = 8'd215;//0001_0000\\\\n//parameter volt6 = 8'd255;//1111_1000\\\\n\\\\ninput [1:0]sw;\\\\noutput fin;\\\\nreg en1,en2;\\\\nparameter sinc_w = 4'b0000;\\\\nparameter sinc_f = 4'b1111;\\\\n\\\\noutput rst_slave;\\\\ninput [7:0]Vpa,Vpb,Vpc;\\\\nwire [7:0]volt1,volt2,volt3;\\\\n\\\\nassign volt1 = Vpa;\\\\nassign volt2 = Vpb;\\\\nassign volt3 = Vpc;\\\\nreg [10:0]dspace_rate;\\\\nreg [7:0]bit_rate_fpga;\\\\ninput clk,rst,fpga_in;\\\\noutput fpga_out,Sstart,sync_slave,frate_slave;\\\\noutput [3:0] dspace_upper;\\\\nreg frate_slave;\\\\nreg Sstart;\\\\nreg [3:0] dspace_upper;\\\\ninitial dspace_upper = 4'd0;\\\\nreg [3:0] est_com;\\\\ninitial est_com = 4'd0;\\\\n\\\\nreg [10:0] rate_counter;\\\\ninitial rate_counter = 0;\\\\n\\\\nwire flag_rate = (rate_counter == dspace_rate || rst);\\\\nwire Mstart;\\\\nwire beg_flag = (est_com == begin_trans || rst);\\\\nreg s1,s2;\\\\nwire [3:0]rxword1,rxword2,rxword3;\\\\nwire [3:0]txword1,txword2,txword3;\\\\nassign txword1 = volt1[7:4];\\\\nassign txword2 = volt2[7:4];\\\\nassign txword3 = volt3[7:4];\\\\nreg d1,d2,flag_rated;\\\\nreg Mstartd,Mstartd2;\\\\n//Modulo para intercambiar palabras entre fpga superior e inferior\\\\n\\\\nalways@(posedge clk)\\\\ncase(sw)\\\\n0:begin \\\\n\\\\tdspace_rate <= 500; //10us\\\\n\\\\tbit_rate_fpga <= 40;\\\\n end\\\\n1:begin \\\\n\\\\tdspace_rate <= 750; //15us\\\\n\\\\tbit_rate_fpga <= 60;\\\\n end\\\\n2:begin \\\\n\\\\tdspace_rate <= 1000; //20us\\\\n\\\\tbit_rate_fpga <= 75;\\\\n end\\\\n3:begin \\\\n\\\\tdspace_rate <= 1250; //25us\\\\n\\\\tbit_rate_fpga <= 95;\\\\n end\\\\ndefault:\\\\n begin \\\\n\\\\tdspace_rate <= 750; //15us\\\\n\\\\tbit_rate_fpga <= 60;\\\\n end\\\\n endcase\\\\n\\\\n\\\\n\\\\n\\\\n\\\\n\\\\nalways@(posedge clk)\\\\nif(flag_rate)frate_slave<=1;\\\\nelse if(rate_counter==(dspace_rate>>1))frate_slave<=0;\\\\nelse frate_slave<=frate_slave;\\\\n\\\\nalways@(posedge clk)if(est_com == end_trans)en1<=1;else en1<=0;\\\\nalways@(posedge clk)en2<=en1;\\\\nassign fin = !en2&en1;\\\\n\\\\n\\\\nalways@(posedge clk)d1<=flag_rate;\\\\nalways@(posedge clk)d2<=d1;\\\\nalways@(posedge clk)flag_rated<=d2;\\\\n\\\\ndspace_com_master sub_master(\\\\n.clk(clk),\\\\n.rst(rst),\\\\n.fpga_in(fpga_in),\\\\n.fpga_out(fpga_out),\\\\n.reset_slave(rst_slave),\\\\n.Mstart(Mstartd2),\\\\n.sync_slave(sync_slave),\\\\n.rx_w1(rxword1),.rx_w2(rxword2),.rx_w3(rxword3),\\\\n.tx_w1(txword1),.tx_w2(txword2),.tx_w3(txword3),\\\\n.bit_rate_fpga(bit_rate_fpga)\\\\n);\\\\n\\\\nalways@(posedge clk)s1 <= beg_flag;\\\\nalways@(posedge clk)s2 <= s1;\\\\n\\\\nassign Mstart = !s2 && s1;\\\\nalways@(posedge clk)Mstartd<=Mstart;\\\\nalways@(posedge clk)Mstartd2<=Mstartd;\\\\n\\\\n\\\\nalways@(posedge clk)\\\\nif(Mstart)Sstart <= 1;\\\\nelse if(flag_rate) Sstart<=0;\\\\nelse Sstart <= Sstart;\\\\n\\\\nalways@(posedge clk)\\\\nif(rst||rate_counter == dspace_rate||Mstartd2) rate_counter <= 0;\\\\nelse rate_counter <= rate_counter + 1;\\\\n\\\\nalways@(posedge clk)\\\\nif(rst) est_com <= begin_trans;\\\\nelse if(flag_rated)\\\\n\\\\tcase(est_com)\\\\n\\\\t\\\\tbegin_trans:est_com <= send_1;\\\\n\\\\t\\\\tsend_1:est_com <= send_2;\\\\n\\\\t\\\\tsend_2:est_com <= send_3;\\\\n\\\\t\\\\tsend_3:est_com <= send_4;\\\\n\\\\t\\\\tsend_4:est_com <= send_5;\\\\n\\\\t\\\\tsend_5: est_com <= send_6;\\\\n\\\\t\\\\tsend_6:est_com <= end_trans;\\\\n\\\\t\\\\tend_trans:est_com <= other_one;\\\\n\\\\t\\\\tother_one:est_com <= begin_trans;\\\\n\\\\t\\\\tdefault:est_com <= begin_trans;\\\\n\\\\tendcase\\\\n\\\\telse est_com<=est_com;\\\\n\\\\t//Envio a la dspace\\\\nalways@(posedge clk)\\\\nif(flag_rate)\\\\ncase(est_com)\\\\nbegin_trans: dspace_upper <= sinc_w;\\\\nsend_1:dspace_upper <= volt1[3:0]; //Vcpa\\\\nsend_2:dspace_upper <= volt2[3:0]; //Vcpb\\\\nsend_3:dspace_upper <= volt3[3:0]; //Vcpc\\\\nsend_4:dspace_upper <= rxword1;\\\\nsend_5:dspace_upper <= rxword2;\\\\nsend_6:dspace_upper <= rxword3;\\\\nend_trans:dspace_upper <= sinc_f;\\\\nother_one:dspace_upper <= sinc_f;\\\\ndefault:dspace_upper <= sinc_w;\\\\nendcase\\\\nelse \\\\ndspace_upper<=dspace_upper;\\\\nendmodule"]
["module mem_model(clk, addr, data, memrq, rnw);\\\\ninput clk, memrq, rnw;\\\\ninput [11:0] addr;\\\\ninout [15:0] data;\\\\nreg [15:0] mem [4095:0];\\\\nassign data = memrq & rnw ? mem[addr] : 16'hz; // read\\\\n\\\\nalways @(negedge clk) // write\\\\nif (memrq & !rnw) mem[addr] <= data;\\\\n\\\\ninitial begin // program codes start\\\\n mem[0] = {`LDA, 12'h64}; // 0000 0110 0100\\\\n mem[1] = {`SUB, 12'h65};\\\\n mem[2] = {`JNE, 12'h6};\\\\n mem[3] = {`LDA, 12'h64};\\\\n mem[4] = {`ADD, 12'h65};\\\\n mem[5] = {`JMP, 12'h9};\\\\n mem[6] = {`LDA, 12'h64};\\\\n mem[7] = {`SUB, 12'h66};\\\\n mem[8] = {`SUB, 12'h66};\\\\n mem[9] = {`STO, 12'h64};\\\\n mem[10] = {`STP, 12'h0};\\\\n mem['h64] = 16'h4444; // program data start\\\\n mem['h65] = 16'h2222;\\\\n mem['h66] = 16'h1111;\\\\n\\\\nend\\\\nendmodule"]
['module lab7_6(LEDR, HEX0, HEX1, HEX2, HEX3, KEY, SW);\\\\n\\\\tinput[3:0] KEY;\\\\n\\\\tinput[9:0] SW;\\\\n\\\\toutput[6:0] HEX0, HEX1, HEX2, HEX3;\\\\n\\\\toutput[9:0] LEDR;\\\\n\\\\t\\\\n\\\\treg [7:0] A, B, C, D;\\\\n\\\\twire [15:0] X, Y, S, OUT;\\\\n\\\\treg displayResult, displayAC_BD;\\\\n\\\\twire [7:0] AC, BD;\\\\n\\\\t\\\\n\\\\tinitial begin\\\\n\\\\t\\\\tA <= 0;\\\\n\\\\t\\\\tB <= 0;\\\\n\\\\t\\\\tC <= 0;\\\\n\\\\t\\\\tD <= 0;\\\\n\\\\tend\\\\n\\\\t\\\\n\\\\talways @ (posedge KEY[1]) begin\\\\n\\\\t\\\\tif(SW[9]) begin\\\\n\\\\t\\\\t\\\\tif(~SW[8]) begin\\\\n\\\\t\\\\t\\\\t\\\\tif(KEY[2])\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tA <= SW[7:0];\\\\n\\\\t\\\\t\\\\t\\\\telse\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tB <= SW[7:0];\\\\n\\\\t\\\\t\\\\tend else begin\\\\n\\\\t\\\\t\\\\t\\\\tif(KEY[2])\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tC <= SW[7:0];\\\\n\\\\t\\\\t\\\\t\\\\telse\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tD <= SW[7:0];\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\tend\\\\n\\\\tend\\\\n\\\\t\\\\n\\\\talways @ (posedge KEY[3]) begin\\\\n\\\\t\\\\tdisplayResult <= ~displayResult;\\\\n\\\\tend\\\\n\\\\t\\\\n\\\\tassign LEDR[7:0] = SW[7:0];\\\\n\\\\tmultiplexer(A, B, X);\\\\n\\\\tmultiplexer(C, D, Y);\\\\n\\\\tadder(X, Y, LEDR[9], S);\\\\n\\\\t\\\\n\\\\tmux_8bit(A, C, SW[8], AC);\\\\n\\\\tmux_8bit(B, D, SW[8], BD);\\\\n\\\\tmux_16bit({AC, BD}, S, displayResult, OUT);\\\\n\\\\t\\\\n\\\\tconverter(HEX0, OUT[3:0]);\\\\n\\\\tconverter(HEX1, OUT[7:4]);\\\\n\\\\tconverter(HEX2, OUT[11:8]);\\\\n\\\\tconverter(HEX3, OUT[15:12]);\\\\n\\\\t\\\\nendmodule', "module converter(seg, num);\\\\n\\\\t input [3:0] num;\\\\n\\\\t output reg [6:0] seg;\\\\n always @(num) begin\\\\n case (num)\\\\n\\\\t\\\\t\\\\t4'b0000: seg <= 7'b1000000; // 0\\\\n\\\\t\\\\t\\\\t4'b0001: seg <= 7'b1111001; // 1\\\\n\\\\t\\\\t\\\\t4'b0010: seg <= 7'b0100100; // 2\\\\n\\\\t\\\\t\\\\t4'b0011: seg <= 7'b0110000; // 3\\\\n\\\\t\\\\t\\\\t4'b0100: seg <= 7'b0011001; // 4\\\\n\\\\t\\\\t\\\\t4'b0101: seg <= 7'b0010010; // 5\\\\n\\\\t\\\\t\\\\t4'b0110: seg <= 7'b0000010; // 6\\\\n\\\\t\\\\t\\\\t4'b0111: seg <= 7'b1111000; // 7\\\\n\\\\t\\\\t\\\\t4'b1000: seg <= 7'b0000000; // 8\\\\n\\\\t\\\\t\\\\t4'b1001: seg <= 7'b0011000; // 9\\\\n\\\\t\\\\t\\\\t4'b1010: seg <= 7'b0001000; // A\\\\n\\\\t\\\\t\\\\t4'b1011: seg <= 7'b0000000; // B\\\\n\\\\t\\\\t\\\\t4'b1100: seg <= 7'b1000110; // C\\\\n\\\\t\\\\t\\\\t4'b1101: seg <= 7'b1000000; // D\\\\n\\\\t\\\\t\\\\t4'b1110: seg <= 7'b0000110; // E\\\\n\\\\t\\\\t\\\\t4'b1111: seg <= 7'b0001110; // F\\\\n\\\\t\\\\t\\\\tdefault: seg <= 7'b0000000; // \\\\n endcase\\\\n end\\\\nendmodule"]
["module clock_week_day(\\\\ninput Is_Leap_Year,CLK, // clock signal and signal telling if year is leap\\\\ninput [3:0] clock_day,clock_10day,clock_1month,clock_10month,clock_year,clock_decade,clock_century, clock_millenia,\\\\noutput [2:0] weekday);// output\\\\n\\\\nwire [4:0] day; // this represents day\\\\nwire [4:0] month; // this represents month\\\\nwire [6:0] year_2_least_signif;//this is last two digits of year 34 out of 1234\\\\nwire [6:0] year_2_most_signif;//this is most two digits of year 12 out of 1234\\\\n\\\\nassign day = clock_day + clock_10day*10;\\\\nassign month = clock_1month + clock_10month*10;\\\\nassign year_2_least_signif = clock_year + clock_decade*10;\\\\nassign year_2_most_signif = clock_century + clock_millenia*10;\\\\n\\\\nwire [2:0] century_code; // this is century code \\\\n\\\\nassign century_code = // choosing doomsdays based on century\\\\n (year_2_most_signif[1:0]==0) ? 2: // if last two bits of year_2_most_signifis 0, century code is 2\\\\n (year_2_most_signif[1:0]==1) ? 0:// if last two bits of year_2_most_signifis 1, century code is 0\\\\n (year_2_most_signif[1:0]==2) ? 5:// if last two bits of year_2_most_signifis 2, century code is 5\\\\n (year_2_most_signif[1:0]==3) ? 3: 2'bx;// if last two bits of year_2_most_signifis 3, century code is 3\\\\n\\\\nwire [6:0] division_of_year_2_least_signif_by_12; // this is us an integer part of ratio of year_2_least_signif and 12\\\\nwire [6:0] remainder_of_division_of_year_2_least_signif_by_12; // this is us an remainder of ratio of year_2_least_signif and 12\\\\n\\\\nclock_divsion_remainder clock_divsion_remainder00(.CLK(CLK),.dividend(year_2_least_signif),.divisor(12),\\\\n.quotient(division_of_year_2_least_signif_by_12),.remainder(remainder_of_division_of_year_2_least_signif_by_12)); // year by 12\\\\n//year_2_least_signif\\\\n\\\\nwire [6:0] qoution_of_remainder_by_4;// this is us an integer part of ratio of remainder_of_division_of_year_2_least_signif_by_12 and 4\\\\nassign qoution_of_remainder_by_4 = remainder_of_division_of_year_2_least_signif_by_12>>2;\\\\n\\\\nwire [7:0] sum; // this of all four things calculated above\\\\nassign sum = century_code + division_of_year_2_least_signif_by_12 + remainder_of_division_of_year_2_least_signif_by_12 + qoution_of_remainder_by_4;\\\\n\\\\nwire [2:0] Doomsday_of_year; // this is doomsday of the year, remainder of sum/7\\\\nclock_divsion_remainder clock_divsion_remainder01(.CLK(CLK),.dividend(sum),.divisor(7),\\\\n.remainder(Doomsday_of_year)); // find doomsday of the year\\\\n\\\\nreg [4:0] Doomsday_of_month; // this table stores which dates are doomsdays in each month\\\\n\\\\nalways @(month) begin\\\\ncase(month)\\\\n1: Doomsday_of_month <= 3 + Is_Leap_Year;\\\\n2: Doomsday_of_month <= 28 + Is_Leap_Year;\\\\n3: Doomsday_of_month <= 14;\\\\n4: Doomsday_of_month <= 4;\\\\n5: Doomsday_of_month <= 9;\\\\n6: Doomsday_of_month <= 6;\\\\n7: Doomsday_of_month <= 11;\\\\n8: Doomsday_of_month <= 8;\\\\n9: Doomsday_of_month <= 5;\\\\n10: Doomsday_of_month <= 10;\\\\n11: Doomsday_of_month <= 7;\\\\n12: Doomsday_of_month <= 12;\\\\ndefault: Doomsday_of_month <= 'bx;\\\\nendcase\\\\nend\\\\n\\\\nreg [6:0] difference; // difference of Doomsday_of_year and day. Only value withouth sign. This is always positive\\\\n//wire [2:0] remainder;\\\\nalways @(Doomsday_of_year or day) begin\\\\nif(Doomsday_of_month>day) \\\\ndifference = Doomsday_of_month-day+Doomsday_of_year;\\\\nelse\\\\ndifference = day-Doomsday_of_month+Doomsday_of_year;\\\\nend\\\\n\\\\n// remainder of difference / 7 is weekday\\\\nclock_divsion_remainder clock_divsion_remainder10(.CLK(CLK),.dividend(difference),.divisor(7),\\\\n.remainder(weekday));\\\\n\\\\n\\\\nendmodule"]
['module pratica21(KEY, SW, LW);\\\\n\\\\tinput [17:00]SW;\\\\n\\\\tinput [2:0]KEY;\\\\n\\\\toutput [17:00]LW;\\\\n\\\\tassign LW[15:0]=SW[15:0];\\\\n\\\\tassign LW[17]=SW[17];\\\\n\\\\twire [4:0]n;\\\\n\\\\twire [15:0]DataIN;\\\\n\\\\twire [15:0] Bus;\\\\n\\\\twire WREN;\\\\n\\\\twire done;\\\\n\\\\t\\\\n\\\\tassign WREN = 1;\\\\n\\\\n\\\\t//KEY[0] = Resetn\\\\n\\\\t//KEY[1] = MClock\\\\n\\\\t//KEY[2] = PClock\\\\n\\\\t//SW[17] = Run\\\\n\\\\t//SW[14:0] = Dado a ser escrito\\\\n\\\\t//LW[16:0] = DONE\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t//MClock |Resetn\\\\n\\\\tcounter Contador(KEY[1], KEY[0], n);\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t//MClock //dado\\\\n\\\\tmemory Memoria(n, KEY[1], SW[15:0], WREN, DataIN);\\\\n\\\\n\\\\tprocessor Processador(KEY[2], DataIN, KEY[0], SW[17], Bus, Done);\\\\n\\\\n\\\\tassign LW[16] = Done;\\\\n\\\\nendmodule']
['module halfsum(a,b,s0,s1);\\\\n\\\\tinput a;\\\\n\\\\tinput b;\\\\n\\\\toutput s0;\\\\n\\\\toutput s1;\\\\n\\\\treg s0;\\\\n\\\\treg s1;\\\\n\\\\twire nota;\\\\n\\\\twire notb;\\\\n\\\\twire andb1;\\\\n\\\\twire andb2;\\\\n\\\\tnot NOT1(nota,a);\\\\n\\\\tnot NOT2(notb,b);\\\\n\\\\tand AND1(s1,a,b);\\\\n\\\\tand AND2(andb1,nota,b);\\\\n\\\\tand AND3(andb2,a,notb);\\\\n\\\\tor OR(s1,andb1,andb2);\\\\nendmodule', 'module fulladder(a,b,c,s0,s1);\\\\n\\\\tinput a,b,c;\\\\n\\\\toutput s0,s1;\\\\n\\\\treg s0,s1;\\\\n\\\\twire so1,so2,so3,so4;\\\\n\\\\thalfsum SOMA1(a,b,so1,so2);\\\\t\\\\n\\\\thalfsum SOMA2(c,so1,s0,so3);\\\\n\\\\thalfsum SOMA3(so2,so1,so4,s1);\\\\nendmodule', 'module fulladder4bits(a,b,s0,s1);\\\\n\\\\tinput[4:0] a,b;\\\\n\\\\toutput[4:0] s0;\\\\n\\\\toutput s1;\\\\n\\\\treg[4:0] s0;\\\\n\\\\treg s1;\\\\n\\\\twire sum1,sum2,sum3,sum4,sum5;\\\\n\\\\t\\\\n\\\\thalfsum SOMA1(a[0],b[0],s0[0],sum1);\\\\n\\\\tfulladder SOMA2(a[1],b[1],sum1,s0[1],sum2);\\\\n\\\\tfulladder SOMA3(a[2],b[2],sum2,so[2],sum3);\\\\n\\\\tfulladder SOMA3(a[3],b[3],sum3,so[3],s1);\\\\nendmodule', 'module halfsub(a,b,s0,s1);\\\\n\\\\tinput a,b;\\\\n\\\\toutput s0,s1;\\\\n\\\\treg s0,s1;\\\\n\\\\twire nota,notb,and1,and2;\\\\n\\\\t\\\\n\\\\tnot NOT1(nota,a);\\\\n\\\\tnot NOT2(notb,b);\\\\n\\\\tand AND1(and1,nota,b);\\\\n\\\\tand AND2(and2,a,notb);\\\\n\\\\ts1 = and1;\\\\n\\\\tor OR(s0,and1,and2);\\\\nendmodule', 'module fullsub(a,b,c,s0,s1);\\\\n\\\\tinput a,b,c;\\\\n\\\\toutput s0,s1;\\\\n\\\\treg s0,s1;\\\\n\\\\twire sub1,sub2,sub3;\\\\n\\\\t\\\\n\\\\thalfsub SUB1(a,b,sub1,sub2);\\\\n\\\\thalfsub SUB2(sub1,c,s0,sub3);\\\\n\\\\tor OR(s1,sub2,sub1);\\\\nendmodule', 'module fullsub4bits(a,b,s0,s1);\\\\n\\\\tinput[4:0] a,b;\\\\n\\\\toutput[4:0] s0;\\\\n\\\\toutput s1;\\\\n\\\\treg[4:0] s0;\\\\n\\\\treg s1;\\\\n\\\\twire sub1,sub2,sub3;\\\\n\\\\thalfsub SUB1(a[0],b[0],s0[0],sub1);\\\\n\\\\thalfsub SUB2(a[1],b[1],sub1,s0[1],sub2);\\\\n\\\\thalfsub SUB3(a[2],b[2],sub2,s0[2],sub3);\\\\n\\\\thalfsub SUB4(a[3],b[3],sub3,s0[3],s1);\\\\nendmodule', 'module igualdade(a,b,s);\\\\n\\\\tinput[4:0] a,b;\\\\n\\\\toutput s;\\\\n\\\\treg s;\\\\n\\\\twire or1,or2;\\\\n\\\\treg[4:0] respsub1;\\\\n\\\\treg respsub2;\\\\n\\\\tfullsub4bits SUB(a,b,respsub1,respsub2);\\\\n\\\\tor OR1(or1,respsub1[0],respsub1[1]);\\\\n\\\\tor OR2(or2,respsub1[2],respsub1[3]);\\\\n\\\\tor OR3(or3,or1,or2);\\\\n\\\\tor OR4(or4,or3,respsub2);\\\\n\\\\tnot NOT(s,or4);\\\\nendmodule', 'module desiguladade(a,b,maior,menor,igual);\\\\n\\\\tinput[4:0] a,b;\\\\n\\\\toutput maior,menor,igual;\\\\n\\\\treg maior,menor,igual;\\\\n\\\\twire[4:0] valor;\\\\n\\\\twire vaium;\\\\n\\\\twire or1,or2,or3,or4;\\\\n\\\\twire notor,notvu;\\\\n\\\\tfullsub SUB(a,b,valor,vaium);\\\\n\\\\tor OR1(or1,valor[0],valor[1]);\\\\n\\\\tor OR2(or2,valor[2],valor[3]);\\\\n\\\\tor OR3(or3,valor[3],or1);\\\\n\\\\tor OR4(or4,or2,or3);\\\\n\\\\tand AND1(menor,vaium,or4);\\\\n\\\\tnot NOTOR(igual,or4);\\\\n\\\\tnot NOTVU(notvu,vaium);\\\\n\\\\tand AND2(maior,or4,notvu);\\\\nendmodule', 'module complemento1(a,s);\\\\n\\\\tinput[4:0] a;\\\\n\\\\toutput s;\\\\n\\\\treg[4:0] s;\\\\n\\\\tnot NOT1(s[0],a[0]);\\\\n\\\\tnot NOT2(s[1],a[1]);\\\\n\\\\tnot NOT3(s[2],a[2]);\\\\n\\\\tnot NOT4(s[3],a[3]);\\\\nendmodule', "module complemento2(a,s);\\\\n\\\\tinput[4:0] a;\\\\n\\\\toutput s;\\\\n\\\\treg[4:0] s;\\\\n\\\\twire[4:0] c1,soma;\\\\n\\\\twire vaium;\\\\n\\\\tsoma = 4'b0001;\\\\n\\\\tcomplemento1 COMPLEMENTO1(a,c1);\\\\n\\\\tfulladder4bits SOMA(a,b,s,vaium);\\\\nendmodule", 'module lu(a,b,maior,menor,igual,c1a,c1b,c2a,c2b);\\\\n\\\\tinput[4:0] a,b;\\\\n\\\\toutput maior,menor,igual,c1a,c1b,c2a,c2b;\\\\n\\\\treg maior,menor,igual;\\\\n\\\\treg[4:0] c1a,c1b,c2a,c2b;\\\\n\\\\tdesigualdade DESIGUALDADE(a,b,maior,menor,igual);\\\\n\\\\tcomplemento1 C1A(a,c1a);\\\\n\\\\tcomplemento1 C1B(b,c1b);\\\\n\\\\tcomplemento2 C2A(a,c2a);\\\\n\\\\tcomplemento2 C2B(b,c2b);\\\\nendmodule']
['module snake(w,a,s,d,out1,out2,row,col,clk,rst);\\\\n\\\\n//\\\\u6700\\\\u5916\\\\u5708\\\\u6c38\\\\u9060\\\\u4eae\\\\uff0c\\\\u5be6\\\\u969b\\\\u63a7\\\\u5236\\\\u7bc4\\\\u570d\\\\u70ba(1,1)~(6,6)\\\\n\\\\ninput w,a,s,d,clk,rst;\\\\noutput [7:0]row,col;//snake\\\\noutput [6:0]out1,out2;//length of snake\\\\nwire [1:0]dirc;//use 0~3 to represent wasd\\\\n\\\\nwire [5:0]len;\\\\nwire div10000,div12500000;\\\\nwire [7:0] rand0,rand1;\\\\n\\\\n//two div_clk\\\\ndiv10000 v0(\\\\n\\\\t.clk(clk),//I\\\\n\\\\t.rst(rst),//I\\\\n\\\\t.div_clk(div10000)//O\\\\n);\\\\ndiv12500000 v1(\\\\n\\\\t.clk(clk),//I\\\\n\\\\t.rst(rst),//I\\\\n\\\\t.div_clk(div12500000)//O\\\\n);\\\\n\\\\n//generate two rand number\\\\nrand_number v2(\\\\n\\\\t.clk(div12500000),//I\\\\n\\\\t.rst(rst),//I\\\\n\\\\t.rand0(rand0),//O\\\\n\\\\t.rand1(rand1)//O\\\\n);\\\\n\\\\n//control direction\\\\nchangeDirec u0(\\\\n\\\\t.up(w),//I\\\\n\\\\t.left(a),//I\\\\n\\\\t.down(s),//I\\\\n\\\\t.right(d),//I\\\\n\\\\t.direction(dirc),//O\\\\n);\\\\n\\\\n//control snake and output\\\\nmove u1(\\\\n\\\\t.clk10000(div10000),//I\\\\n\\\\t.clk12500000(div12500000),//I\\\\n\\\\t.direction(dirc),//I\\\\n\\\\t.rst(rst),//I\\\\n\\\\t.rand0(rand0),//I\\\\n\\\\t.rand1(rand1),//I\\\\n\\\\t.len(len),//O\\\\n\\\\t.dot_row(row),//O\\\\n\\\\t.dot_col(col)//O\\\\n);\\\\n\\\\n//output length of snake\\\\nseven d0(\\\\n\\\\t.len(len),//I\\\\n\\\\t.out1(out1),//O\\\\n\\\\t.out2(out2),//O\\\\n\\\\t.clk(div12500000),//I\\\\n);\\\\n\\\\n\\\\nendmodule']
['module counter_to_decoder(clkup,up,down,reset,tcount,clk,pcount,wtime1,wtime2,full_flag,empty_flag);\\\\n \\\\n input clkup,up,down,reset,clk;\\\\n input [1:0]tcount;\\\\n output full_flag,empty_flag;\\\\n output [6:0]pcount,wtime1,wtime2;\\\\n \\\\n wire [7:0]wtime;\\\\n wire [3:0]count;\\\\n \\\\n counter counter1(clk,up,down,reset,count,full_flag,empty_flag);\\\\n rom rom1(count,tcount,wtime);\\\\n decoder_to_7seg decode1(count[3],count[2],count[1],count[0],pcount[6],pcount[5],pcount[4],pcount[3],pcount[2],pcount[1],pcount[0]);\\\\n decoder_to_7seg decode2(wtime[3],wtime[2],wtime[1],wtime[0],wtime1[6],wtime1[5],wtime1[4],wtime1[3],wtime1[2],wtime1[1],wtime1[0]);\\\\n decoder_to_7seg decode3(wtime[7],wtime[6],wtime[5],wtime[4],wtime2[6],wtime2[5],wtime2[4],wtime2[3],wtime2[2],wtime2[1],wtime2[0]);\\\\n \\\\nendmodule', "module counter_to_decoder_dut();\\\\n \\\\n reg clkup,up,down,clk,reset;\\\\n reg [1:0] tcount;\\\\n \\\\n wire [6:0] pcount; //output on sevensegment 1\\\\n wire [6:0]wtime1; //output on sevensegment 2\\\\n wire [6:0]wtime2; //output on sevensegment 3\\\\n wire full_flag, empty_flag;\\\\n \\\\n initial\\\\n begin\\\\n clk = 0;\\\\n tcount = 2'b01;//tailer equal 1\\\\n clkup = 0;\\\\n up= 1;\\\\n down=0;\\\\n reset=1; #100;//reset is on and delay 100\\\\n reset=0;//reset is off\\\\n tcount=2'b01;\\\\n end\\\\n \\\\n always\\\\n #50\\\\n clkup = ~clkup;\\\\n always\\\\n #900\\\\n up= ~up; //up =1 after 900 down=0\\\\n always\\\\n #900\\\\n down= ~down; //down =0 after 900 down=1\\\\n always\\\\n #50\\\\n clk = ~clk;\\\\n \\\\n counter_to_decoder top(clkup,up,down,reset,tcount,clk,pcount,wtime1,wtime2,full_flag,empty_flag);\\\\n \\\\nendmodule"]
['module Top_Mod (input [63:0] plaintext, input[79:0] inkey,\\\\n input clk,input R,input ED,\\\\n output reg [63:0] output_text\\\\n\\\\t\\\\t);\\\\n\\\\nwire [63:0] text;\\\\nwire [63:0] dectext;\\\\nwire [79:0] key;\\\\nwire [79:0] deckey;\\\\nwire [4:0] RC_out;\\\\nwire [4:0] decRC_out;\\\\nwire [63:0] regtext;\\\\nwire [79:0] regkey;\\\\nwire [4:0] i;\\\\nwire [4:0] RC;\\\\nwire [63:0] ciphertext;\\\\n\\\\nwire [63:0] out_text;\\\\n\\\\n\\\\nReg_update reg1 (plaintext ,text,dectext, inkey ,key,deckey,clk, R,ED,RC_out,decRC_out,regtext, regkey,i,RC);\\\\n\\\\ntext_update tex1 (regtext,regkey[63:0],i,text,ciphertext);\\\\n\\\\nkey_update kep1(regkey, RC, key);\\\\n\\\\nkey_updatedec kepd1(regkey,RC,deckey);\\\\n\\\\ntext_updatedec textdec1 (regtext,deckey[63:0],i,dectext,out_text);\\\\n\\\\nRCupdate RCp1 (RC,RC_out);\\\\n\\\\nRCUpdatedec RCpd1 (RC,decRC_out);\\\\n\\\\nalways @(*) begin\\\\nif (ED == 1) output_text = ciphertext;\\\\nelse output_text = out_text;\\\\nend\\\\n\\\\nendmodule']
["module Uart(sysclk,clk,reset,RX_DATA,TX_DATA,UART_CON,UART_SIGNAL,TX_EN,UART_RX,UART_TX); // Controller\\\\n input [7:0] TX_DATA; // data to be sent\\\\n input [4:0] UART_CON;\\\\n input sysclk;\\\\n\\\\tinput TX_EN;\\\\n\\\\tinput UART_RX;\\\\n input clk, reset;\\\\n\\\\twire sampleclk;\\\\n\\\\toutput UART_TX;\\\\n output [7:0] RX_DATA;// data received\\\\n output [1:0] UART_SIGNAL; // 0-RX_STATUS, 1-TX_STATUS, 2-TX_EN\\\\n\\\\t\\\\n BRG baud1(.sysclk(sysclk),.sampleclk(sampleclk));\\\\n Sender sender1(.sampleclk(sampleclk),.TX_DATA(TX_DATA),.TX_EN(TX_EN),.TX_STATUS(UART_SIGNAL[1]),.UART_TX(UART_TX));\\\\n Receiver receiver1(.sampleclk(sampleclk),.RX_DATA(RX_DATA),.UART_RX(UART_RX),.RX_STATUS(UART_SIGNAL[0]),.reset(reset));\\\\n\\\\n always@(posedge sampleclk or negedge reset) begin\\\\n if(~reset) begin\\\\n // RX_DATA <= 8'b0;\\\\n // UART_SIGNAL <= 3'b0;\\\\n end\\\\n // else if(UART_SIGNAL[2]) // sending request\\\\n\\\\t\\\\t\\\\t//UART_SIGNAL[2] <= UART_SIGNAL[1];\\\\n end\\\\nendmodule"]
["module MPY(clk, a, b, product);\\\\n input clk;\\\\n input [3:0] a, b;\\\\n output [7:0] p;\\\\n wire [4:0] add0, add1, add2, add3;\\\\n wire [7:0] add0_ext;\\\\n wire [6:0] add1_ext;\\\\n wire [5:0] add2_ext;\\\\n\\\\n wire [6:0] s0;\\\\n wire [5:0] s1;\\\\n wire [4:0] s2;\\\\n booth_add booth1(a, {b[0],1'b0}, add0);\\\\n booth_add booth2(a, b[1:0], add1);\\\\n booth_add booth3(a, b[2:1], add2);\\\\n booth_add booth4(a, b[3:2], add3);\\\\n\\\\n assign add0_ext = {{3{add0[4]}},add0};\\\\n assign add1_ext = {{2{add1[4]}},add1};\\\\n assign add2_ext = {add2[4],add2};\\\\n\\\\n HA1FA6 HA1FA6_u1(clk, add0_ext[7:1], add1_ext, s0);\\\\n HA1FA5 HA1FA5_u1(clk, s0[6:1], add2_ext, s1);\\\\n HA1FA4 HA1FA4_u1(clk, s1[5:1], add3, s2);\\\\n\\\\n assign p[0] = add0_ext[0];\\\\n assign p[1] = s0[0];\\\\n assign p[2] = s1[0];\\\\n assign p[7:3] = s2;\\\\nendmodule", "module booth_add(a, b, ab);\\\\n input [3:0] a;\\\\n input [1:0] b;\\\\n wire signed [4:0] a_ext;\\\\n output [4:0] ab;\\\\n\\\\n assign a_ext = {a[3],a};\\\\n assign ab = (b==2'b01) ? a_ext:\\\\n (b==2'b10) ? -a_ext:\\\\n 5'b0; \\\\nendmodule", 'module HA1FA6(clk, a, b, s);\\\\n input clk;\\\\n input [6:0] a;\\\\n input [6:0] b;\\\\n output [6:0] s;\\\\n\\\\n wire [6:0] carry;\\\\n wire cout;\\\\n HA HA1(clk,a[0],b[0],s[0],carry[0]);\\\\n FA FA1(clk,a[1],b[1],carry[0],s[1],carry[1]);\\\\n FA FA2(clk,a[2],b[2],carry[1],s[2],carry[2]);\\\\n FA FA3(clk,a[3],b[3],carry[2],s[3],carry[3]);\\\\n FA FA4(clk,a[4],b[4],carry[3],s[4],carry[4]);\\\\n FA FA5(clk,a[5],b[5],carry[4],s[5],carry[5]);\\\\n FA FA6(clk,a[6],b[6],carry[5],s[6],carry[6]);\\\\n\\\\n assign cout = carry[6];\\\\nendmodule', 'module HA1FA5(clk, a, b, s);\\\\n input clk;\\\\n input [5:0] a;\\\\n input [5:0] b;\\\\n output [5:0] s;\\\\n\\\\n wire [5:0] carry;\\\\n wire cout;\\\\n HA HA1(clk,a[0],b[0],s[0],carry[0]);\\\\n FA FA1(clk,a[1],b[1],carry[0],s[1],carry[1]);\\\\n FA FA2(clk,a[2],b[2],carry[1],s[2],carry[2]);\\\\n FA FA3(clk,a[3],b[3],carry[2],s[3],carry[3]);\\\\n FA FA4(clk,a[4],b[4],carry[3],s[4],carry[4]);\\\\n FA FA5(clk,a[5],b[5],carry[4],s[5],carry[5]);\\\\n\\\\n assign cout = carry[5];\\\\nendmodule', 'module HA1FA4(clk, a, b, s);\\\\n input clk;\\\\n input [4:0] a;\\\\n input [4:0] b;\\\\n output [4:0] s;\\\\n\\\\n wire [4:0] carry;\\\\n wire cout;\\\\n HA HA1(clk,a[0],b[0],s[0],carry[0]);\\\\n FA FA1(clk,a[1],b[1],carry[0],s[1],carry[1]);\\\\n FA FA2(clk,a[2],b[2],carry[1],s[2],carry[2]);\\\\n FA FA3(clk,a[3],b[3],carry[2],s[3],carry[3]);\\\\n FA FA4(clk,a[4],b[4],carry[3],s[4],carry[4]);\\\\n\\\\n assign cout = carry[4];\\\\nendmodule']
['module clockcount(count, clock, clr);\\\\n input clock, clr;\\\\n output[7:0] count;\\\\n\\\\n //counting to 32, but just in case ill make counter go up to 8 bits\\\\n\\\\n wire o0, o1, o2, o3, o4, o5, o6, o7, i0, i1, i2, i3, i4, i5, i6, i7;\\\\n wire one;\\\\n assign one = 1;\\\\n\\\\n //counter rationale, take tff which flips on clock edge if high input, so this is like constructing truth table where lsb flips every cycle, 2nd lsb flips every two cycles, etc... up to msb\\\\n\\\\n tffe tff0(o0, clock, one, clr);\\\\n tffe tff1(o1, clock, i0, clr);\\\\n tffe tff2(o2, clock, i1, clr);\\\\n tffe tff3(o3, clock, i2, clr);\\\\n tffe tff4(o4, clock, i3, clr);\\\\n tffe tff5(o5, clock, i4, clr);\\\\n tffe tff6(o6, clock, i5, clr);\\\\n tffe tff7(o7, clock, i6, clr);\\\\n\\\\n\\\\n\\\\n and a0(i0, o0, one);\\\\n and a1(i1, o1, i0);\\\\n and a2(i2, o2, i1);\\\\n and a3(i3, o3, i2);\\\\n and a4(i4, o4, i3);\\\\n and a5(i5, o5, i4);\\\\n and a6(i6, o6, i5);\\\\n and a7(i7, o7, i6);\\\\n\\\\n assign count = {o7, o6, o5, o4, o3, o2, o1, o0};\\\\n\\\\n \\\\n\\\\nendmodule']
['module OR2(input A1,input A2,output Out);\\\\n/************Out = A1 or A2**************/\\\\n//wire NA1,NA2;\\\\n//not U1 (NA1,A1);\\\\n//not U2 (NA2,A2);\\\\n//nand U3 (Out,NA1,NA2);\\\\n//endmodule', 'module OR4(input [3:0]A,output Out);\\\\n//wire AA1,AA2;\\\\n//OR2 U1(.A1(A[0]),.A2(A[1]),.Out(AA1));\\\\n//OR2 U2(.A1(A[2]),.A2(A[3]),.Out(AA2));\\\\n//OR2 U3(.A1(AA1),.A2(AA2),.Out(Out));\\\\n//endmodule', 'module OR32(input [31:0] A, output [3:0] ORA, output [3:0] ORB);\\\\nwire OR4A[7:0];\\\\n\\\\ngenvar gi;\\\\ngenerate\\\\nfor(gi = 0; gi < 8; gi=gi+1) begin : OR4LOOP\\\\n//OR4 UOR4(A[3+gi*4:gi*4], OR4A[gi]);\\\\nassign OR4A[gi] = A[gi*4]|A[gi*4+1]|A[gi*4+2]|A[gi*4+3];\\\\nend\\\\nendgenerate\\\\n\\\\ngenerate\\\\nfor(gi = 0; gi < 4; gi=gi+1) begin : OR2LOOP\\\\n//OR2 UOR2A(OR4A[gi*2],OR4A[gi*2+1], ORA[gi]);\\\\n//OR2 UOR2B(OR4A[(gi*2+1)%8],OR4A[(gi*2+2)%8], ORB[gi]);\\\\nassign ORA[gi] = OR4A[gi*2]|OR4A[gi*2+1];\\\\nassign ORB[gi] = OR4A[(gi*2+1)%8]|OR4A[(gi*2+2)%8];\\\\nend\\\\nendgenerate\\\\n\\\\nendmodule', "module TOT_fineEncoder_core\\\\n(\\\\n input [31:0] encode_In,\\\\n input [2:0] level,//proper values of level ={1,2,3}\\\\n output[4:0] Binary_Out,\\\\n output errorFlag\\\\n);\\\\n\\\\n/*************************************/\\\\n\\\\twire [31:0] encode_In;\\\\n\\\\twire [3:0] ORA;\\\\n\\\\twire [3:0] ORB;\\\\n//\\\\twire[2:0] SumORA,SumORB;\\\\n\\\\twire[7:0] LSB8bCode;\\\\n\\\\twire[2:0] LSB3b;\\\\n\\\\twire[1:0] MSB2b;\\\\n \\\\twire MSBerror,LSBerror;\\\\n\\\\twire[2:0] offset;\\\\n\\\\treg MSBerrorA,MSBerrorB;\\\\n\\\\treg[1:0] MSB2bA,MSB2bB;\\\\n \\\\treg[7:0] LSB8bCodeA,LSB8bCodeB;\\\\n\\\\n\\\\t\\\\t\\\\n\\\\tOR32 U_OR32(.A(encode_In),.ORA(ORA),.ORB(ORB));\\\\n\\\\nalways @ (encode_In or ORA or ORB)\\\\nbegin\\\\t\\\\t\\\\n\\\\tcase(ORA)\\\\n\\\\t\\\\t4'b0001: begin MSBerrorA=0; MSB2bA=0; LSB8bCodeA=encode_In[7:0]; end \\\\n\\\\t\\\\t4'b0010: begin MSBerrorA=0; MSB2bA=1; LSB8bCodeA=encode_In[15:8]; end \\\\n\\\\t\\\\t4'b0100: begin MSBerrorA=0; MSB2bA=2; LSB8bCodeA=encode_In[23:16]; end\\\\n\\\\t\\\\t4'b1000: begin MSBerrorA=0; MSB2bA=3; LSB8bCodeA=encode_In[31:24]; end\\\\n\\\\t\\\\tdefault: begin MSBerrorA=0; MSB2bA=0; LSB8bCodeA=8'b00000000; end //wrong data\\\\t\\\\t\\\\n\\\\tendcase\\\\n\\\\t\\\\n\\\\tcase(ORB)\\\\n\\\\t\\\\t4'b0001: begin MSBerrorB=0; MSB2bB=0; LSB8bCodeB=encode_In[11:4]; end \\\\n\\\\t\\\\t4'b0010: begin MSBerrorB=0; MSB2bB=1; LSB8bCodeB=encode_In[19:12]; end \\\\n\\\\t\\\\t4'b0100: begin MSBerrorB=0; MSB2bB=2; LSB8bCodeB=encode_In[27:20]; end\\\\n\\\\t\\\\t4'b1000: begin MSBerrorB=0; MSB2bB=3; LSB8bCodeB={encode_In[3:0],encode_In[31:28]}; end\\\\n\\\\t\\\\tdefault: begin MSBerrorB=0; MSB2bB=0; LSB8bCodeB=8'b00000000; end //wrong data\\\\t\\\\t\\\\t\\\\t\\\\t\\\\n\\\\tendcase\\\\t\\\\t\\\\t\\\\nend\\\\n\\\\n\\\\tassign MSB2b = (MSBerrorA==1'b0)?MSB2bA:MSB2bB;\\\\n\\\\tassign LSB8bCode = (MSBerrorA==1'b0)?LSB8bCodeA:LSB8bCodeB;\\\\n\\\\tassign offset = (MSBerrorA==1'b0)?3'b000:3'b100;\\\\n\\\\tassign MSBerror = MSBerrorA & MSBerrorB;\\\\n\\\\n/*************************************/ \\\\t \\\\nencode8b3b encode8\\\\n(\\\\n\\\\t.encode_In(LSB8bCode),\\\\n\\\\t.level(level),\\\\n\\\\t.Binary_Out(LSB3b),\\\\n\\\\t.error(LSBerror)\\\\n);\\\\t \\\\n\\\\n/*************************************/ \\\\n\\\\tassign errorFlag = (LSBerror == 1'b1)|(MSBerror == 1'b1);\\\\n\\\\tassign Binary_Out =(errorFlag == 1)? 5'b00000:({MSB2b,LSB3b}+offset);\\\\n/*************************************/\\\\n\\\\t \\\\nendmodule"]
["module tb_or1200_rf_top();\\\\n\\\\nparameter aw = 5; //`OR1200_REGFILE_ADDR_WIDTH;\\\\nparameter dw = 32;// `OR1200_OPERAND_WIDTH;\\\\n\\\\nreg clk;\\\\nreg rst;\\\\nreg supv;\\\\nreg wb_freeze;\\\\nreg [aw-1:0] addrw;\\\\nreg [dw-1:0] dataw;\\\\nreg we;\\\\nreg we2;\\\\nreg flushpipe;\\\\n\\\\nreg [aw-1:0] addrw2;\\\\nreg [dw-1:0] dataw2;\\\\n\\\\nreg id_freeze;\\\\nreg [aw-1:0] addra;\\\\nreg [aw-1:0] addrb;\\\\nwire [dw-1:0] dataa;\\\\nwire [dw-1:0] datab;\\\\nreg rda;\\\\nreg rdb;\\\\n\\\\nreg [aw-1:0] addra2;\\\\nreg [aw-1:0] addrb2;\\\\nwire [dw-1:0] dataa2;\\\\nwire [dw-1:0] datab2;\\\\nreg rda2;\\\\nreg rdb2;\\\\n\\\\nreg spr_cs;\\\\nreg spr_write;\\\\nreg [31:0] spr_addr;\\\\nreg [31:0] spr_dat_i;\\\\nwire [31:0] spr_dat_o;\\\\n\\\\nwire[2:0] current_thread_read_out;\\\\nreg[2:0] current_thread_read;\\\\nreg[2:0] current_thread_write;\\\\n\\\\n\\\\nor1200_rf_top or1200_rf_top(.clk(clk), .rst(rst), .supv(supv), \\\\n .wb_freeze(wb_freeze), .current_thread_read(current_thread_read),\\\\n .addrw(addrw), .dataw(dataw), .addrw2(addrw2), .dataw2(dataw2), .we(we),\\\\n .we2(we2), .flushpipe (flushpipe), .id_freeze(id_freeze), .addra(addra),\\\\n .addrb(addrb), .dataa(dataa), .datab(datab), .rda(rda), .rdb(rdb),\\\\n .addra2(addra2), .addrb2(addrb2), .dataa2(dataa2), \\\\n .datab2(datab2), .rda2(rda2), .rdb2(rdb2), .spr_cs(spr_cs), \\\\n .spr_write(spr_write), .spr_addr(spr_addr), .spr_dat_i(spr_dat_i), \\\\n .spr_dat_o(spr_dat_o), .current_thread_read_out(current_thread_read_out),\\\\n .current_thread_write(current_thread_write));\\\\n\\\\ninitial begin\\\\n #0\\\\tclk=0;\\\\n\\\\trst=0;\\\\n\\\\n\\\\n #10\\\\trst=1;\\\\n current_thread_write=3'bX;\\\\n #10\\\\trst=0;\\\\n\\\\twb_freeze=0;\\\\n\\\\tflushpipe=0;\\\\n\\\\tspr_cs=0;\\\\n\\\\tspr_addr=32'b0;\\\\n\\\\tspr_write=0;\\\\n\\\\taddrw =5'd1;\\\\n\\\\taddrw2=5'd2;\\\\n\\\\twe=1;\\\\n\\\\twe2=1;\\\\n\\\\trda=0;\\\\n\\\\trda2=0;\\\\n\\\\tsupv=1;\\\\n\\\\tdataw =32'h12345678;\\\\n\\\\tdataw2 =32'h90ABCDEF;\\\\n\\\\tcurrent_thread_write = 3'b0;\\\\n\\\\n #10 id_freeze=0;\\\\n \\\\n #20\\\\tspr_write=0;\\\\n\\\\tid_freeze=0;\\\\n\\\\twe=0;\\\\n\\\\twe2=0;\\\\n\\\\trda=1;\\\\n\\\\trda2=1;\\\\n\\\\taddra=5'd1;\\\\n\\\\taddra2=5'd2;\\\\n\\\\tcurrent_thread_read=3'd0;\\\\n\\\\n #20\\\\trst=0;\\\\n\\\\twb_freeze=0;\\\\n\\\\tflushpipe=0;\\\\n\\\\tspr_cs=0;\\\\n\\\\tspr_addr[10:5]=6'b0;\\\\n\\\\tspr_write=0;\\\\n\\\\taddrw =5'd13;\\\\n\\\\taddrw2=5'd14;\\\\n rda=0;\\\\n\\\\trda2=0;\\\\n\\\\twe=1;\\\\n\\\\twe2=1;\\\\n\\\\tsupv=1;\\\\n\\\\tdataw =32'h23456789;\\\\n\\\\tdataw2 =32'h0ABCDEF1;\\\\n\\\\tcurrent_thread_write=3'd0;\\\\n\\\\n #20\\\\tspr_write=0;\\\\n\\\\tid_freeze=0;\\\\n\\\\twe=0;\\\\n\\\\twe2=0;\\\\n\\\\trdb=1;\\\\n\\\\trdb2=1;\\\\n\\\\taddrb=5'd13;\\\\n\\\\taddrb2=5'd14;\\\\n\\\\tcurrent_thread_read=3'd0;\\\\n\\\\n #10\\\\trst=0;\\\\n\\\\twb_freeze=0;\\\\n\\\\tflushpipe=0;\\\\n\\\\tspr_cs=0;\\\\n\\\\tspr_addr=32'b0;\\\\n\\\\tspr_write=0;\\\\n\\\\taddrw =5'd1;\\\\n\\\\taddrw2=5'd2;\\\\n\\\\twe=1;\\\\n\\\\twe2=1;\\\\n\\\\trda=0;\\\\n\\\\trda2=0;\\\\n\\\\tsupv=1;\\\\n\\\\tdataw =32'h12345678;\\\\n\\\\tdataw2 =32'h90ABCDEF;\\\\n current_thread_write=3'd1;\\\\n\\\\n #10 id_freeze=0;\\\\n \\\\n #20\\\\tspr_write=0;\\\\n\\\\tid_freeze=0;\\\\n\\\\twe=0;\\\\n\\\\twe2=0;\\\\n\\\\trda=1;\\\\n\\\\trda2=1;\\\\n\\\\taddra=5'd1;\\\\n\\\\taddra2=5'd2;\\\\n current_thread_read=3'd1;\\\\n\\\\n #20\\\\trst=0;\\\\n\\\\twb_freeze=0;\\\\n\\\\tflushpipe=0;\\\\n\\\\tspr_cs=0;\\\\n\\\\tspr_addr[10:5]=6'b0;\\\\n\\\\tspr_write=0;\\\\n\\\\taddrw =5'd13;\\\\n\\\\taddrw2=5'd14;\\\\n rda=0;\\\\n\\\\trda2=0;\\\\n\\\\twe=1;\\\\n\\\\twe2=1;\\\\n\\\\tsupv=1;\\\\n\\\\tdataw =32'h23456789;\\\\n\\\\tdataw2 =32'h0ABCDEF1;\\\\n\\\\tcurrent_thread_write=3'd1;\\\\n\\\\n #20\\\\tspr_write=0;\\\\n\\\\tid_freeze=0;\\\\n\\\\twe=0;\\\\n\\\\twe2=0;\\\\n\\\\trdb=1;\\\\n\\\\trdb2=1;\\\\n\\\\taddrb=5'd13;\\\\n\\\\taddrb2=5'd14;\\\\n current_thread_read=3'd1;\\\\n\\\\n #10\\\\trst=0;\\\\n\\\\twb_freeze=0;\\\\n\\\\tflushpipe=0;\\\\n\\\\tspr_cs=0;\\\\n\\\\tspr_addr=32'b0;\\\\n\\\\tspr_write=0;\\\\n\\\\taddrw =5'd1;\\\\n\\\\taddrw2=5'd2;\\\\n\\\\twe=1;\\\\n\\\\twe2=1;\\\\n\\\\trda=0;\\\\n\\\\trda2=0;\\\\n\\\\tsupv=1;\\\\n\\\\tdataw =32'h11111112;\\\\n\\\\tdataw2 =32'h2AAAAAAA;\\\\n\\\\tcurrent_thread_write=3'd2;\\\\n\\\\n #10 id_freeze=0;\\\\n \\\\n #20\\\\tspr_write=0;\\\\n\\\\tid_freeze=0;\\\\n\\\\twe=0;\\\\n\\\\twe2=0;\\\\n\\\\trda=1;\\\\n\\\\trda2=1;\\\\n\\\\taddra=5'd1;\\\\n\\\\taddra2=5'd2;\\\\n\\\\tcurrent_thread_read=3'd2;\\\\n\\\\n #20\\\\trst=0;\\\\n\\\\twb_freeze=0;\\\\n\\\\tflushpipe=0;\\\\n\\\\tspr_cs=0;\\\\n\\\\tspr_addr[10:5]=6'b0;\\\\n\\\\tspr_write=0;\\\\n\\\\taddrw =5'd13;\\\\n\\\\taddrw2=5'd14;\\\\n rda=0;\\\\n\\\\trda2=0;\\\\n\\\\twe=1;\\\\n\\\\twe2=1;\\\\n\\\\tsupv=1;\\\\n\\\\tdataw =32'h31111111;\\\\n\\\\tdataw2 =32'h3BBBBBBB;\\\\n\\\\tcurrent_thread_write=3'd2;\\\\n\\\\n #20\\\\tspr_write=0;\\\\n\\\\tid_freeze=0;\\\\n\\\\twe=0;\\\\n\\\\twe2=0;\\\\n\\\\trdb=1;\\\\n\\\\trdb2=1;\\\\n\\\\taddrb=5'd13;\\\\n\\\\taddrb2=5'd14;\\\\n\\\\tcurrent_thread_read=3'd2;\\\\n\\\\n #10\\\\trst=0;\\\\n\\\\twb_freeze=0;\\\\n\\\\tflushpipe=0;\\\\n\\\\tspr_cs=0;\\\\n\\\\tspr_addr=32'b0;\\\\n\\\\tspr_write=0;\\\\n\\\\taddrw =5'd1;\\\\n\\\\taddrw2=5'd2;\\\\n\\\\twe=1;\\\\n\\\\twe2=1;\\\\n\\\\trda=0;\\\\n\\\\trda2=0;\\\\n\\\\tsupv=1;\\\\n\\\\tdataw =32'h43333333;\\\\n\\\\tdataw2 =32'h4CCCCCCC;\\\\n\\\\tcurrent_thread_write=3'd3;\\\\n\\\\n #10 id_freeze=0;\\\\n \\\\n #20\\\\tspr_write=0;\\\\n\\\\tid_freeze=0;\\\\n\\\\twe=0;\\\\n\\\\twe2=0;\\\\n\\\\trda=1;\\\\n\\\\trda2=1;\\\\n\\\\taddra=5'd1;\\\\n\\\\taddra2=5'd2;\\\\n\\\\tcurrent_thread_read=3'd3;\\\\n\\\\n #20\\\\trst=0;\\\\n\\\\twb_freeze=0;\\\\n\\\\tflushpipe=0;\\\\n\\\\tspr_cs=0;\\\\n\\\\tspr_addr[10:5]=6'b0;\\\\n\\\\tspr_write=0;\\\\n\\\\taddrw =5'd13;\\\\n\\\\taddrw2=5'd14;\\\\n rda=0;\\\\n\\\\trda2=0;\\\\n\\\\twe=1;\\\\n\\\\twe2=1;\\\\n\\\\tsupv=1;\\\\n\\\\tdataw =32'h23456789;\\\\n\\\\tdataw2 =32'h0ABCDEF1;\\\\n\\\\tcurrent_thread_write=3'd3;\\\\n\\\\n #20\\\\tspr_write=0;\\\\n\\\\tid_freeze=0;\\\\n\\\\twe=0;\\\\n\\\\twe2=0;\\\\n\\\\trdb=1;\\\\n\\\\trdb2=1;\\\\n\\\\taddrb=5'd13;\\\\n\\\\taddrb2=5'd14;\\\\n\\\\tcurrent_thread_read=3'd3;\\\\n\\\\n #10\\\\trst=0;\\\\n\\\\twb_freeze=0;\\\\n\\\\tflushpipe=0;\\\\n\\\\tspr_cs=0;\\\\n\\\\tspr_addr=32'b0;\\\\n\\\\tspr_write=0;\\\\n\\\\taddrw =5'd1;\\\\n\\\\taddrw2=5'd2;\\\\n\\\\twe=1;\\\\n\\\\twe2=1;\\\\n\\\\trda=0;\\\\n\\\\trda2=0;\\\\n\\\\tsupv=1;\\\\n\\\\tdataw =32'h12345678;\\\\n\\\\tdataw2 =32'h90ABCDEF;\\\\n\\\\tcurrent_thread_write=3'd4;\\\\n\\\\n #10 id_freeze=0;\\\\n \\\\n #20\\\\tspr_write=0;\\\\n\\\\tid_freeze=0;\\\\n\\\\twe=0;\\\\n\\\\twe2=0;\\\\n\\\\trda=1;\\\\n\\\\trda2=1;\\\\n\\\\taddra=5'd1;\\\\n\\\\taddra2=5'd2;\\\\n\\\\tcurrent_thread_read=3'd4;\\\\n\\\\n #20\\\\trst=0;\\\\n\\\\twb_freeze=0;\\\\n\\\\tflushpipe=0;\\\\n\\\\tspr_cs=0;\\\\n\\\\tspr_addr[10:5]=6'b0;\\\\n\\\\tspr_write=0;\\\\n\\\\taddrw =5'd13;\\\\n\\\\taddrw2=5'd14;\\\\n rda=0;\\\\n\\\\trda2=0;\\\\n\\\\twe=1;\\\\n\\\\twe2=1;\\\\n\\\\tsupv=1;\\\\n\\\\tdataw =32'h01323434;\\\\n\\\\tdataw2 =32'h23389321;\\\\n\\\\tcurrent_thread_write=3'd4;\\\\n\\\\n #20\\\\tspr_write=0;\\\\n\\\\tid_freeze=0;\\\\n\\\\twe=0;\\\\n\\\\twe2=0;\\\\n\\\\trdb=1;\\\\n\\\\trdb2=1;\\\\n\\\\taddrb=5'd13;\\\\n\\\\taddrb2=5'd14;\\\\n\\\\tcurrent_thread_read=3'd4;\\\\n\\\\n #10\\\\trst=0;\\\\n\\\\twb_freeze=0;\\\\n\\\\tflushpipe=0;\\\\n\\\\tspr_cs=0;\\\\n\\\\tspr_addr=32'b0;\\\\n\\\\tspr_write=0;\\\\n\\\\taddrw =5'd1;\\\\n\\\\taddrw2=5'd2;\\\\n\\\\twe=1;\\\\n\\\\twe2=1;\\\\n\\\\trda=0;\\\\n\\\\trda2=0;\\\\n\\\\tsupv=1;\\\\n\\\\tdataw =32'h13456782;\\\\n\\\\tdataw2 =32'h9AABCDEF;\\\\n\\\\tcurrent_thread_write=3'd5;\\\\n\\\\n #10 id_freeze=0;\\\\n \\\\n #20\\\\tspr_write=0;\\\\n\\\\tid_freeze=0;\\\\n\\\\twe=0;\\\\n\\\\twe2=0;\\\\n\\\\trda=1;\\\\n\\\\trda2=1;\\\\n\\\\taddra=5'd1;\\\\n\\\\taddra2=5'd2;\\\\n\\\\tcurrent_thread_read=3'd5;\\\\n\\\\n #20\\\\trst=0;\\\\n\\\\twb_freeze=0;\\\\n\\\\tflushpipe=0;\\\\n\\\\tspr_cs=0;\\\\n\\\\tspr_addr[10:5]=6'b0;\\\\n\\\\tspr_write=0;\\\\n\\\\taddrw =5'd13;\\\\n\\\\taddrw2=5'd14;\\\\n rda=0;\\\\n\\\\trda2=0;\\\\n\\\\twe=1;\\\\n\\\\twe2=1;\\\\n\\\\tsupv=1;\\\\n\\\\tdataw =32'h34567829;\\\\n\\\\tdataw2 =32'h0ABCDE1F;\\\\n\\\\tcurrent_thread_write=3'd5;\\\\n\\\\n #20\\\\tspr_write=0;\\\\n\\\\tid_freeze=0;\\\\n\\\\twe=0;\\\\n\\\\twe2=0;\\\\n\\\\trdb=1;\\\\n\\\\trdb2=1;\\\\n\\\\taddrb=5'd13;\\\\n\\\\taddrb2=5'd14;\\\\n\\\\tcurrent_thread_read=3'd5;\\\\nend\\\\n\\\\nalways #5 clk = ~clk;\\\\nendmodule"]
['module Datapath(\\\\n input CLK,\\\\n input Reset,\\\\n output [31:0] Dout\\\\n);\\\\n\\\\n //internal wire\\\\n //wire <define by user> <btw there are 5 of them :ded:>\\\\n //but heres just 2 of them\\\\n //PC\\\\n wire [31:0] PC_Add_out, PC_Out, Inst_out, S, T;\\\\n wire [31:0] ALUOut;\\\\n wire RegWrite;\\\\n wire [3:0] ALUCntl;\\\\n wire C, V, N, Z;\\\\n //instantiate PC\\\\n PC pc(.CLK(CLK), .Reset(Reset), .Din(PC_Add_out), .PC_Out(PC_Out));\\\\n\\\\n //instatiate instruction memory\\\\n Instruction_Memory im(.Addr(PC_Out), .Inst_out(Inst_out));\\\\n\\\\n //instantiate all the other modules. Good fucking luck!\\\\n\\\\n PC_ADD pcadd(.Din(PC_Out),.PC_Add_out(PC_Add_out));\\\\n\\\\n CNTL control(.Op(Inst_out[31:26]), .Func(Inst_out[5:0]), .RegWrite(RegWrite), .ALUCntl(ALUCntl));\\\\n\\\\n ALU alu(.A(S), .B(T), .ALUCntl(ALUCntl), .ALUOut(Dout), .C(C), .N(N), .V(V), .Z(Z));\\\\n\\\\n //Instantiate regfile\\\\n regfile32 rf(.CLK(CLK), .Reset(Reset), .D_En(RegWrite), .D_Addr(Inst_out[15:11]), .S_Addr(Inst_out[25:21]), .T_Addr(Inst_out[20:16]), .D(Dout), .S(S), .T(T));\\\\n\\\\n //then at the end, only Dout from ALUOut will be the one that outputs\\\\n assign Dout = ALUOut;\\\\n\\\\nendmodule']
["module csa_16(Sum, Cout, overflow, A, B, Cin);\\\\n\\\\tinput [15:0] A, B;\\\\n\\\\tinput Cin;\\\\n\\\\toutput [15:0] Sum;\\\\n\\\\toutput Cout, overflow;\\\\n\\\\t\\\\n\\\\twire [7:0] Sum_hi0, Sum_hi1;\\\\n\\\\twire Cout_lo, Cout_hi0, Cout_hi1;\\\\n\\\\twire ovf_lo, ovf_hi0, ovf_hi1;\\\\n\\\\t\\\\n\\\\trca_8 rca_lo(Sum[7:0], Cout_lo, ovf_lo, A[7:0], B[7:0], Cin);\\\\n\\\\trca_8 rca_hi0(Sum_hi0, Cout_hi0, ovf_hi0, A[15:8], B[15:8], 1'b0);\\\\n\\\\trca_8 rca_hi1(Sum_hi1, Cout_hi1, ovf_hi1, A[15:8], B[15:8], 1'b1);\\\\n\\\\t\\\\n\\\\tassign Sum[15:8] = Cout_lo ? Sum_hi1 : Sum_hi0;\\\\n\\\\tassign Cout = Cout_lo ? Cout_hi1 : Cout_hi0;\\\\n\\\\tassign overflow = Cout_lo ? ovf_hi1 : ovf_hi0;\\\\nendmodule", "module csa_32(Sum, Cout, overflow, A, B, Cin);\\\\n\\\\tinput [31:0] A, B;\\\\n\\\\tinput Cin;\\\\n\\\\toutput [31:0] Sum;\\\\n\\\\toutput Cout, overflow;\\\\n\\\\t\\\\n\\\\twire [15:0] Sum_hi0, Sum_hi1;\\\\n\\\\twire Cout_lo, Cout_hi0, Cout_hi1;\\\\n\\\\twire ovf_lo, ovf_hi0, ovf_hi1;\\\\n\\\\t\\\\n\\\\tcsa_16 csa_lo(Sum[15:0], Cout_lo, ovf_lo, A[15:0], B[15:0], Cin);\\\\n\\\\tcsa_16 csa_hi0(Sum_hi0, Cout_hi0, ovf_hi0, A[31:16], B[31:16], 1'b0);\\\\n\\\\tcsa_16 csa_hi1(Sum_hi1, Cout_hi1, ovf_hi1, A[31:16], B[31:16], 1'b1);\\\\n\\\\t\\\\n\\\\tassign Sum[31:16] = Cout_lo ? Sum_hi1 : Sum_hi0;\\\\n\\\\tassign Cout = Cout_lo ? Cout_hi1 : Cout_hi0;\\\\n\\\\tassign overflow = Cout_lo ? ovf_hi1 : ovf_hi0;\\\\nendmodule", 'module general_adder_32(Sum, Cout, overflow, A, B, ctrl_ALUopcode);\\\\n\\\\tinput [31:0] A, B;\\\\n\\\\tinput [4:0] ctrl_ALUopcode;\\\\n\\\\toutput [31:0] Sum;\\\\n\\\\toutput Cout, overflow;\\\\n\\\\t\\\\n\\\\twire [31:0] notB, B_input;\\\\n\\\\t\\\\n\\\\tnot_32 not_32_0(notB, B);\\\\n\\\\tassign B_input = ctrl_ALUopcode[0] ? notB : B; // add/sub\\\\n\\\\t\\\\n\\\\tcsa_32 csa(Sum, Cout, overflow, A, B_input, ctrl_ALUopcode[0]);\\\\nendmodule']
["module ALU (input [3:0] Opcode, input [15:0] in1, input [15:0] in2, output [15:0] out, output [2:0] flags); // flags are [2] Z, [1] V, [0] N\\\\n\\\\twire [31:0] routlong;\\\\n\\\\twire [15:0] addout, shout, redout, padout;\\\\n\\\\twire add, pad, shift, red, excor;\\\\n\\\\t\\\\n\\\\twire [15:0] addsat;\\\\n\\\\t\\\\n\\\\twire sign1, sign2;\\\\n\\\\t\\\\n\\\\twire [15:0] in2edit;\\\\n\\\\t\\\\n\\\\t// Unused\\\\n\\\\twire psaerror, claovf;\\\\n\\\\n\\\\twire sub;\\\\n\\\\tassign sub = Opcode == 4'b0001 ? 1'b1 : 1'b0;\\\\n\\\\t\\\\n\\\\tassign in2edit = sub == 1'b1 ? ~in2 : in2;\\\\n\\\\t\\\\n\\\\tassign sign1 = in1[15];\\\\n\\\\tassign sign2 = in2[15] ^ sub;\\\\n\\\\t\\\\n\\\\tcla_16bit a (.Sum(addout), .Ovfl(claovf), .A(in1), .B(in2edit), .Cin(sub));\\\\n\\\\tShifter s (.Shift_Out(shout), .Shift_In(in1), .Shift_Val(in2[3:0]), .Mode(Opcode[1:0]));\\\\n\\\\treduction r (.a(in1), .b(in2), .c(routlong));\\\\n\\\\tPSA_16bit p (.Sum(padout), .Error(psaerror), .A(in1), .B(in2));\\\\n\\\\t\\\\n\\\\tassign addsat = ((sign1 == 1'b0 && sign2 == 1'b0) && (addout[15] == 1'b1)) \\\\n\\\\t? 16'b0111111111111111 : ((sign1 == 1'b1 && sign2 == 1'b1) && (addout[15] == 1'b0))\\\\n\\\\t? 16'b1000000000000000 : addout;\\\\n\\\\t\\\\n\\\\t\\\\n\\\\tassign add = Opcode[3:1] == 3'b000 || Opcode[3:2] == 2'b10;\\\\n\\\\tassign pad = Opcode [3:0] == 4'b0111;\\\\n\\\\tassign shift = Opcode[3:2] == 2'b01 && Opcode[2:0] != 3'b111;\\\\n\\\\tassign red = Opcode[3:0] == 4'b0011;\\\\n\\\\t\\\\n\\\\tassign out = add ? addsat : \\\\n\\\\t\\\\t(pad) ? padout : \\\\n\\\\t\\\\t(shift) ? shout : \\\\n\\\\t\\\\t(red) ? routlong[15:0] : (in1 ^ in2);\\\\n\\\\t\\\\t\\\\n\\\\tassign flags[2] = (out == 16'h0000) ? 1'b1 : 1'b0;\\\\n\\\\tassign flags[1] = claovf;\\\\n\\\\tassign flags[0] = out[15];\\\\nendmodule"]
["module demux_1x4(\\\\n\\\\tdin,\\\\n\\\\tsel,\\\\n\\\\t// output o0, o1, o2,o3\\\\n dout\\\\n\\\\t);\\\\n input din;\\\\n input [1:0] sel;\\\\n output dout;\\\\n // output o0;\\\\n // output o1;\\\\n // output o2;\\\\n // output o3;\\\\n\\\\n reg din;\\\\n reg sel;\\\\n wire dout;\\\\n\\\\t\\\\n // assign o0 = (sel[1] == 0) ? ((sel[0] == 0) ? in : 0) : ((sel[0] == 0) ? 0 : 0); \\\\n // assign o1 = (sel[1] == 0) ? ((sel[0] == 0) ? 0 : in) : ((sel[0] == 0) ? 0 : 0); \\\\n // assign o2 = (sel[1] == 0) ? ((sel[0] == 0) ? 0 : 0) : ((sel[0] == 0) ? in : 0); \\\\n // assign o3 = (sel[1] == 0) ? ((sel[0] == 0) ? 0 : 0) : ((sel[0] == 0) ? 0 : in); \\\\n // assign o0 = sel === 2'b00 ? in : 2bx;\\\\n // assign o1 = sel === 2'b01 ? in : 2bx;\\\\n // assign o2 = sel === 2'b10 ? in : 2bx;\\\\n // assign o3 = sel === 2'b11 ? in : 2bx;\\\\n // assign dout = (sel == 2'b00) ? din:\\\\n // (sel == 2'b01) ? din:\\\\n // (sel == 2'b10) ? din:\\\\n // (sel == 2'b11) ? din: x;\\\\n always @(*) begin\\\\n case (sel)\\\\n 2'b00: dout = din;\\\\n 2'b01: dout = din;\\\\n 2'b10: dout = din;\\\\n 2'b11: dout = din;\\\\n default: dout = x;\\\\n endcase\\\\n end\\\\n\\\\t\\\\nendmodule"]
["module top_elevator( rst_n, clk_df, ftsd, ftsd_ctl, led, row_n, col_n, \\\\n\\\\tau_appsel, au_sysclk, au_bck, au_ws, au_data, \\\\n\\\\tlcd_rst, lcd_cs, lcd_rw, lcd_di, lcd_d, lcd_e,\\\\n\\\\tdip,pb);\\\\n\\\\tinput clk_df; // clock from the crystal\\\\n\\\\tinput rst_n; // active low reset\\\\n\\\\toutput [3:0]ftsd_ctl;\\\\n\\\\toutput [14:0]ftsd;\\\\n\\\\toutput reg [7:0]led; \\\\n\\\\toutput [3:0] row_n;\\\\n\\\\tinput [3:0] col_n;\\\\n\\\\toutput au_appsel; // playing mode selection\\\\n\\\\toutput au_sysclk; // control clock for DAC (from crystal)\\\\n\\\\toutput au_bck; // bit clock of au data (5MHz)\\\\n\\\\toutput au_ws; // left/right parallel to serial control\\\\n\\\\toutput au_data; \\\\n\\\\toutput lcd_rst; // LCD reset\\\\n\\\\toutput [1:0] lcd_cs; // LCD frame selection\\\\n\\\\toutput lcd_rw; // LCD read/write control\\\\n\\\\toutput lcd_di; // LCD data/instruction\\\\n\\\\toutput [7:0] lcd_d; // LCD data\\\\n\\\\toutput lcd_e; // LCD enable\\\\n\\\\tinput [1:0]dip;\\\\n\\\\tinput [7:0]pb;\\\\n\\\\t\\\\n\\\\treg [7:0]led_next;\\\\n\\\\treg [7:0]arr;\\\\n\\\\treg [2:0]at;\\\\n\\\\treg [1:0]state;\\\\n\\\\treg [1:0]state_next;\\\\n\\\\treg [3:0]i;\\\\n\\\\twire [19:0]nd;\\\\n\\\\t\\\\n\\\\twire [15:0] au_in_left, au_in_right;\\\\n\\\\twire [3:0]clk_move;\\\\n\\\\twire [3:0]ftsd_in;\\\\n\\\\twire [1:0]clk_fs;\\\\n\\\\t\\\\n\\\\treg move;\\\\t\\\\n\\\\treg [3:0]fre;\\\\t\\\\t//frequency indicator\\\\n\\\\twire [15:0]key;\\\\n\\\\t\\\\n\\\\tbuzzer_control Ung(\\\\n\\\\t\\\\t.clk(clk_df), // clock from crystal\\\\n\\\\t\\\\t.rst_n(rst_n&&~(fre==4'd15)), // active low reset\\\\n\\\\t\\\\t.note_div(nd), // div for music note\\\\n\\\\t\\\\t.au_left(au_in_left), // left audio\\\\n\\\\t\\\\t.au_right(au_in_right) // right audio\\\\n\\\\t);\\\\n\\\\t// Speaker controllor\\\\n\\\\tspeaker_control Usc(\\\\n\\\\t\\\\t.clk(clk_df), // clock from the crystal\\\\n\\\\t\\\\t.rst_n(rst_n&&~(fre==4'd15)), // active low reset\\\\n\\\\t\\\\t.au_in_left(au_in_left), // left channel au data\\\\n\\\\t\\\\t.au_in_right(au_in_right), // right channel au data\\\\n\\\\t\\\\t.au_appsel(au_appsel), // mode selection\\\\n\\\\t\\\\t.au_sysclk(au_sysclk), // control clock for DAC (from crystal)\\\\n\\\\t\\\\t.au_bck(au_bck), // bit clock of au data (5MHz)\\\\n\\\\t\\\\t.au_ws(au_ws), // left/right parallel to serial control\\\\n\\\\t\\\\t.au_data(au_data) // serial output au data\\\\n\\\\t);\\\\n\\\\tnote16 n16(\\\\n\\\\t\\\\t.clk(clk_fs[0]),\\\\n\\\\t\\\\t.nd(nd),\\\\n\\\\t\\\\t.ki(fre),\\\\n\\\\t\\\\t.pre(rst_n&&~(fre==4'd15)),\\\\n\\\\t\\\\t.d1(),\\\\n\\\\t\\\\t.d2()\\\\n\\\\t);\\\\n\\\\twire [3:0]ff; //frequency flag\\\\n\\\\treg [4:0]ft;\\\\t//frequency time\\\\n\\\\twire [63:0]tune0=64'h0001222022002222;\\\\n\\\\twire [63:0]tune1=64'h1112332133333333;\\\\n\\\\twire [63:0]tune2=64'h2223555255225555;\\\\n\\\\twire [63:0]tune3=64'h3335775377777777;\\\\n\\\\twire [63:0]tune4=64'h5550123577777777;\\\\n\\\\twire [63:0]tune5=64'h7771245799999999;\\\\n\\\\twire [63:0]tune6=64'h99924679aaaaaaaa;\\\\n\\\\twire [63:0]tune7=64'h9877339955aaaaaa;\\\\n\\\\twire [6:0]addr;\\\\n wire [7:0]data;\\\\n wire clk_50k;\\\\n \\\\n reg clk_tm;\\\\t\\\\t//clk true move\\\\n\\\\twire ffrst;\\\\n\\\\tassign ffrst = ft[4]||~rst_n;\\\\n\\\\tassign ff = (move||ffrst)? 4'd8 : {1'b0,at};\\\\n\\\\t\\\\n\\\\talways @*\\\\n\\\\t\\\\tcase(ff)\\\\n\\\\t\\\\t\\\\t4'd0 :fre<=tune0[(60-ft*4)+:4];\\\\n\\\\t\\\\t\\\\t4'd1 :fre<=tune1[(60-ft*4)+:4];\\\\n\\\\t\\\\t\\\\t4'd2 :fre<=tune2[(60-ft*4)+:4];\\\\n\\\\t\\\\t\\\\t4'd3 :fre<=tune3[(60-ft*4)+:4];\\\\n\\\\t\\\\t\\\\t4'd4 :fre<=tune4[(60-ft*4)+:4];\\\\n\\\\t\\\\t\\\\t4'd5 :fre<=tune5[(60-ft*4)+:4];\\\\n\\\\t\\\\t\\\\t4'd6 :fre<=tune6[(60-ft*4)+:4];\\\\n\\\\t\\\\t\\\\t4'd7 :fre<=tune7[(60-ft*4)+:4];\\\\n\\\\t\\\\t\\\\tdefault:fre<=4'd15;\\\\n\\\\t\\\\tendcase\\\\n\\\\t\\\\n\\\\n\\\\talways @(negedge clk_move[2] or posedge move)\\\\n\\\\t\\\\tif(move)\\\\n\\\\t\\\\t\\\\tft <= 5'b0;\\\\n\\\\t\\\\telse\\\\n\\\\t\\\\t\\\\tft <= ft+1'b1;\\\\n\\\\t\\\\n\\\\tscan_ctl sc(\\\\n\\\\t\\\\t.ftsd_ctl(ftsd_ctl),\\\\n\\\\t\\\\t.ftsd_in(ftsd_in),\\\\n\\\\t\\\\t.in0(4'hf),\\\\n\\\\t\\\\t.in1(4'hf),\\\\n\\\\t\\\\t.in2({2'b11,state}),\\\\n\\\\t\\\\t.in3({1'b0,at}),\\\\n\\\\t\\\\t.ftsd_ctl_en(clk_fs)\\\\n\\\\t);\\\\n\\\\t\\\\n\\\\tftsd zer94ftsdr(\\\\n\\\\t\\\\t.display(ftsd),\\\\n\\\\t\\\\t.bcd(ftsd_in)\\\\n\\\\t);\\\\n\\\\t\\\\n\\\\tkeypad_scan K1 (\\\\n .rst_n(rst_n),\\\\n .clk(clk_fs[0]),\\\\n .col(col_n),\\\\n .row(row_n),\\\\n .change(), // push and release\\\\n .key(key) // mask {F,E,D,C,B,3,6,9,A,2,5,8,0,1,4,7}\\\\n );\\\\n \\\\n \\\\n rom_ctrl U_romctrl(\\\\n .clk(clk_50k), // rom controller clock\\\\n .rst_n(rst_n), // active low reset\\\\n .en(lcd_e), // LCD enable\\\\n .data_request(data_request), // request signal from LCD\\\\n .address(addr), // requested address\\\\n .data_ack(data_ack), // data ready acknowledge\\\\n .data(data) // data to be transferred (byte)\\\\n);\\\\n wire halt;\\\\n lcd_ctrl U_LCDctrl(\\\\n .clk(clk_50k), // LCD controller clock\\\\n .rst_n(rst_n), // active low reset\\\\n .data_ack(data_ack), // data re-arrangement buffer ready indicator\\\\n .data(data), // byte data transfer from buffer\\\\n .lcd_di(lcd_di), // LCD data/instruction \\\\n .lcd_rw(lcd_rw), // LCD Read/Write\\\\n .lcd_en(lcd_e), // LCD enable\\\\n .lcd_rst(lcd_rst), // LCD reset\\\\n .lcd_cs(lcd_cs), // LCD frame select\\\\n .lcd_data(lcd_d), // LCD data\\\\n .addr(addr), // Address for each picture\\\\n .data_request(data_request), // request for the memory data\\\\n .cnt_e(~move),\\\\n .halt(halt)\\\\n);\\\\n\\\\t\\\\n clock_divider #(\\\\n .half_cycle(400), // half cycle = 400 (divided by 800)\\\\n .counter_width(14) // counter width = 10 bits\\\\n ) www (\\\\n .rst_n(rst_n),\\\\n .clk(clk_df),\\\\n .clk_div(clk_50k)\\\\n );\\\\n freq_div fd(\\\\n\\\\t\\\\t.clk_out(clk_move),\\\\n\\\\t\\\\t.clk_ctl(clk_fs),\\\\n\\\\t\\\\t.clk(clk_df),\\\\n\\\\t\\\\t.rst_n(rst_n)\\\\n\\\\t);\\\\n \\\\n\\\\t\\\\n\\\\talways @(posedge clk_fs[0] or negedge rst_n)\\\\n\\\\t\\\\tif(~rst_n)begin\\\\n\\\\t\\\\t\\\\tled <= 8'b0;\\\\n\\\\t\\\\t\\\\tstate<=2'd1;\\\\n\\\\t\\\\tend\\\\n\\\\t\\\\telse begin\\\\n\\\\t\\\\t\\\\tled <= led_next;\\\\n\\\\t\\\\t\\\\tstate<=state_next;\\\\n\\\\t\\\\tend\\\\n\\\\talways @*begin\\\\n\\\\t\\\\tled_next[0] = ~arr[0]&&( led[0] ||key[2] || ~pb[0] );\\\\t//key1\\\\n\\\\t\\\\tled_next[1] = ~arr[1]&&( led[1] ||key[6] || ~pb[1] );\\\\t//key2\\\\n\\\\t\\\\tled_next[2] = ~arr[2]&&( led[2] ||key[10]|| ~pb[2] );\\\\t//key3\\\\n\\\\t\\\\tled_next[3] = ~arr[3]&&( led[3] ||key[1] || ~pb[3] );\\\\t//key4\\\\n\\\\t\\\\tled_next[4] = ~arr[4]&&( led[4] ||key[5] || ~pb[4] );\\\\t//key5\\\\n\\\\t\\\\tled_next[5] = ~arr[5]&&( led[5] ||key[9] || ~pb[5] );\\\\t//key6\\\\n\\\\t\\\\tled_next[6] = ~arr[6]&&( led[6] ||key[0] || ~pb[6] );\\\\t//key7\\\\n\\\\t\\\\tled_next[7] = ~arr[7]&&( led[7] ||key[4] || ~pb[7] );\\\\t//key8\\\\n\\\\tend\\\\n\\\\t\\\\n\\\\talways @(at)begin\\\\n\\\\t\\\\tarr <= 8'b0;\\\\n\\\\t\\\\tcase(at)\\\\n\\\\t\\\\t\\\\t3'd0:arr[0] <= 1'b1;\\\\n\\\\t\\\\t\\\\t3'd1:arr[1] <= 1'b1;\\\\n\\\\t\\\\t\\\\t3'd2:arr[2] <= 1'b1;\\\\n\\\\t\\\\t\\\\t3'd3:arr[3] <= 1'b1;\\\\n\\\\t\\\\t\\\\t3'd4:arr[4] <= 1'b1;\\\\n\\\\t\\\\t\\\\t3'd5:arr[5] <= 1'b1;\\\\n\\\\t\\\\t\\\\t3'd6:arr[6] <= 1'b1;\\\\n\\\\t\\\\t\\\\t3'd7:arr[7] <= 1'b1;\\\\n\\\\t\\\\tendcase\\\\n\\\\tend\\\\n\\\\t\\\\n\\\\tinitial\\\\n\\\\t\\\\tmove<=1'b1;\\\\n\\\\talways @ *begin\\\\n\\\\t\\\\tif((arr[0]&&( led[0] ||key[2] || ~pb[0] ))||\\\\n\\\\t\\\\t\\\\t(arr[1]&&( led[1] ||key[6] || ~pb[1] ))||\\\\n\\\\t\\\\t\\\\t(arr[2]&&( led[2] ||key[10]|| ~pb[2] ))||\\\\n\\\\t\\\\t\\\\t(arr[3]&&( led[3] ||key[1] || ~pb[3] ))||\\\\n\\\\t\\\\t\\\\t(arr[4]&&( led[4] ||key[5] || ~pb[4] ))||\\\\n\\\\t\\\\t\\\\t(arr[5]&&( led[5] ||key[9] || ~pb[5] ))||\\\\n\\\\t\\\\t\\\\t(arr[6]&&( led[6] ||key[0] || ~pb[6] ))||\\\\n\\\\t\\\\t\\\\t(arr[7]&&( led[7] ||key[4] || ~pb[7] )))begin\\\\n\\\\t\\\\t\\\\tmove<=1'b0;\\\\n\\\\t\\\\tend\\\\n\\\\t\\\\telse begin\\\\n\\\\t\\\\t\\\\tif(halt)\\\\n\\\\t\\\\t\\\\t\\\\tmove<=1'b1;\\\\n\\\\t\\\\t\\\\telse\\\\n\\\\t\\\\t\\\\t\\\\tmove<=1'b0;\\\\n\\\\t\\\\tend\\\\n\\\\tend\\\\n\\\\t\\\\n\\\\talways @*\\\\n\\\\t\\\\tcase(dip)\\\\n\\\\t\\\\t\\\\t2'd0:clk_tm=clk_move[3];\\\\n\\\\t\\\\t\\\\t2'd1:clk_tm=clk_move[0];\\\\n\\\\t\\\\t\\\\t2'd2:clk_tm=clk_move[2];\\\\n\\\\t\\\\t\\\\t2'd3:clk_tm=clk_move[1];\\\\n\\\\t\\\\tendcase\\\\n\\\\talways @(posedge clk_tm or negedge rst_n)\\\\n\\\\t\\\\tif(~rst_n)\\\\n\\\\t\\\\t\\\\tat <= 3'b0;\\\\n\\\\t\\\\telse if(move)\\\\n\\\\t\\\\t\\\\tcase(state)\\\\n\\\\t\\\\t\\\\t\\\\t2'b0:/*down*/\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tat <= at-1'b1;\\\\n\\\\t\\\\t\\\\t\\\\t2'b1:/*idle*/;\\\\n\\\\t\\\\t\\\\t\\\\t2'd2:/*up*/\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tat <= at+1'b1;\\\\n\\\\t\\\\t\\\\t\\\\tdefault:at<=at;\\\\n\\\\t\\\\t\\\\tendcase\\\\n\\\\t\\\\n\\\\talways @* begin\\\\t\\\\t\\\\t\\\\t\\\\t\\\\n\\\\t\\\\tstate_next = 2'd1;\\\\t\\\\t//idle\\\\n\\\\t\\\\tcase(state)\\\\n\\\\t\\\\t\\\\t2'd0:begin\\\\n\\\\t\\\\t\\\\tfor(i=4'd7;i<=4'd7;i=i-1'b1)begin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tif(led[i])begin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tif(at<(i))\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tstate_next = 2'd2; //up\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\telse if(at>(i))\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tstate_next = 2'd0; //down\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t//lack of open door signal\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t2'd1:begin\\\\n\\\\t\\\\t\\\\t\\\\tfor(i=4'd0;i<=4'd7;i=i+1'b1)begin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tif(led[i])begin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tif(at<(i))\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tstate_next = 2'd2; //up\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\telse if(at>(i))\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tstate_next = 2'd0; //down\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t//lack of open door signal\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t2'd2:begin\\\\n\\\\t\\\\t\\\\tfor(i=4'd0;i<=4'd7;i=i+1'b1)begin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tif(led[i])begin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tif(at<(i))\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tstate_next = 2'd2; //up\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\telse if(at>(i))\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tstate_next = 2'd0; //down\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t//lack of open door signal\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\tdefault : state_next = state;\\\\n\\\\t\\\\tendcase\\\\n\\\\tend\\\\n\\\\t\\\\nendmodule"]
["module proc(Clock, Resetn, Run, DIN, Done, ADDR, DOUT, W);\\\\n\\\\tinput Clock, Resetn, Run;\\\\n\\\\tinput [8:0] DIN;\\\\n\\\\toutput Done;\\\\n\\\\toutput [8:0] ADDR, DOUT;\\\\n\\\\toutput W;\\\\n\\\\t\\\\n\\\\tparameter T0 = 3'b000, T1 = 3'b001, T2 = 3'b010, T3 = 3'b011, T4 = 3'b100, T5 = 3'b101;\\\\n\\\\tparameter mv = 3'b000, mvi = 3'b001, add = 3'b010, sub = 3'b011, ld = 3'b100, st = 3'b101, mvnz = 3'b110;\\\\n\\\\t\\\\n\\\\treg [0:7] Rin, Rout;\\\\n\\\\treg Ain, IRin, AddSub, Gin, Gout, DINout, incr_pc, ADDR_in, DOUT_in, W_D;\\\\n\\\\treg [3:0] Tstep_Q, Tstep_D;\\\\n\\\\treg Done;\\\\n\\\\treg [8:0] BusWires;\\\\n\\\\t\\\\n\\\\twire [1:9] IR;\\\\n\\\\twire [0:7] Xreg, Yreg;\\\\n\\\\twire [2:0] I;\\\\n\\\\twire [2:0] X, Y;\\\\n\\\\twire W;\\\\n\\\\t\\\\n\\\\twire [8:0] R7, R6, R5, R4, R3, R2, R1, R0, A, G, AddSub_result, ADDR, DOUT;\\\\n\\\\twire [9:0] Sel;\\\\n\\\\t\\\\n\\\\tassign I = IR[1:3];\\\\n\\\\tassign X = IR[4:6];\\\\n\\\\tassign Y = IR[7:9];\\\\n\\\\tdec3to8 decX (X, 1'b1, Xreg);\\\\n\\\\tdec3to8 decY (Y, 1'b1, Yreg);\\\\n\\\\t\\\\n\\\\t//Control FSM state table\\\\n\\\\talways @ (Tstep_Q, Run, Done)\\\\n\\\\tbegin\\\\n\\\\t\\\\tcase (Tstep_Q)\\\\n\\\\t\\\\t\\\\tT0: if(!Run) Tstep_D = T0;\\\\n\\\\t\\\\t\\\\t\\\\t else Tstep_D = T1;\\\\n\\\\t\\\\t\\\\tT1: Tstep_D = T2;\\\\n\\\\t\\\\t\\\\tT2: Tstep_D = T3;\\\\n\\\\t\\\\t\\\\tT3: if (Done) \\\\tTstep_D = T0;\\\\n\\\\t\\\\t\\\\t\\\\t else\\\\t\\\\tTstep_D = T4;\\\\n\\\\t\\\\t\\\\tT4: Tstep_D = T5;\\\\n\\\\t\\\\t\\\\tT5: Tstep_D = T0;\\\\n\\\\t\\\\t\\\\tdefault:\\\\tTstep_D = 4'bxxxx;\\\\n\\\\t\\\\tendcase\\\\n\\\\tend \\\\n\\\\t\\\\n\\\\t//Control FSM outputs\\\\n\\\\talways @ (Tstep_Q or I or Xreg or Yreg or G)\\\\n\\\\tbegin\\\\n\\\\t\\\\tIRin = 1'b0;\\\\n\\\\t\\\\tRin = 1'b0;\\\\n\\\\t\\\\tRout = 1'b0;\\\\n\\\\t\\\\tDINout = 1'b0;\\\\n\\\\t\\\\tAddSub = 1'b0;\\\\n\\\\t\\\\tAin = 1'b0;\\\\n\\\\t\\\\tGin = 1'b0;\\\\n\\\\t\\\\tGout = 1'b0;\\\\n\\\\t\\\\tDone = 1'b0;\\\\n\\\\t\\\\tincr_pc = 1'b0;\\\\n\\\\t\\\\tADDR_in = 1'b0;\\\\n\\\\t\\\\tDOUT_in = 1'b0;\\\\n\\\\t\\\\tW_D = 1'b0;\\\\n\\\\t\\\\t\\\\n\\\\t\\\\tcase (Tstep_Q)\\\\n\\\\t\\\\t\\\\tT0: \\\\n\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\tif(!Run) incr_pc = 1'b0;\\\\n\\\\t\\\\t\\\\t\\\\telse incr_pc = 1'b1;\\\\n\\\\t\\\\t\\\\t\\\\tRout[7] = 1'b1;\\\\n\\\\t\\\\t\\\\t\\\\tADDR_in = 1'b1;\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\tT1: ; //wait cycle for synchronous memory\\\\n\\\\t\\\\t\\\\tT2: //store DIn in IR in time step 2\\\\n\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\tIRin = 1'b1;\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\tT3: //define signals in time step 3\\\\n\\\\t\\\\t\\\\t\\\\tcase (I)\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tmv: \\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tRin = Xreg;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tRout = Yreg;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tDone = 1'b1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tend \\\\n\\\\t\\\\t\\\\t\\\\t\\\\tmvi:\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tincr_pc = 1'b1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tRout[7] = 1'b1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tADDR_in = 1'b1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tadd:\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tAin = 1'b1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tRout = Xreg;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tend \\\\n\\\\t\\\\t\\\\t\\\\t\\\\tsub:\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tRout = Xreg;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tAin = 1'b1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tld, st:\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tRout = Yreg;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tADDR_in = 1'b1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tmvnz:\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tif(G != 0)\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tRout = Yreg;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tRin = Xreg;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tDone = 1'b1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tdefault: ;\\\\n\\\\t\\\\t\\\\t\\\\tendcase\\\\n\\\\t\\\\t\\\\tT4: //define signals in time step 4\\\\n\\\\t\\\\t\\\\t\\\\tcase (I)\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tmvi: ;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tadd:\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tRout = Yreg;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tGin = 1'b1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tend \\\\n\\\\t\\\\t\\\\t\\\\t\\\\tsub:\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tRout = Yreg;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tGin = 1'b1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tAddSub = 1'b1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tend \\\\n\\\\t\\\\t\\\\t\\\\t\\\\tld:\\\\t;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tst:\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tRout = Xreg;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tDOUT_in = 1'b1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tW_D = 1'b1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tdefault: ;\\\\n\\\\t\\\\t\\\\t\\\\tendcase\\\\n\\\\t\\\\t\\\\tT5: //define signals in time step 5\\\\n\\\\t\\\\t\\\\t\\\\tcase (I)\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tmvi:\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tDINout = 1'b1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tRin = Xreg;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tDone = 1'b1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tadd:\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tGout = 1'b1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tRin = Xreg;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tDone = 1'b1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tsub:\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tGout = 1'b1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tRin = Xreg;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tDone = 1'b1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tld:\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tRin = Xreg;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tDINout = 1'b1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tDone = 1'b1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tst:\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tDone = 1'b1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tdefault: ;\\\\n\\\\t\\\\t\\\\t\\\\tendcase \\\\n\\\\t\\\\t\\\\tdefault: ;\\\\n\\\\t\\\\tendcase \\\\n\\\\tend\\\\n\\\\n\\\\t//Control Fsm flip-flops\\\\n\\\\talways @ (posedge Clock, posedge Resetn)\\\\n\\\\t\\\\tif (Resetn)\\\\n\\\\t\\\\t\\\\tTstep_Q <= T0;\\\\n\\\\t\\\\telse\\\\n\\\\t\\\\t\\\\tTstep_Q <= Tstep_D;\\\\n\\\\t\\\\n\\\\tregn reg_0 (BusWires, Rin[0], Clock, R0);\\\\n\\\\tregn reg_1 (BusWires, Rin[1], Clock, R1);\\\\n\\\\tregn reg_2 (BusWires, Rin[2], Clock, R2);\\\\n\\\\tregn reg_3 (BusWires, Rin[3], Clock, R3);\\\\n\\\\tregn reg_4 (BusWires, Rin[4], Clock, R4);\\\\n\\\\tregn reg_5 (BusWires, Rin[5], Clock, R5);\\\\n\\\\tregn reg_6 (BusWires, Rin[6], Clock, R6);\\\\n\\\\t//regn reg_7 (BusWires, Rin[7], Clock, R7);\\\\n\\\\tprogram_counter pc7(\\\\n\\\\t\\\\t.clock(Clock),\\\\n\\\\t\\\\t.reset(Resetn),\\\\n\\\\t\\\\t.E(incr_pc),\\\\n\\\\t\\\\t.L(Rin[7]),\\\\n\\\\t\\\\t.PC(BusWires),\\\\n\\\\t\\\\t.Q(R7));\\\\n\\\\t\\\\n\\\\t\\\\n\\\\tregn reg_IR (DIN, IRin, Clock, IR);\\\\n\\\\tregn reg_A (BusWires, Ain, Clock, A);\\\\n\\\\tregn reg_G (AddSub_result, Gin, Clock, G);\\\\n\\\\t\\\\n\\\\tregn reg_ADDR (BusWires, ADDR_in, Clock, ADDR);\\\\n\\\\tregn reg_DOUT (BusWires, DOUT_in, Clock, DOUT);\\\\n\\\\t\\\\n\\\\tregw reg_W (Clock, W_D, W);\\\\n\\\\t\\\\n\\\\tadder_subtractor addsub (AddSub, A, BusWires, AddSub_result);\\\\n\\\\t\\\\n\\\\tassign Sel = {Rout, Gout, DINout};\\\\n\\\\t\\\\n\\\\talways @ (*)\\\\n\\\\t\\\\tcase (Sel)\\\\n\\\\t\\\\t\\\\t10'b10_0000_0000 : BusWires = R0;\\\\n\\\\t\\\\t\\\\t10'b01_0000_0000 : BusWires = R1;\\\\n\\\\t\\\\t\\\\t10'b00_1000_0000 : BusWires = R2;\\\\n\\\\t\\\\t\\\\t10'b00_0100_0000 : BusWires = R3;\\\\n\\\\t\\\\t\\\\t10'b00_0010_0000 : BusWires = R4;\\\\n\\\\t\\\\t\\\\t10'b00_0001_0000 : BusWires = R5;\\\\n\\\\t\\\\t\\\\t10'b00_0000_1000 : BusWires = R6;\\\\n\\\\t\\\\t\\\\t10'b00_0000_0100 : BusWires = R7;\\\\n\\\\t\\\\t\\\\t10'b00_0000_0010 : BusWires = G;\\\\n\\\\t\\\\t\\\\t10'b00_0000_0001 : BusWires = DIN;\\\\n\\\\t\\\\t\\\\tdefault : BusWires = 9'bxxxxxxxxx;\\\\n\\\\t\\\\tendcase\\\\n\\\\t\\\\t\\\\nendmodule"]
['module router_top(input clk, resetn, packet_valid, read_enb_0, read_enb_1, read_enb_2,\\\\n\\\\t\\\\t\\\\t\\\\t input [7:0]datain, \\\\n\\\\t\\\\t\\\\t\\\\t output vldout_0, vldout_1, vldout_2, err, busy,\\\\n\\\\t\\\\t\\\\t\\\\t output [7:0]data_out_0, data_out_1, data_out_2);\\\\n\\\\nwire [2:0]w_enb;\\\\nwire [2:0]soft_reset;\\\\nwire [2:0]read_enb; \\\\nwire [2:0]empty;\\\\nwire [2:0]full;\\\\nwire lfd_state_w;\\\\nwire [7:0]data_out_temp[2:0];\\\\nwire [7:0]dout;\\\\n\\\\n\\\\tgenvar a;\\\\n\\\\ngenerate \\\\nfor(a=0;a<3;a=a+1)\\\\n\\\\nbegin:fifo\\\\n\\\\trouter_fifo f(.clk(clk), .resetn(resetn), .soft_reset(soft_reset[a]),\\\\n\\\\t.lfd_state(lfd_state_w), .write_enb(w_enb[a]), .datain(dout), .read_enb(read_enb[a]), \\\\n\\\\t.full(full[a]), .empty(empty[a]), .dataout(data_out_temp[a]));\\\\nend\\\\nendgenerate\\\\t\\\\t\\\\t \\\\n\\\\nrouter_reg r1(.clk(clk), .resetn(resetn), .packet_valid(packet_valid), .datain(datain), \\\\n\\\\t\\\\t\\\\t .dout(dout), .fifo_full(fifo_full), .detect_add(detect_add), \\\\n\\\\t\\\\t\\\\t .ld_state(ld_state), .laf_state(laf_state), .full_state(full_state), \\\\n\\\\t\\\\t\\\\t .lfd_state(lfd_state_w), .rst_int_reg(rst_int_reg), .err(err), .parity_done(parity_done), .low_packet_valid(low_packet_valid));\\\\n\\\\nrouter_fsm fsm(.clk(clk), .resetn(resetn), .packet_valid(packet_valid), \\\\n\\\\t\\\\t\\\\t .datain(datain[1:0]), .soft_reset_0(soft_reset[0]), .soft_reset_1(soft_reset[1]), .soft_reset_2(soft_reset[2]), \\\\n\\\\t\\\\t\\\\t .fifo_full(fifo_full), .fifo_empty_0(empty[0]), .fifo_empty_1(empty[1]), .fifo_empty_2(empty[2]),\\\\n\\\\t\\\\t\\\\t .parity_done(parity_done), .low_packet_valid(low_packet_valid), .busy(busy), .rst_int_reg(rst_int_reg), \\\\n\\\\t\\\\t\\\\t .full_state(full_state), .lfd_state(lfd_state_w), .laf_state(laf_state), .ld_state(ld_state), \\\\n\\\\t\\\\t\\\\t .detect_add(detect_add), .write_enb_reg(write_enb_reg));\\\\n\\\\nrouter_sync s(.clk(clk), .resetn(resetn), .datain(datain[1:0]), .detect_add(detect_add), \\\\n .full_0(full[0]), .full_1(full[1]), .full_2(full[2]), .read_enb_0(read_enb[0]), \\\\n\\\\t\\\\t\\\\t .read_enb_1(read_enb[1]), .read_enb_2(read_enb[2]), .write_enb_reg(write_enb_reg), \\\\n\\\\t\\\\t\\\\t .empty_0(empty[0]), .empty_1(empty[1]), .empty_2(empty[2]), .vld_out_0(vldout_0), .vld_out_1(vldout_1), .vld_out_2(vldout_2), \\\\n\\\\t\\\\t\\\\t .soft_reset_0(soft_reset[0]), .soft_reset_1(soft_reset[1]), .soft_reset_2(soft_reset[2]), .write_enb(w_enb), .fifo_full(fifo_full));\\\\n\\\\t\\\\t\\\\t \\\\nassign read_enb[0]= read_enb_0;\\\\nassign read_enb[1]= read_enb_1;\\\\nassign read_enb[2]= read_enb_2;\\\\nassign data_out_0=data_out_temp[0];\\\\nassign data_out_1=data_out_temp[1];\\\\nassign data_out_2=data_out_temp[2];\\\\n\\\\nendmodule']
["module microc(input wire clk, reset, s_ret, s_rre, s_inc, s_inm, we3, wez, input wire [2:0] op, output wire z, output wire [5:0] opcode);\\\\n//Microcontrolador sin memoria de datos de un solo ciclo\\\\n\\\\n//Instanciar e interconectar pc, memprog, regfile, alu, sum, biestable Z y mux's\\\\n\\\\nwire[9:0] sum_out, mux_SumSalto, mux_pc, dir, dir_salto, rr_out;\\\\nwire[3:0] ra1, ra2, wa3;\\\\nwire[7:0] inm, wd3, rd1, rd2, alu_out;\\\\nwire[15:0] instruccion;\\\\nwire zalu;\\\\n\\\\nassign ra1[3:0] = instruccion[11:8];\\\\nassign ra2[3:0] = instruccion[7:4];\\\\nassign wa3[3:0] = instruccion[3:0];\\\\nassign inm[7:0] = instruccion[11:4];\\\\nassign opcode[5:0] = instruccion[15:10];\\\\nassign dir_salto[9:0] = instruccion[9:0];\\\\n\\\\nmux2 #(10) muxPC(mux_SumSalto, rr_out, s_ret, mux_pc);\\\\nregistro #(10) pc(clk, reset, mux_pc, dir);\\\\nsum sum(dir, 10'b1, sum_out);\\\\nmemprog memprog(clk, dir, instruccion);\\\\nregfile banco_registros(clk, we3, ra1, ra2, wa3, wd3, rd1, rd2);\\\\nalu alu(rd1, rd2, op, alu_out, zalu);\\\\nffd ffz(clk, reset, zalu, wez, z);\\\\nmux2 muxAlu(alu_out, inm, s_inm, wd3);\\\\nregistro_en #(10) rr(clk, reset, s_rre, sum_out, rr_out);\\\\nmux2 #(10) muxInc(dir_salto, sum_out, s_inc, mux_SumSalto);\\\\n\\\\n\\\\nendmodule"]
['module\\\\n\\\\nmodule mips_16( input clk,reset, output[15:0] pc_out,instruction, alu_result,reg1,reg2,reg3 ); // Defines a module named \\\\"mips_16\\\\" with input and output ports\\\\n\\\\nwire [15:0] instr; // Declares a 16-bit wire \\\\"instr\\\\"\\\\nwire[1:0] alu_op; // Declares a 2-bit wire \\\\"alu_op\\\\"\\\\nwire [2:0] write_dest; // Declares a 3-bit wire \\\\"write_dest\\\\"\\\\nwire [15:0] write_data; // Declares a 16-bit wire \\\\"write_data\\\\"\\\\nwire [2:0] read_addr_1; // Declares a 3-bit wire \\\\"read_addr_1\\\\"\\\\nwire [15:0] read_data_1; // Declares a 16-bit wire \\\\"read_data_1\\\\"\\\\nwire [2:0] read_addr_2; // Declares a 3-bit wire \\\\"read_addr_2\\\\"\\\\nwire [15:0] read_data_2; // Declares a 16-bit wire \\\\"read_data_2\\\\"\\\\nwire jump,beq,mem_read,mem_write,alu_src,reg_dst,mem_to_reg,reg_write,bne; // Declares several wires for control signals\\\\nwire [15:0] read_data2,imm_ext; // Declares several 16-bit wires\\\\nwire [2:0] ALU_Control; // Declares a 3-bit wire \\\\"ALU_Control\\\\"\\\\nwire [15:0] ALU_out; // Declares a 16-bit wire \\\\"ALU_out\\\\"\\\\nwire zero_flag; // Declares a wire \\\\"zero_flag\\\\"\\\\nreg[15:0] pc_current; // Declares a 16-bit register \\\\"pc_current\\\\"\\\\nwire signed[15:0] pc_next,pc_2; // Declares two 16-bit wires \\\\"pc_next\\\\" and \\\\"pc_2\\\\"\\\\nwire signed[15:0] im_shift_1, PC_j, PC_beq, PC_4beq,PC_bne,PC_4bne; // Declares several 16-bit wires\\\\nwire beq_control,bne_control; // Declares wires for control signals\\\\nwire [14:0] jump_shift_1; // Declares a 15-bit wire \\\\"jump_shift_1\\\\"\\\\nwire [15:0] mem_read_data; // Declares a 16-bit wire \\\\"mem_read_data\\\\"\\\\n\\\\n\\\\n// PC\\\\nalways @(posedge clk or posedge reset) // Executes the following block on the positive edge of the clock or the positive edge of the reset signal\\\\nbegin\\\\n if(reset) // If the reset signal is active\\\\n pc_current <= 16\\'d0; // Assigns 0 to the register \\\\"pc_current\\\\"\\\\n else\\\\n pc_current <= pc_next; // Assigns the value of \\\\"pc_next\\\\" to the register \\\\"pc_current\\\\"\\\\nend\\\\n\\\\n// PC + 2\\\\nassign pc_2 = pc_current + 16\\'d2; // Adds 2 to \\\\"pc_current\\\\" and assigns the result to \\\\"pc_2\\\\"\\\\n // instruction memory \\\\n// instruction memory\\\\ninstr_mem instrucion_memory(.pc(pc_current),.instruction(instr));\\\\n\\\\n// jump shift left 1\\\\nassign jump_shift_1 = {instr[12:0],1\\'b0};\\\\n\\\\n// control unit\\\\ncontrol_unit control(.reset(reset),.opcode(instr[15:13]),.reg_dst(reg_dst),\\\\n .mem_to_reg(mem_to_reg),.alu_op(alu_op),.jump(jump),.beq(beq),.mem_read(mem_read),\\\\n .mem_write(mem_write),.alu_src(alu_src),.reg_write(reg_write),.bne(bne));\\\\n\\\\n// multiplexer regdest\\\\nassign write_dest = (reg_dst==1\\'b1) ? instr[6:4] : instr[9:7];\\\\n\\\\n// register file\\\\nassign read_addr_1 = instr[12:10];\\\\nassign read_addr_2 = instr[9:7];\\\\nregister_file reg_file(.clk(clk),.rst(reset),.reg_write(reg_write),\\\\n.write_dest(write_dest),\\\\n.write_data(write_data),\\\\n.read_addr_1(read_addr_1),\\\\n.read_data_1(read_data_1),\\\\n.read_addr_2(read_addr_2),\\\\n.read_data_2(read_data_2),\\\\n.reg1(reg1),\\\\n.reg2(reg2),\\\\n.reg3(reg3));\\\\n\\\\n// sign extend\\\\nassign imm_ext = {{9{instr[6]}},instr[6:0]}; //9{instr[6]}: This expression creates a 9-bit signal where all the bits are the same as the 6th bit of the instr signal\\\\n\\\\n\\\\n\\\\n// ALU control unit\\\\nALUControl ALU_Control_unit(.ALUOp(alu_op),.Function(instr[3:0]),.ALU_Control(ALU_Control));\\\\n\\\\n// multiplexer alu_src\\\\nassign read_data2 = (alu_src==1\\'b1) ? imm_ext : read_data_2;\\\\n\\\\n// ALU\\\\nalu alu_unit(.a(read_data_1),.b(read_data2),.alu_ctrl(ALU_Control),.result(ALU_out),.zero(zero_flag));\\\\n\\\\n// immediate shift 1\\\\nassign im_shift_1 = {imm_ext[14:0],1\\'b0};\\\\n\\\\n// PC beq&bne add\\\\nassign PC_beq = pc_2 + im_shift_1 ;\\\\nassign PC_bne = pc_2 + im_shift_1 ;\\\\n\\\\n// beq control\\\\nassign beq_control = beq & zero_flag;\\\\nassign bne_control = bne & (~zero_flag);\\\\n\\\\n// PC_beq\\\\nassign PC_4beq = (beq_control==1\\'b1) ? PC_beq : pc_2;\\\\n\\\\n// PC_bne\\\\nassign PC_4bne = (bne_control==1\\'b1) ? PC_bne : PC_4beq;\\\\n\\\\n// PC_j\\\\nassign PC_j = {pc_2[15],jump_shift_1};\\\\n\\\\n// PC_next\\\\nassign pc_next = (jump == 1\\'b1) ? PC_j : PC_4beq;\\\\n\\\\n// data memory\\\\ndata_memory datamem(.clk(clk),.mem_addr(ALU_out),\\\\n.mem_write(read_data_2),.mem_write_en(mem_write),.mem_read(mem_read),\\\\n.mem_read_data(mem_read_data));\\\\n\\\\n// write back\\\\nassign write_data = (mem_to_reg == 1\\'b0) ? pc_2:((mem_to_reg == 1\\'b1)? mem_read_data: ALU_out);\\\\n\\\\n// output\\\\nassign pc_out = pc_current;\\\\nassign alu_result = ALU_out;\\\\nassign instruction = instr;\\\\n endmodule']
["module alu(A, B, opcode, twoLSB, invA, invB, Cin, ALUOut, Zero, Pos, Neg);\\\\n\\\\n input [15:0] A, B;\\\\n input [4:0] opcode;\\\\n input [1:0] twoLSB;\\\\n input invA, invB, Cin;\\\\n\\\\n output reg [15:0] ALUOut;\\\\n output Zero, Pos, Neg;\\\\n\\\\n wire [15:0] signedA, signedB, ALU_ADD, ALUOut_arithmetic, BTROut;\\\\n wire g;\\\\n\\\\n // Invert inputs to ALU?\\\\n assign signedA = (invA) ? ~A : A;\\\\n assign signedB = (invB) ? ~B : B;\\\\n\\\\n // CLA for add operation\\\\n cla_16 cla1(.A(signedA), .B(signedB), .Cin(Cin), .sum(ALU_ADD), .Cout(), .Pout(), .Gout(g));\\\\n\\\\n // Which arithmetic operation?\\\\n mux4_1_16 mux0(.in1(ALU_ADD), .in2(ALU_ADD), .in3(signedA^signedB), .in4(signedA&signedB), .sel(twoLSB), .Out(ALUOut_arithmetic));\\\\n\\\\n // BTR (Bit Test and Rotate)\\\\n BTR btr1(.Out(BTROut), .In(A));\\\\n\\\\n // Flag Assignment (Zero, Pos, Neg)\\\\n assign Zero = (ALU_ADD == 16'h0000) ? 1'b1 : 1'b0;\\\\n assign Neg = (ALU_ADD[15] & ~Zero);\\\\n assign Pos = ~(ALU_ADD[15] | Zero);\\\\n\\\\n\\\\n/***************************************************\\\\n Shift/Rotate Operations\\\\n***************************************************/\\\\nwire [15:0] shift1out;\\\\nwire [15:0] shift2out;\\\\n\\\\nshifter shifter0 (.In(signedA), .Cnt(signedB[3:0]), .Op(opcode[1:0]), .Out(shift1out));\\\\nshifter shifter1 (.In(signedA), .Cnt(signedB[3:0]), .Op(twoLSB[1:0]), .Out(shift2out));\\\\n\\\\nalways @(*) begin \\\\n \\\\tALUOut = 16'hXXXX;\\\\n\\\\n\\\\t case(opcode)\\\\n\\\\n\\\\t 5'b00000: begin // Halt\\\\n end\\\\n\\\\n 5'b00001: begin // NOP\\\\n\\\\t end\\\\n \\\\n \\\\t 5'b01000: begin // ADDI\\\\n\\\\t\\\\t ALUOut = ALU_ADD;\\\\n \\\\t end\\\\n\\\\n \\\\t 5'b01001: begin // SUBI\\\\n\\\\t\\\\t ALUOut = ALU_ADD;\\\\n end\\\\n\\\\n \\\\t 5'b01010: begin // XORI\\\\n\\\\t \\\\t ALUOut = signedA ^ signedB;\\\\n end\\\\n\\\\n \\\\t 5'b01011: begin // ANDNI\\\\n\\\\t\\\\t ALUOut = signedA & signedB;\\\\n end\\\\n\\\\n \\\\t 5'b10100: begin // ROLI\\\\n\\\\t\\\\t ALUOut = shift1out;\\\\n end\\\\n\\\\n \\\\t 5'b10101: begin // SLLI\\\\n\\\\t\\\\t ALUOut = shift1out;\\\\n end\\\\n\\\\n \\\\t 5'b10110: begin // RORI\\\\n\\\\t\\\\t ALUOut = shift1out;\\\\n end\\\\n\\\\n \\\\t 5'b10111: begin // SRLI\\\\n\\\\t\\\\t ALUOut = shift1out;\\\\n \\\\t end\\\\n\\\\n \\\\t 5'b10000: begin // ST\\\\n\\\\t\\\\t ALUOut = ALU_ADD;\\\\n end\\\\n\\\\n \\\\t 5'b10001: begin // LD\\\\n\\\\t\\\\t ALUOut = ALU_ADD;\\\\n end\\\\n\\\\n \\\\t 5'b10011: begin // STU\\\\n\\\\t\\\\t ALUOut = ALU_ADD;\\\\n\\\\t end\\\\n\\\\n \\\\t 5'b11001: begin // BTR\\\\n\\\\t\\\\t ALUOut = BTROut;\\\\n end\\\\n\\\\n \\\\t 5'b11011: begin // ADD, SUB, XOR, ANDN\\\\n\\\\t\\\\t ALUOut = ALUOut_arithmetic;\\\\n end\\\\n\\\\n \\\\t 5'b11010: begin // ROL, SLL, ROR, SRL\\\\n\\\\t\\\\t ALUOut = shift2out;\\\\n \\\\t end\\\\n\\\\n \\\\t 5'b11100: begin // SEQ\\\\n\\\\t\\\\t ALUOut = (Zero) ? 16'h0001 : 16'h0000;\\\\n end\\\\n\\\\n \\\\t 5'b11101: begin // SLT\\\\n\\\\t\\\\t ALUOut = ((A[15] & ~B[15])|(Neg & ~(A[15] ^ B[15]))) ? 16'h0001 : 16'h0000;\\\\n end\\\\n\\\\n \\\\t 5'b11110: begin // SLE\\\\n\\\\t\\\\t ALUOut = (Zero|(A[15] & ~B[15])|(Neg & ~(A[15] ^ B[15]))) ? 16'h0001 : 16'h0000;\\\\n \\\\t end\\\\n\\\\n \\\\t 5'b11111: begin // SCO\\\\n\\\\t\\\\t ALUOut = (g) ? 16'h0001 : 16'h0000;\\\\n \\\\t end\\\\n\\\\n \\\\t 5'b01100: begin // BEQZ\\\\n\\\\t\\\\t ALUOut = ALU_ADD;\\\\n end\\\\n\\\\n \\\\t 5'b01101: begin // BNEZ\\\\n\\\\t\\\\t ALUOut = ALU_ADD;\\\\n \\\\t end\\\\n\\\\n \\\\t 5'b01110: begin // BLTZ\\\\n\\\\t\\\\t ALUOut = ALU_ADD;\\\\n \\\\t end\\\\n\\\\n \\\\t 5'b01111: begin // BGEZ\\\\n\\\\t\\\\t ALUOut = ALU_ADD;\\\\n end\\\\n\\\\n \\\\t 5'b11000: begin // LBI\\\\n\\\\t\\\\t ALUOut = B;\\\\n \\\\t end\\\\n\\\\n \\\\t 5'b10010: begin // SLBI\\\\n\\\\t\\\\t ALUOut = ((A << 8) | B);\\\\n end\\\\n\\\\n \\\\t 5'b00100: begin // J\\\\n\\\\t\\\\t ALUOut = ALU_ADD;\\\\n \\\\t end\\\\n\\\\n \\\\t 5'b00101: begin // JR\\\\n\\\\t\\\\t ALUOut = ALU_ADD;\\\\n \\\\t end\\\\n\\\\n \\\\t 5'b00110: begin // JAL\\\\n\\\\t\\\\t ALUOut = ALU_ADD;\\\\n \\\\t end\\\\n\\\\n \\\\t 5'b00111: begin // JALR\\\\n\\\\t\\\\t ALUOut = ALU_ADD;\\\\n end\\\\n\\\\n 5'b00010: begin // siic\\\\n\\\\n end\\\\n\\\\n \\\\t 5'b00011: begin // NOP / RTI\\\\n\\\\n \\\\t end\\\\n\\\\t \\\\n default: begin\\\\n end\\\\n endcase\\\\n end\\\\n\\\\nendmodule"]
["module alu(rst,clk_1,clk_2,accumulator,operand_2,status_in,alu_op,result,status_out);\\\\n\\\\ninput wire rst,clk_1,clk_2;\\\\ninput wire[7:0] accumulator,operand_2,status_in;\\\\ninput wire[3:0] alu_op;\\\\noutput wire[7:0] result,status_out;\\\\n\\\\nwire cout;\\\\nreg[7:0] accumulator_buffer,operand_2_buffer,status_buffer;\\\\nwire[7:0] result_buff;\\\\nparameter ADD=0,ADC=1,SBC=2,AND=3,EOR=4,ORA=5,BIT=6,ASL=7,LSR=8,ROL=9,ROR=10,PASS=11; //for alu\\\\nreg[6:0] alu_sel;\\\\n\\\\n//status reg contents : carry zero interrput_disable decimal_mode break_cmd overflow negative\\\\n\\\\nalways @(posedge rst ) begin\\\\n accumulator_buffer<=8'h00;\\\\n operand_2_buffer<=8'h00;\\\\n status_buffer<=8'h00;\\\\n alu_sel<=7'b0000000;\\\\nend\\\\n\\\\nalways @(posedge clk_2 ) begin\\\\n accumulator_buffer<=accumulator;\\\\n operand_2_buffer<=operand_2;\\\\n status_buffer<=status_in;\\\\n case(alu_op) \\\\n ADD: alu_sel<=7'b0000001;\\\\n ADC: alu_sel<=7'b0000001;\\\\n SBC: alu_sel<=7'b0000001;\\\\n AND: alu_sel<=7'b0000010;\\\\n EOR: alu_sel<=7'b0000100;\\\\n ORA: alu_sel<=7'b0001000;\\\\n BIT: alu_sel<=7'b0010000;\\\\n ASL: alu_sel<=7'b0100000;\\\\n ROL: alu_sel<=7'b0100000;\\\\n LSR: alu_sel<=7'b1000000;\\\\n ROR: alu_sel<=7'b1000000;\\\\n PASS: alu_sel<=7'b0000000;\\\\n endcase\\\\nend\\\\n\\\\nadder ad(alu_sel[0],(alu_op==SBC?1'b0:1'b1),accumulator_buffer,operand_2_buffer,status_buffer[7],result_buff,cout);\\\\nl_shift ls (alu_sel[5],(alu_op==ASL?1'b1:1'b0),status_buffer[7],accumulator_buffer,cout,result_buff);\\\\n\\\\nr_shift rs (alu_sel[6],(alu_op==LSR?1'b1:1'b0),status_buffer[7],accumulator_buffer,cout,result_buff);\\\\n\\\\nand_l an(alu_sel[1],accumulator_buffer,operand_2_buffer,result_buff);\\\\n\\\\neor_l eor(alu_sel[2],accumulator_buffer,operand_2_buffer,result_buff);\\\\n\\\\nora_l org(alu_sel[3],accumulator_buffer,operand_2_buffer,result_buff);\\\\n\\\\nbit_l bit(alu_sel[4],accumulator_buffer,operand_2_buffer,result_buff,status_out[2]);\\\\n\\\\nmux_2x1 #(8) m1(1'b1,|alu_sel,operand_2_buffer,result_buff,result);\\\\n\\\\nassign status_out[7]=(alu_sel[0]|alu_sel[5]|alu_sel[6])?cout:status_buffer[7]; //carry\\\\nassign status_out[6]=alu_op==PASS?status_buffer[6]:~|result_buff; //zero\\\\nassign status_out[5]=status_buffer[5]; //interrupt_disable\\\\nassign status_out[4]=status_buffer[4]; //decimal_mode\\\\nassign status_out[3]=status_buffer[3]; //break_cmd\\\\nassign status_out[2]=status_buffer[2]; //overflow\\\\nassign status_out[1]=alu_op==PASS?status_buffer[1]:result_buff[7]; //negative\\\\nassign status_out[0]=status_buffer[0]; //unused\\\\n\\\\n\\\\nendmodule", "module and_l (\\\\n en,operand_1,operand_2,result\\\\n);\\\\n\\\\ninput wire en;\\\\ninput wire [7:0] operand_1,operand_2;\\\\noutput wire[7:0] result;\\\\n\\\\nassign result=en?operand_1&operand_2:8'hzz;\\\\n \\\\nendmodule", "module eor_l (\\\\n en,operand_1,operand_2,result\\\\n);\\\\n\\\\ninput wire en;\\\\ninput wire [7:0] operand_1,operand_2;\\\\noutput wire[7:0] result;\\\\n\\\\nassign result=en?operand_1^operand_2:8'hzz;\\\\n \\\\nendmodule", "module ora_l (\\\\n en,operand_1,operand_2,result\\\\n);\\\\n\\\\ninput wire en;\\\\ninput wire [7:0] operand_1,operand_2;\\\\noutput wire[7:0] result;\\\\n\\\\nassign result=en?operand_1|operand_2:8'hzz;\\\\n \\\\nendmodule", "module bit_l (\\\\n en,operand_1,operand_2,result,over\\\\n);\\\\n\\\\ninput wire en;\\\\ninput wire [7:0] operand_1,operand_2;\\\\noutput wire[7:0] result;\\\\noutput wire over;\\\\n\\\\nassign result=en?operand_1&operand_2:8'hzz;\\\\nassign over=en?operand_2[6]:1'bz;\\\\nendmodule"]
['module nor2(input a , b , output w);\\\\n supply1 vdd;\\\\n supply0 gnd;\\\\n wire j;\\\\n pmos#(5,6,7) p1(j , vdd , a),\\\\n p2(w , j , b);\\\\n nmos#(3,4,5) n1(w , gnd , a),\\\\n n2(w , gnd , b);\\\\nendmodule', 'module demultiplexer_4Select(input serIn , [3:0] PB , output [3:0] P);\\\\n wire k , j0 , j1 , j2 , j3;\\\\n not #(5 , 7) not_k(k , serIn);\\\\n not #(5 , 7) not_j0(j0 , PB[0]);\\\\n not #(5 , 7) not_j1(j1 , PB[1]);\\\\n not #(5 , 7) not_j2(j2 , PB[2]);\\\\n not #(5 , 7) not_j3(j3 , PB[3]);\\\\n //nor #(10 , 14) cut_nor(P[0] , j0 , k);\\\\n nor2 nor_P0(j0 , k , P[0]);\\\\n nor2 nor_P1(j1 , k , P[1]);\\\\n nor2 nor_P2(j2 , k , P[2]);\\\\n nor2 nor_P3(j3 , k , P[3]);\\\\nendmodule', 'module demultiplexer_4Select_assign(input serIn , [3:0] PB , output [3:0] P);\\\\n wire k , j0 , j1 , j2 , j3;\\\\n assign #7 k = ~serIn;\\\\n assign #7 j0 = ~PB[0];\\\\n assign #7 j1 = ~PB[1];\\\\n assign #7 j2 = ~PB[2];\\\\n assign #7 j3 = ~PB[3];\\\\n assign #14 P[0] = ~(k | j0);\\\\n assign #14 P[1] = ~(k | j1);\\\\n assign #14 P[2] = ~(k | j2);\\\\n assign #14 P[3] = ~(k | j3);\\\\nendmodule', 'module demultiplexer_4selectTB();\\\\n reg serIn; \\\\n reg [3:0] PB;\\\\n wire [3:0] P_normal;\\\\n wire [3:0] P_assign;\\\\n demultiplexer_4Select cut_normal_demulti(serIn , PB , P_normal);\\\\n demultiplexer_4Select_assign cut_assign_demulti(serIn , PB , P_assign);\\\\n initial begin\\\\n #5 serIn = 1; PB[0] = 1; PB[1] = 0; PB[2] = 1; PB[3] = 0;\\\\n #30 PB[0] = 0; PB[1] = 1; PB[2] = 0; PB[3] = 1;\\\\n #25 PB[0] = 1; PB[2] = 1;\\\\n #30 PB[0] = 0; PB[1] = 0; PB[2] = 0; PB[3] = 0;\\\\n #25 serIn = 0; PB[0] = 1; PB[1] = 1; PB[2] = 1; PB[3] = 1;\\\\n #40 $stop;\\\\n end\\\\n \\\\nendmodule', 'module nor3(input a , b , c , output w);\\\\n supply1 vdd;\\\\n supply0 gnd;\\\\n wire j , k;\\\\n pmos#(5,6,7) p1(j , vdd , a),\\\\n p2(k , j , c),\\\\n p3(w , k , b);\\\\n nmos#(3,4,5) n1(w , gnd , a),\\\\n n2(w , gnd , b),\\\\n n3(w , gnd , c);\\\\nendmodule', 'module demultiplexer_2select(input serIn , [0:1] LB , output [0:3] L);\\\\n wire k , j0 , j1;\\\\n not #(5 , 7) not_k(k , serIn);\\\\n not #(5 , 7) not_j0(j0 , LB[0]);\\\\n not #(5 , 7) not_j1(j1 , LB[1]);\\\\n //nor #(15 , 21) cut_nor(L[0] , LB[0] , LB[1] , k);\\\\n nor3 nor_L0(LB[0] , LB[1] , k , L[0]);\\\\n nor3 nor_L1(LB[0] , j1 , k , L[1]);\\\\n nor3 nor_L2(j0 , j1 , k , L[2]);\\\\n nor3 nor_L3(j0 , LB[1] , k , L[3]);\\\\n \\\\nendmodule', 'module demultiplexer_2select_assign(input serIn , [0:1] LB , output [0:3] L);\\\\n wire k , j0 , j1;\\\\n assign #7 k = ~serIn;\\\\n assign #7 j0 = ~LB[0];\\\\n assign #7 j1 = ~LB[1];\\\\n assign #21 L[0] = ~(LB[0] | LB[1] | k);\\\\n assign #21 L[1] = ~(LB[0] | j1 | k);\\\\n assign #21 L[2] = ~(j0 | j1 | k);\\\\n assign #21 L[3] = ~(j0 | LB[1] | k);\\\\nendmodule', 'module demultiplexer_2selectTB();\\\\n reg serIn; reg [0:1] LB;\\\\n wire[0:3] L_normal;\\\\n wire[0:3] L_assign;\\\\n demultiplexer_2select cut_normal_demulti2(serIn , LB , L_normal);\\\\n demultiplexer_2select_assign cut_assign_demulti2(serIn , LB , L_assign);\\\\n initial begin\\\\n #5 serIn = 1; LB[0] = 0; LB[1] = 0;\\\\n #30 LB[1] = 1; \\\\n #35 LB[0] = 1;\\\\n #30 LB[1] = 0; \\\\n #40 $stop;\\\\n end\\\\n \\\\nendmodule', 'module broadcaster(input serIn , [3:0] PB , [0:1] LB0 , [0:1] LB1 , [0:1] LB2 , [0:1] LB3 , output [0:3] lines0 , [0:3] lines1 , [0:3] lines2 , [0:3] lines3);\\\\n wire [3:0] j;\\\\n demultiplexer_4Select cut_demulti_4select_ports(serIn , PB , j);\\\\n demultiplexer_2select cut_demulti_2select_0(j[0] , LB0 , lines0);\\\\n demultiplexer_2select cut_demulti_2select_1(j[1] , LB1 , lines1);\\\\n demultiplexer_2select cut_demulti_2select_2(j[2] , LB2 , lines2);\\\\n demultiplexer_2select cut_demulti_2select_3(j[3] , LB3 , lines3);\\\\n \\\\nendmodule', 'module broadcaster_assign(input serIn , [3:0] PB , [0:1] LB0 , [0:1] LB1 , [0:1] LB2 , [0:1] LB3 , output [0:3] lines0 , [0:3] lines1 , [0:3] lines2 , [0:3] lines3);\\\\n wire [0:3] j;\\\\n assign j[0] = PB[0] ? serIn : 0;\\\\n assign #21 j[1] = PB[1] ? serIn : 0;\\\\n assign #21 j[2] = PB[2] ? serIn : 0;\\\\n assign #21 j[3] = PB[3] ? serIn : 0;\\\\n \\\\n assign #28 lines0[0] = LB0[0] ? (LB0[1]? 0 : 0) : (LB0[1]? 0 : j[0]);\\\\n assign #28 lines0[1] = LB0[0] ? (LB0[1]? 0 : j[0]) : (LB0[1]? 0 : 0);\\\\n assign #28 lines0[2] = LB0[0] ? (LB0[1]? 0 : 0) : (LB0[1]? j[0] : 0);\\\\n assign #28 lines0[3] = LB0[0] ? (LB0[1]? j[0] : 0) : (LB0[1]? 0 : 0);\\\\n \\\\n assign #28 lines1[0] = LB1[0] ? (LB1[1]? 0 : 0) : (LB1[1]? 0 : j[1]);\\\\n assign #28 lines1[1] = LB1[0] ? (LB1[1]? 0 : j[1]) : (LB1[1]? 0 : 0);\\\\n assign #28 lines1[2] = LB1[0] ? (LB1[1]? 0 : 0) : (LB1[1]? j[1] : 0);\\\\n assign #28 lines1[3] = LB1[0] ? (LB1[1]? j[1] : 0) : (LB1[1]? 0 : 0);\\\\n \\\\n assign #28 lines2[0] = LB2[0] ? (LB2[1]? 0 : 0) : (LB2[1]? 0 : j[2]);\\\\n assign #28 lines2[1] = LB2[0] ? (LB2[1]? 0 : j[2]) : (LB2[1]? 0 : 0);\\\\n assign #28 lines2[2] = LB2[0] ? (LB2[1]? 0 : 0) : (LB2[1]? j[2] : 0);\\\\n assign #28 lines2[3] = LB2[0] ? (LB2[1]? j[2] : 0) : (LB2[1]? 0 : 0);\\\\n \\\\n assign #28 lines3[0] = LB3[0] ? (LB3[1]? 0 : 0) : (LB3[1]? 0 : j[3]);\\\\n assign #28 lines3[1] = LB3[0] ? (LB3[1]? 0 : j[3]) : (LB3[1]? 0 : 0);\\\\n assign #28 lines3[2] = LB3[0] ? (LB3[1]? 0 : 0) : (LB3[1]? j[3] : 0);\\\\n assign #28 lines3[3] = LB3[0] ? (LB3[1]? j[3] : 0) : (LB3[1]? 0 : 0);\\\\n \\\\nendmodule', 'module broadcasterTB();\\\\n reg serIn = 1;\\\\n reg [3:0] PB; reg [0:1] LB0 , LB1 , LB2 , LB3;\\\\n wire [0:3] lines0_normal , lines1_normal , lines2_normal , lines3_normal;\\\\n wire [0:3] lines0_assign , lines1_assign , lines2_assign , lines3_assign;\\\\n broadcaster cut_broadcaster(serIn , PB , LB0 , LB1 , LB2 , LB3 , lines0_normal , lines1_normal , lines2_normal , lines3_normal);\\\\n broadcaster_assign cut_assign_broadcaster(serIn , PB , LB0 , LB1 , LB2 , LB3 , lines0_assign , lines1_assign , lines2_assign , lines3_assign);\\\\n initial begin\\\\n #5 PB[0] = 1; PB[1] = 0; PB[2] = 0; PB[3] = 0; LB0[0] = 0 ; LB0[1] = 0;\\\\n #50 LB0[0] = 1;\\\\n #45 LB0[1] = 1 ; LB0[0] = 0;\\\\n #50 LB0[0] = 1;\\\\n \\\\n #45 PB[1] = 1; LB1[0] = 0 ; LB1[1] = 0;\\\\n #50 LB1[0] = 1;\\\\n #55 LB1[1] = 1 ; LB1[0] = 0;\\\\n #50 LB1[0] = 1;\\\\n \\\\n #45 PB[2] = 1; LB2[0] = 0 ; LB2[1] = 0;\\\\n #50 LB2[0] = 1;\\\\n #55 LB2[1] = 1 ; LB2[0] = 0;\\\\n #50 LB2[0] = 1;\\\\n \\\\n #45 PB[3] = 1; LB3[0] = 0 ; LB3[1] = 0;\\\\n #50 LB3[0] = 1;\\\\n #55 LB3[1] = 1 ; LB3[0] = 0;\\\\n #50 LB3[0] = 1;\\\\n \\\\n #45 serIn = 0;\\\\n PB[0] = 1; LB0[0] = 1; LB0[1] = 1;\\\\n PB[1] = 1; LB1[0] = 1; LB1[1] = 1;\\\\n PB[2] = 1; LB2[0] = 1; LB2[1] = 1;\\\\n PB[3] = 1; LB3[0] = 1; LB3[1] = 1;\\\\n \\\\n #50 serIn = 1;\\\\n PB[1] = 0;\\\\n LB0[0] = 1; LB0[1] = 0;\\\\n LB1[0] = 1; LB1[1] = 1;\\\\n LB2[0] = 0; LB2[1] = 1;\\\\n LB3[0] = 0; LB3[1] = 0;\\\\n \\\\n #20;\\\\n repeat(5) #60 serIn = ~serIn;\\\\n \\\\n #70 $stop;\\\\n end\\\\n \\\\nendmodule']
["module top(CLK_temp, RST, serial_clk, lr_clk, serial_in, clk_out, serial_out, LE);\\\\ninput CLK_temp, RST, serial_clk, lr_clk, serial_in;\\\\noutput clk_out, serial_out, LE;\\\\nwire rst; //General\\\\nwire clk;\\\\nwire rin, lin; //Vrshftreg\\\\nwire [2:0] sA, sB, sC;\\\\nwire [15:0] dA, dB, dC;\\\\nwire [15:0] qA, qB, qC; \\\\nwire [15:0] sample; //pcm2706_interface\\\\nwire data_rdy, serial_in_sync, serial_clk_sync, lr_clk_sync;\\\\nwire [15:0] sample1, sample2; //interpolate\\\\n\\\\nwire [16:0] d; //need extra bit to span possible outcomes (ex: max positive - (max negative))\\\\nwire [15:0] d_div_temp;\\\\nreg [15:0] d_div;\\\\nwire [15:0] sum_output_temp;\\\\nreg [15:0] sum_output;\\\\n\\\\n\\\\nwire ld_shifting_counter, ENT, ENP_interp_counter;\\\\n\\\\nwire [3:0] ld_cnt_interpolate_counter;\\\\nwire [3:0] interp_cnt_out, shifting_cnt_out, clk_div_cnt_out;\\\\nwire rco_clk_div;\\\\nwire shifting_done;\\\\nwire interpolate_done;\\\\nwire init;\\\\n\\\\nwire sample_rdy;\\\\n\\\\nassign clk = CLK_temp;\\\\n\\\\n synchronizer synchronizer_clk (.clk(clk),\\\\n .rst(rst),\\\\n .in(serial_clk),\\\\n .out(serial_clk_sync));\\\\n \\\\n synchronizer synchronizer_data (.clk(clk),\\\\n .rst(rst),\\\\n .in(serial_in),\\\\n .out(serial_in_sync));\\\\n\\\\n synchronizer synchronizer_LRclk (.clk(clk),\\\\n .rst(rst),\\\\n .in(lr_clk),\\\\n .out(lr_clk_sync)); \\\\n\\\\n VrSMex_pipelined VrSMex1 (.CLOCK(clk),\\\\n .RESET(rst),\\\\n .Data_RDY(data_rdy),\\\\n .interpolate_count(ld_interp_counter),\\\\n .shift_done(shifting_done),\\\\n .RegA(sA),\\\\n .RegB(sB),\\\\n .RegC(sC),\\\\n .interpolate_count_ENP(ENP_interp_counter),\\\\n .init_C(init),\\\\n .sample_rdy(sample_rdy));\\\\n \\\\n pcm2706_interface pcm2706_interface1 (.sysclk(clk),\\\\n .RST(rst),\\\\n .serial_clk(serial_clk_sync),\\\\n .lr_clk(lr_clk_sync),\\\\n .serial_in(serial_in_sync),\\\\n .parallel_out(sample),\\\\n .data_rdy(data_rdy));\\\\n \\\\n Vrshftreg VrshftregA (.CLK(clk),\\\\n .RST(rst),\\\\n .RIN(rin),\\\\n .LIN(lin),\\\\n .S(sA),\\\\n .D(dA),\\\\n .Q(qA));\\\\n \\\\n Vrshftreg VrshftregB (.CLK(clk),\\\\n .RST(rst),\\\\n .RIN(rin),\\\\n .LIN(lin),\\\\n .S(sB),\\\\n .D(dB),\\\\n .Q(qB));\\\\n \\\\n Vrshftreg VrshftregC (.CLK(clk),\\\\n .RST(rst),\\\\n .RIN(rin),\\\\n .LIN(lin),\\\\n .S(sC),\\\\n .D(dC),\\\\n .Q(qC)); \\\\n \\\\n Vrsubtract #(17) difference (.A({sample2[15], sample2}),\\\\n .B({sample1[15],sample1}),\\\\n .D(d),\\\\n .OVFL());\\\\n \\\\n assign d_div_temp = {d[16],d[16],d[16],d[16:4]}; \\\\n\\\\n always @ (posedge clk)\\\\n if (rst==1) d_div <= 16'b0;\\\\n else d_div <= d_div_temp;\\\\n\\\\n Vradders Vradder (.A(qC),\\\\n .B(d_div),\\\\n .S(sum_output_temp),\\\\n .OVFL()); \\\\n \\\\n always @ (posedge clk)\\\\n if (rst==1) sum_output <= 16'b0;\\\\n else sum_output <= sum_output_temp;\\\\n \\\\n pcm1702_interface pcm1702_interface1 (.clk(clk),\\\\n .rst(rst),\\\\n .sample_rdy(sample_rdy),\\\\n .data(qC),\\\\n .shift_done(shifting_done),\\\\n .clk_out(clk_out),\\\\n .serial_out(serial_out),\\\\n .LE(LE)); \\\\n \\\\n Vr74x163 interp_counter (.CLK(clk),\\\\n .CLR(rst),\\\\n .LD(ld_interp_counter),\\\\n .ENP(ENP_interp_counter),\\\\n .ENT(ENT),\\\\n .D(ld_cnt_interpolate_counter),\\\\n .Q(interp_cnt_out),\\\\n .RCO()); \\\\n \\\\n \\\\n///PCM1702 test register\\\\n\\\\nwire signed [19:0] test_output;\\\\n\\\\nVrshftreg #(20) test_unit (.CLK(clk_out),\\\\n .RST(!LE && clk_out),\\\\n .RIN(1'b0),\\\\n .LIN(serial_out),\\\\n .S(3'd3),\\\\n .D(20'b0),\\\\n .Q(test_output)); \\\\n\\\\nassign ENT = 1'b1;\\\\nassign ld_cnt_interpolate_counter = 4'b0; \\\\nassign rst = RST;\\\\nassign rin = 1'b0;\\\\nassign lin = 1'b0;\\\\n\\\\nassign dA = qB;\\\\nassign dB = sample;\\\\nassign dC = init ? qA : sum_output;\\\\n\\\\nassign sample1 = qA;\\\\nassign sample2 = qB;\\\\n\\\\nassign ld_interp_counter = interp_cnt_out[3] && interp_cnt_out[2] && interp_cnt_out[1] && interp_cnt_out[0];\\\\n\\\\nendmodule"]
['module REG8out(clk,rst_n,in,out,s);\\\\nparameter N=8;\\\\ninput clk,s,rst_n;\\\\ninput signed [N-1:0] in;\\\\noutput signed [N-1:0] out;\\\\nwire signed [N-1:0] wire1;\\\\nwire signed [N-1:0] wire2;\\\\nwire signed [N-1:0] wire3;\\\\nwire signed [N-1:0] wire4;\\\\nwire signed [N-1:0] wire5;\\\\nwire signed [N-1:0] wire6;\\\\nwire signed [N-1:0] wire7;\\\\nwire signed [N-1:0] wire8;\\\\nwire signed [N-1:0] wire9;\\\\nwire signed [N-1:0] wire10;\\\\nwire signed [N-1:0] wire11;\\\\n\\\\n\\\\nREG8_hold reg8hold1(clk,rst_n,in,wire1,s);\\\\nREG8_hold reg8hold2(clk,rst_n,wire1,wire2,s);\\\\nREG8_hold reg8hold3(clk,rst_n,wire2,wire3,s);\\\\nREG8_hold reg8hold4(clk,rst_n,wire3,wire4,s);\\\\nREG8_hold reg8hold5(clk,rst_n,wire4,wire5,s);\\\\nREG8_hold reg8hold6(clk,rst_n,wire5,wire6,s);\\\\nREG8_hold reg8hold7(clk,rst_n,wire6,wire7,s);\\\\nREG8_hold reg8hold8(clk,rst_n,wire7,wire8,s);\\\\nREG8_hold reg8hold9(clk,rst_n,wire8,wire9,s);\\\\nREG8_hold reg8hold10(clk,rst_n,wire9,wire10,s);\\\\nREG8_hold reg8hold11(clk,rst_n,wire10,wire11,s);\\\\nREG8_hold reg8hold12(clk,rst_n,wire11,out,s);\\\\n\\\\nendmodule']
['module RAM (Din, address, Dout, clk, rw);\\\\n\\\\ninput [31:0] Din;\\\\ninput [7:0] address;\\\\ninput clk, rw;\\\\n\\\\noutput [31:0] Dout;\\\\n\\\\n\\\\nwire [3:0] CS;\\\\nwire [31:0] dout0, dout1, dout2, dout3; //for each output of 64x8 ram\\\\n\\\\n//instantating decoder:\\\\n//module decoder2to4(in, ou0, ou1, ou2, ou3);\\\\n\\\\nRamDecoder u0(address[7:6], CS);\\\\n\\\\n/*\\\\nisntantating 64x8 ram:\\\\n\\\\"call 16 times. 32 btis for each row and column. dout[3:0] = row & Din[31:0] = column.\\\\"\\\\n*/\\\\n\\\\n//smallRAM (rw, dataIn, CS, address[5:0], clk, dataOut);\\\\n\\\\nsmallRAM m0(rw, Din[7:0], CS[0], address[5:0], clk, dout0[7:0]);\\\\nsmallRAM m1(rw, Din[15:8], CS[0], address[5:0], clk, dout0[15:8]);\\\\nsmallRAM m2(rw, Din[23:16], CS[0], address[5:0], clk, dout0[23:16]);\\\\nsmallRAM m3(rw, Din[31:24], CS[0], address[5:0], clk, dout0[31:24]);\\\\n\\\\nsmallRAM m4(rw, Din[7:0], CS[1], address[5:0], clk, dout1[7:0]);\\\\nsmallRAM m5(rw, Din[15:8], CS[1], address[5:0], clk, dout1[15:8]);\\\\nsmallRAM m6(rw, Din[23:16], CS[1], address[5:0], clk, dout1[23:16]);\\\\nsmallRAM m7(rw, Din[31:24], CS[1], address[5:0], clk, dout1[31:24]);\\\\n\\\\nsmallRAM m8(rw, Din[7:0], CS[2], address[5:0], clk, dout2[7:0]);\\\\nsmallRAM m9(rw, Din[15:8], CS[2], address[5:0], clk, dout2[15:8]);\\\\nsmallRAM m10(rw, Din[23:16], CS[2], address[5:0], clk, dout2[23:16]);\\\\nsmallRAM m11(rw, Din[31:24], CS[2], address[5:0], clk, dout2[31:24]);\\\\n\\\\nsmallRAM m12(rw, Din[7:0], CS[3], address[5:0], clk, dout3[7:0]);\\\\nsmallRAM m13(rw, Din[15:8], CS[3], address[5:0], clk, dout3[15:8]);\\\\nsmallRAM m14(rw, Din[23:16], CS[3], address[5:0], clk, dout3[23:16]);\\\\nsmallRAM m15(rw, Din[31:24], CS[3], address[5:0], clk, dout3[31:24]);\\\\n\\\\n\\\\n//selecting specific row for output\\\\nassign Dout= CS[0]? dout0: \\'bz;\\\\nassign Dout= CS[1]? dout1: \\'bz;\\\\nassign Dout= CS[2]? dout2: \\'bz;\\\\nassign Dout= CS[3]? dout3: \\'bz;\\\\n\\\\nendmodule']
["module except to change an output type (reg/wire).\\\\nmodule timed_electronic_safe(input clk, rst_n, input [17:0] SW, input action_n, output reg[6:0] HEX7, HEX6, HEX5, HEX4, HEX2, HEX1, HEX0, output reg [3:0] LEDG);\\\\n\\\\n\\\\t//Time\\\\n\\\\tlocalparam tmax = 10'd750;\\\\n\\\\tlocalparam BITS_timer = 10;\\\\n\\\\n\\\\t// States\\\\n\\\\tlocalparam S_ENTRY = 3'd0;\\\\n\\\\tlocalparam S_TRY_1 = 3'd1;\\\\n\\\\tlocalparam S_TRY_2 = 3'd2;\\\\n\\\\tlocalparam S_TRY_3 = 3'd3;\\\\n\\\\tlocalparam S_UNLOCK = 3'd4;\\\\n\\\\n\\\\t// State register\\\\n\\\\treg [2:0] state;\\\\n\\\\t\\\\n\\\\t//timer \\\\n\\\\treg [BITS_timer-1:0] t;\\\\n \\\\n\\\\twire action_counter;\\\\n\\\\treg [5:0] code_1,code_2,code_3;\\\\n\\\\treg [5:0] try_1,try_2,try_3, try_1_sig;\\\\n\\\\t\\\\n\\\\twire [6:0] disp_0,disp_1,disp_2,disp_4,disp_5,disp_6,disp_7, error_ssd0, error_ssd1, error_ssd2;\\\\n\\\\t\\\\n\\\\treg [8:0] error_count;\\\\n\\\\twire [3:0] error_0,error_1,error_2;\\\\n\\\\t\\\\n\\\\twire [3:0] disp_0_sig, disp_1_sig, disp_2_sig, disp_4_sig, disp_5_sig, disp_6_sig, disp_7_sig;\\\\n\\\\t\\\\n\\\\taction_counter action_counter1(.action_n(action_n), .clk(clk), .rst(rst_n), .action_counter(action_counter));\\\\n\\\\n\\\\n\\\\t\\\\n\\\\tbcd_converter display0(.value(error_count),.hund(error_2), .tens(error_1), .ones(error_0));\\\\n\\\\tSSD_converter ssd_converter_E2(.SSD_in(error_2), .SSD_out(error_ssd2));\\\\n\\\\tSSD_converter ssd_converter_E1(.SSD_in(error_1), .SSD_out(error_ssd1));\\\\n\\\\tSSD_converter ssd_converter_E0(.SSD_in(error_0), .SSD_out(error_ssd0));\\\\n\\\\t\\\\t\\\\n\\\\tbcd_converter display3(.value({3'd0,SW[17:12]}),.tens(disp_7_sig), .ones(disp_6_sig));\\\\n\\\\tbcd_converter display2(.value({3'd0,SW[11:6]}), .tens(disp_5_sig), .ones(disp_4_sig));\\\\n\\\\tbcd_converter display1(.value({3'd0,SW[5:0]}), .tens(disp_1_sig), .ones(disp_0_sig));\\\\n\\\\n\\\\tSSD_converter ssd_converter_5(.SSD_in(disp_7_sig), .SSD_out(disp_7));\\\\n\\\\tSSD_converter ssd_converter_4(.SSD_in(disp_6_sig), .SSD_out(disp_6));\\\\n\\\\tSSD_converter ssd_converter_3(.SSD_in(disp_5_sig), .SSD_out(disp_5));\\\\n\\\\tSSD_converter ssd_converter_2(.SSD_in(disp_4_sig), .SSD_out(disp_4));\\\\n\\\\tSSD_converter ssd_converter_1(.SSD_in(disp_1_sig), .SSD_out(disp_1));\\\\n\\\\tSSD_converter ssd_converter_0(.SSD_in(disp_0_sig), .SSD_out(disp_0));\\\\n\\\\n\\\\n\\\\t// State machine always block, including both next state logic and state register\\\\n\\\\talways @ (posedge clk, negedge rst_n) begin\\\\n\\\\t\\\\tif( rst_n == 1'b0) begin\\\\n\\\\t\\\\t\\\\tstate <= S_ENTRY;\\\\n\\\\t\\\\t\\\\tt <= 5'd0;\\\\n\\\\t\\\\tend\\\\n\\\\t\\\\telse begin\\\\n\\\\t\\\\tt <= t+1;\\\\n\\\\t\\\\t\\\\tcase( state )\\\\n\\\\t\\\\t\\\\t\\\\tS_ENTRY: begin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tcode_1 <= SW[5:0];\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tcode_2 <= SW[11:6];\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tcode_3 <= SW[17:12];\\\\n\\\\t\\\\t\\\\t\\\\t\\\\terror_count <= 9'd0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tif(action_counter == 1) begin \\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tstate <= S_TRY_1;\\\\t\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\terror_count <= 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tt<= 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tend \\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t\\\\t\\\\n\\\\t\\\\t\\\\t\\\\tS_TRY_1: begin\\\\n\\\\t\\\\t\\\\t\\\\t// t <= t+1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\ttry_1 <= SW[5:0];\\\\t\\\\t\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tif (action_counter && t<tmax) begin\\\\t \\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tif( code_3 == try_1 )\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tstate <= S_TRY_2;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\telse begin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tstate <= S_TRY_1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\terror_count = error_count +9'd1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t\\\\t\\\\telse if(t>tmax) begin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tstate <= S_TRY_1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tt <= 0; \\\\n\\\\t\\\\t\\\\t\\\\t\\\\tend \\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\n\\\\t\\\\t\\\\t\\\\tS_TRY_2: begin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\ttry_2 <= SW[5:0];\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tif (action_counter && t<tmax) begin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tif( code_2 == try_2)\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tstate <= S_TRY_3;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\telse begin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tstate <= S_TRY_2;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\terror_count = error_count +9'd1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t\\\\t\\\\telse if(t>tmax) begin \\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tstate <= S_TRY_1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tt <= 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tend \\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\n\\\\t\\\\t\\\\t\\\\tS_TRY_3: begin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\ttry_3 <= SW[5:0];\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tif (action_counter && t<tmax) begin \\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tif( code_1 == try_3)\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tstate <= S_UNLOCK;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\telse begin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tstate <= S_TRY_3;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\terror_count = error_count +9'd1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t\\\\t\\\\telse if(t>tmax) begin \\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tstate <= S_TRY_1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tt <= 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\n\\\\t\\\\t\\\\t\\\\tS_UNLOCK: begin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tif(action_counter) begin \\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tstate <= S_ENTRY;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\terror_count <= 9'd0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tt <= 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\n\\\\t\\\\t\\\\t\\\\tdefault: begin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tstate <= S_ENTRY;\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\tendcase\\\\n\\\\t\\\\tend\\\\n\\\\tend\\\\n\\\\n\\\\t// Output logic always block\\\\n\\\\talways @ (*) begin\\\\n\\\\t\\\\tcase( state )\\\\n\\\\t\\\\t\\\\tS_ENTRY: begin\\\\n\\\\t\\\\t\\\\t\\\\tHEX7 <= disp_7; HEX6 <= disp_6; \\\\n\\\\t\\\\t\\\\t\\\\tHEX5 <= disp_5; HEX4 <= disp_4; HEX2 <= 7'b1000000; HEX1 <= disp_1; HEX0 <= disp_0; LEDG<= 4'b0000;\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t\\\\n\\\\t\\\\t\\\\tS_TRY_1: begin\\\\n\\\\t\\\\t\\\\t\\\\tHEX7 <= 7'b1111111; HEX6 <= 7'b1000111; \\\\n\\\\t\\\\t\\\\t\\\\tHEX5 <= disp_1 ; HEX4 <= disp_0; HEX2 <= error_ssd2; HEX1 <= error_ssd1; HEX0 <= error_ssd0; LEDG<= 4'b0001;\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t\\\\n\\\\t\\\\t\\\\tS_TRY_2: begin\\\\n\\\\t\\\\t\\\\t\\\\tHEX7 <= 7'b1111111; HEX6 <= 7'b1000111; \\\\n\\\\t\\\\t\\\\t\\\\tHEX5 <= disp_1 ; HEX4 <= disp_0; HEX2 <= error_ssd2; HEX1 <= error_ssd1; HEX0 <= error_ssd0; LEDG<= 4'b0011;\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t\\\\n\\\\t\\\\t\\\\tS_TRY_3: begin\\\\n\\\\t\\\\t\\\\t\\\\tHEX7 <= 7'b1111111; HEX6 <= 7'b1000111; \\\\n\\\\t\\\\t\\\\t\\\\tHEX5 <= disp_1 ; HEX4 <= disp_0; HEX2 <= error_ssd2; HEX1 <= error_ssd1; HEX0 <= error_ssd0; LEDG<= 4'b0111;\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t\\\\n\\\\t\\\\t\\\\tS_UNLOCK: begin\\\\n\\\\t\\\\t\\\\t\\\\tHEX7 <= 7'b1111111; HEX6 <= 7'b1000001; \\\\n\\\\t\\\\t\\\\t\\\\tHEX5 <= 7'b1000000 ; HEX4 <= 7'b1000000; HEX2 <= error_ssd2; HEX1 <= error_ssd1; HEX0 <= error_ssd0; LEDG<= 4'b1111;\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\tdefault: begin\\\\n\\\\t\\\\t\\\\t\\\\tHEX7 <= disp_7; HEX6 <= disp_6; HEX5 <= disp_5; HEX4 <= disp_4; HEX2 <= 7'b1000000; HEX1 <= disp_1; HEX0 <= disp_0; LEDG<= 4'b0000;\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\tendcase\\\\n\\\\tend\\\\nendmodule", 'modules below. They are setup to provide a clock divider\\\\n * for your main module and allow the testbench to run at that slower clock\\\\n * rate.\\\\n */\\\\nmodule timed_electronic_safe_top(input clk_in, rst_n, input [17:0] SW, input action_n, output [6:0] HEX7, HEX6, HEX5, HEX4, HEX2, HEX1, HEX0, output [3:0] LEDG);\\\\n\\\\twire clk;\\\\n\\\\tclk_divider c0 (.clk_in(clk_in), .rst_n(rst_n), .clk_out(clk));\\\\n\\\\ttimed_electronic_safe device(clk, rst_n, SW, action_n, HEX7, HEX6, HEX5, HEX4, HEX2, HEX1, HEX0, LEDG);\\\\nendmodule', 'module clk_divider(input clk_in, rst_n, output clk_out);\\\\n\\\\tlocalparam BITS = 21;\\\\n\\\\treg [BITS-1:0] cnt;\\\\n\\\\t\\\\n\\\\talways @ (posedge clk_in) begin\\\\n\\\\t\\\\tif( ~rst_n ) begin\\\\n\\\\t\\\\t\\\\tcnt <= 0;\\\\n\\\\t\\\\tend\\\\n\\\\t\\\\telse begin\\\\n\\\\t\\\\t\\\\tcnt <= cnt + 1;\\\\n\\\\t\\\\tend\\\\n\\\\tend\\\\n\\\\t\\\\n\\\\tassign clk_out = cnt[BITS-1];\\\\nendmodule']
["module bol_320_control(\\\\n\\\\ninput wire CLK_10,\\\\ninput wire CLK_6_6,\\\\n\\\\ninput wire RESET,\\\\ninput wire GLOBAL_RESET,\\\\ninput wire BL_ENABLE,\\\\noutput BL_SYT,\\\\noutput BL_SYP,\\\\noutput BL_SYL,\\\\noutput BL_SIZE,\\\\n\\\\noutput BUF_IN_EN,\\\\noutput WRITE_EN,\\\\noutput reg BUFER_CHANGE,\\\\noutput [9:0] CNT_ROW\\\\n);\\\\n\\\\n\\\\n\\\\n\\\\nreg [3:0]state=4'b0000;\\\\nreg [15:0]cnt=16'b0;\\\\nreg [9:0]cnt_row=10'b0;\\\\nreg [15:0] dalay_shift=15'b0;\\\\n\\\\n\\\\nwire datavalid;\\\\nwire clk_bol;\\\\nparameter S_IDLE=0;\\\\nparameter S_RESET_UP=1;\\\\nparameter S_PAUSE=2;\\\\nparameter S_ROW_UP=3;\\\\nparameter S_ROW_DOWN1=4;\\\\nparameter S_PIX_OUT=5;\\\\nparameter S_ROW_DOWN2=6;\\\\nparameter S_CHANGE_BUF=7;\\\\nparameter S_MEM_UP=8;\\\\n\\\\n\\\\nparameter RESET_BOL=320;\\\\nparameter RESET_LINE=47;\\\\nparameter PAUSE_PIX=20;\\\\nparameter PAUSE=15; \\\\n\\\\nassign BL_SYT=(state==S_RESET_UP)? 1'b1 : 1'b0; // reset_up SYT \\\\nassign BL_SYL=(state==S_ROW_UP)? 1'b1 : 1'b0; // row_up SYL \\\\n\\\\nassign datavalid=(state==S_PIX_OUT)? 1'b1 : 1'b0; // pix_out \\\\n\\\\nassign datavalid_mem=((state==S_PIX_OUT)&&(cnt_row>0))? 1'b1 : 1'b0; // pix_out \\\\n\\\\nassign clk_bol=datavalid & BL_ENABLE;\\\\nassign BL_SYP=CLK_6_6 & clk_bol;\\\\nassign WRITE_EN=((state==S_MEM_UP)&&(cnt_row>1)) ? 1'b1:1'b0;\\\\nassign CNT_ROW=(cnt_row>1) ? (cnt_row-2) :10'b0; \\\\nassign BL_SIZE=1'b0;\\\\nalways @(posedge CLK_10 or posedge RESET or posedge GLOBAL_RESET)\\\\nbegin\\\\n\\\\tif (GLOBAL_RESET)\\\\n\\\\tbegin\\\\n\\\\t\\\\tstate<=S_IDLE;\\\\n\\\\t\\\\tcnt<=16'b0;\\\\n\\\\t\\\\tcnt_row<=10'b0;\\\\n\\\\t\\\\tBUFER_CHANGE<=1'b0;\\\\n\\\\tend\\\\n\\\\n\\\\telse if (RESET)\\\\n\\\\tbegin\\\\n\\\\t\\\\tstate<=S_RESET_UP;\\\\n\\\\t\\\\tcnt<=16'b0;\\\\n\\\\t\\\\tcnt_row<=10'b0;\\\\n\\\\t\\\\tBUFER_CHANGE<=1'b0;\\\\n\\\\tend\\\\n\\\\telse\\\\n\\\\tbegin\\\\n\\\\t\\\\tcase(state)\\\\n\\\\t\\\\t\\\\t\\\\n\\\\t\\\\t\\\\tS_RESET_UP:begin\\\\n\\\\t\\\\t\\\\t\\\\tcnt<=cnt+1'b1;\\\\n\\\\t\\\\t\\\\t\\\\tif (cnt==RESET_BOL)\\\\n\\\\t\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tcnt<=16'b0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tstate<=S_PAUSE;\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\tS_PAUSE:begin\\\\n\\\\t\\\\t\\\\t\\\\tcnt<=cnt+1'b1;\\\\n\\\\t\\\\t\\\\t\\\\tif (cnt==PAUSE)\\\\n\\\\t\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tcnt<=16'b0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tstate<=S_ROW_UP;\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\tS_ROW_UP:begin // \\\\n\\\\t\\\\t\\\\t\\\\tcnt<=cnt+1'b1;\\\\n\\\\t\\\\t\\\\t\\\\tif (cnt==RESET_LINE)\\\\n\\\\t\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tcnt<=16'b0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tstate<=S_ROW_DOWN1;\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\tS_ROW_DOWN1:begin // \\\\n\\\\t\\\\t\\\\t\\\\tcnt<=cnt+1'b1;\\\\n\\\\t\\\\t\\\\t\\\\tif (cnt==PAUSE)\\\\n\\\\t\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tcnt<=16'b0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tstate<=S_PIX_OUT;\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\tS_PIX_OUT:begin // \\\\n\\\\t\\\\t\\\\t\\\\tcnt<=cnt+1'b1;\\\\n\\\\t\\\\t\\\\t\\\\tif (cnt==`PIX_IN_ROW_CLK)\\\\n\\\\t\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tcnt<=16'b0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tstate<=S_ROW_DOWN2;\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\tS_ROW_DOWN2:begin // \\\\n\\\\t\\\\t\\\\t\\\\tcnt<=cnt+1'b1;\\\\n\\\\t\\\\t\\\\t\\\\tif (cnt==PAUSE-2)\\\\n\\\\t\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tcnt<=16'b0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tstate<=S_CHANGE_BUF;\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\tS_CHANGE_BUF:begin // \\\\n\\\\t\\\\t\\\\t\\\\tBUFER_CHANGE<=!BUFER_CHANGE;\\\\n\\\\t\\\\t\\\\t\\\\tstate<=S_MEM_UP;\\\\n\\\\t\\\\t\\\\t\\\\tcnt_row<=cnt_row+1'b1;\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\tS_MEM_UP:begin // \\\\n\\\\t\\\\t\\\\t\\\\tif(cnt_row<=`ROW_IN_FRAME) state<=S_ROW_UP;\\\\n\\\\t\\\\t\\\\t\\\\telse state<=S_IDLE;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\tdefault:state<=S_IDLE;\\\\n\\\\t\\\\t\\\\t\\\\n\\\\t\\\\tendcase\\\\t\\\\n\\\\tend\\\\nend\\\\n\\\\nalways @(posedge CLK_6_6)\\\\nbegin\\\\n\\\\tdalay_shift <= {dalay_shift[14:0], datavalid_mem};\\\\nend\\\\n\\\\nassign BUF_IN_EN=dalay_shift[`DELAY_DATAVALID];\\\\n\\\\n\\\\nendmodule"]
['module part4(\\\\n input clk,\\\\n input rst,\\\\n input ld,\\\\n input [20:0] instruction ,\\\\n output [7:0] out\\\\n );\\\\n\\\\nwire [7:0]dst;\\\\nwire [7:0] immediate; wire [7:0]src1; wire [7:0]src2; wire [2:0] op; wire z;\\\\nwire [7:0] regOut_0,regOut_1, regOut_2, regOut_3, regOut_4, regOut_5, regOut_6;\\\\n\\\\nassign dst[0]=instruction[0];\\\\nassign dst[1]=instruction[1];\\\\nassign dst[2]=instruction[2];\\\\n\\\\nassign src2[0]=instruction[3];\\\\nassign src2[1]=instruction[4];\\\\nassign src2[2]=instruction[5];\\\\n\\\\nassign src1[0]=instruction[6];\\\\nassign src1[1]=instruction[7];\\\\nassign src1[2]=instruction[8];\\\\n\\\\nassign immediate[0]=instruction[9];\\\\nassign immediate[1]=instruction[10];\\\\nassign immediate[2]=instruction[11];\\\\nassign immediate[3]=instruction[12];\\\\nassign immediate[4]=instruction[13];\\\\nassign immediate[5]=instruction[14];\\\\nassign immediate[6]=instruction[15];\\\\nassign immediate[7]=instruction[16];\\\\n\\\\nassign op[0]=instruction[17];\\\\nassign op[1]=instruction[18];\\\\nassign op[2]=instruction[19];\\\\n\\\\nassign z=instruction[20];\\\\nwire en,zero;\\\\nassign en=~(z&zero);\\\\n\\\\npart2 regfile(dst,ld,clk,rst,out,regOut_0, regOut_1, regOut_2, regOut_3, regOut_4, regOut_5, regOut_6);\\\\n\\\\nwire [7:0] mux1out;\\\\nmux m1(regOut_6,regOut_5,regOut_4,regOut_3,regOut_2,regOut_1,regOut_0,immediate,src1,mux1out);\\\\nwire [7:0] mux2out;\\\\nmux m2(regOut_6,regOut_5,regOut_4,regOut_3,regOut_2,regOut_1,regOut_0,immediate,src2,mux2out);\\\\n\\\\npart3 alu(mux1out,mux2out,en,op,zero,out);\\\\nendmodule']
["module alu(input reset, input clk, output reg [3:0] real_part, output reg [3:0] imaginary_part, output ready);\\\\n\\\\t// first stage\\\\n\\\\treg [4:0] PC;\\\\n\\\\twire [17:0] instruction;\\\\n\\\\treg [17:0] instruction_in_register;\\\\n\\\\twire wait_all;\\\\n\\\\twire wait_mult;\\\\n\\\\twire wait_add;\\\\n\\\\tassign wait_all = wait_mult || wait_add;\\\\n\\\\tmemory mem(PC, instruction);\\\\n\\\\talways @(posedge clk)\\\\n\\\\tbegin\\\\n\\\\t\\\\tif (reset) PC <= 0;\\\\n\\\\t\\\\telse\\\\n\\\\t\\\\t\\\\tif (!wait_all)\\\\n\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\tinstruction_in_register <= instruction;\\\\n\\\\t\\\\t\\\\t\\\\tPC <= PC + 1'b1;\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\tend\\\\n\\\\t// second stage\\\\n\\\\twire [3:0] multiplier_first_operand;\\\\n\\\\twire [3:0] multiplier_second_operand;\\\\n\\\\twire [3:0] multiplier_output;\\\\n\\\\treg [1:0] stage2_counter;\\\\n\\\\treg stage2_ready;\\\\n\\\\treg [3:0] stage2_first, stage2_second, stage2_third, stage2_forth;\\\\n\\\\treg [1:0] stage2_opcode;\\\\n\\\\treg [3:0] first, second, third;\\\\n\\\\tmultiplier multiplier_unit(multiplier_first_operand, multiplier_second_operand, multiplier_output);\\\\n\\\\tassign multiplier_first_operand = (stage2_counter == 0) ? instruction_in_register[15:12]: (stage2_counter == 1) ? instruction_in_register[11:8]: (stage2_counter == 2) ? instruction_in_register[11:8]: instruction_in_register[15:12];\\\\n\\\\tassign multiplier_second_operand = (stage2_counter == 0) ? instruction_in_register[7:4]: (stage2_counter == 1) ? instruction_in_register[7:4]: (stage2_counter == 2) ? instruction_in_register[3:0]: instruction_in_register[3:0];\\\\n\\\\tassign wait_mult = !stage2_ready;\\\\n\\\\talways @(posedge clk)\\\\n\\\\tbegin\\\\n\\\\t\\\\tif (reset || !wait_all)\\\\n\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\tstage2_counter <= 0;\\\\n\\\\t\\\\t\\\\tstage2_ready <= 0;\\\\n\\\\t\\\\tend\\\\n\\\\t\\\\tif (stage2_ready == 0)\\\\n\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\tif (instruction_in_register[17] == 0) // it is add or sub\\\\n\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\tif (!wait_add)\\\\n\\\\t\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tstage2_opcode <= instruction_in_register[17:16];\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tstage2_first <= instruction_in_register[15:12];\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tstage2_second <= instruction_in_register[11:8];\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tstage2_third <= instruction_in_register[7:4];\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tstage2_forth <= instruction_in_register[3:0];\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tstage2_counter <= 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tstage2_ready <= 1;\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\telse // it is mult\\\\n\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\tif (stage2_counter == 0)\\\\n\\\\t\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tfirst <= multiplier_output;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tstage2_counter <= stage2_counter + 1'b1;\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t\\\\tif (stage2_counter == 1)\\\\n\\\\t\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tsecond <= multiplier_output;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tstage2_counter <= stage2_counter + 1'b1;\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t\\\\tif (stage2_counter == 2)\\\\n\\\\t\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tthird <= multiplier_output;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tstage2_counter <= stage2_counter + 1'b1;\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t\\\\tif (stage2_counter == 3)\\\\n\\\\t\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tstage2_first <= first;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tstage2_second <= second;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tstage2_third <= third;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tstage2_forth <= multiplier_output;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tstage2_opcode <= instruction_in_register[17:16];\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tstage2_counter <= stage2_counter + 1'b1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tstage2_ready <= 1;\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\tend\\\\n\\\\tend\\\\n\\\\t// third stage\\\\n\\\\twire [3:0] adder_first_operand;\\\\n\\\\twire [3:0] adder_second_operand;\\\\n\\\\twire add_diff_not;\\\\n\\\\twire [3:0] adder_out;\\\\n\\\\treg stage3_counter;\\\\n\\\\treg stage3_ready;\\\\n\\\\treg [3:0] stage3_first;\\\\n\\\\tadder adder_unit(add_diff_not, adder_first_operand, adder_second_operand, adder_out);\\\\n\\\\tassign adder_first_operand = (stage3_counter == 0) ? stage2_first : stage2_second;\\\\n\\\\tassign adder_second_operand = (stage3_counter == 0) ? stage2_third : stage2_forth;\\\\n\\\\tassign add_diff_not = stage2_opcode[0] || stage2_opcode[1] && stage3_counter;\\\\n\\\\tassign wait_add = !stage3_ready && (stage3_counter != 1);\\\\n\\\\tassign ready = stage3_ready;\\\\n\\\\talways @(posedge clk)\\\\n\\\\tbegin\\\\n\\\\t\\\\tif (reset || !wait_all)\\\\n\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\tstage3_counter <= 0;\\\\n\\\\t\\\\t\\\\tstage3_ready <= 0;\\\\n\\\\t\\\\tend\\\\n\\\\t\\\\tif (stage3_ready == 0)\\\\n\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\tif (stage3_counter == 0)\\\\n\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\tstage3_first <= adder_out;\\\\n\\\\t\\\\t\\\\t\\\\tstage3_counter <= stage3_counter + 1'b1;\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\tif (stage3_counter == 1)\\\\n\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\treal_part <= stage3_first;\\\\n\\\\t\\\\t\\\\t\\\\timaginary_part <= adder_out;\\\\n\\\\t\\\\t\\\\t\\\\tstage3_counter <= stage3_counter + 1'b1;\\\\n\\\\t\\\\t\\\\t\\\\tstage3_ready <= 1;\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\tend\\\\n\\\\tend\\\\nendmodule"]
["module test_processor();\\\\n reg clk;\\\\n reg reset;\\\\n wire [63:0] PC_In; //prev inst add\\\\n wire [63:0] PC_Out; //new ins add\\\\n wire [31:0] instruction; //ins\\\\n wire [6:0] opcode; //opcode\\\\n wire [4:0] rs1;\\\\n wire [4:0] rs2;\\\\n wire [4:0] rd;\\\\n wire [63:0] WriteData; //in rd\\\\n wire [63:0] ReadData1;\\\\n wire [63:0] ReadData2; //writedata (mem)\\\\n wire Branch, MemWrite, MemRead, MemtoReg;\\\\n wire [1:0] ALUOp;\\\\n wire ALUSrc, RegWrite;\\\\n wire [63:0] Result; //Mem_Add\\\\n wire [63:0] read_mem_data;\\\\n wire [63:0] imm;\\\\n wire [3:0] operation;\\\\n wire Zero;\\\\n wire [63:0] ALU_input2;\\\\n wire [63:0] branch;\\\\n wire [63:0] immi;\\\\n\\\\nRISC_V_Processor r1(clk, reset, PC_In, PC_Out, instruction, opcode, rs1, rs2, rd, WriteData, ReadData1,ReadData2, Branch, MemWrite, MemRead, MemtoReg, ALUOp, ALUSrc, RegWrite, Result, read_mem_data,imm,operation,Zero, ALU_input2,branch,immi);\\\\n\\\\ninitial begin\\\\n\\\\nclk = 1'b0; \\\\nreset = 1'b1;\\\\n// #20 reset = 1'b1;\\\\n// #20 reset = 1'b0;\\\\n// #100 reset = 1'b1;\\\\n#20 reset = 1'b0;\\\\n\\\\nend\\\\n always\\\\n #10 clk = ~clk;\\\\nendmodule"]
["module alu(\\\\n\\\\tinput [4:0] ops,\\\\n\\\\tinput [31:0] A, B,\\\\n\\\\toutput reg [63:0] Zregin\\\\n);\\\\n\\\\n//reg [63:0] x;\\\\n\\\\nwire [31:0] addresult, andresult, orresult, notresult, negresult, rorresult, rolresult, shlresult, shrresult, shraresult, subresult;\\\\n\\\\nwire [63:0] mulresult, divresult;\\\\n\\\\n\\\\n\\\\nADD ADD(A, B, addresult);\\\\nAND_mod AND_mod(A, B, andresult);\\\\nOR_mod OR_mod(A, B, orresult);\\\\nNOT_mod NOT_mod(A, notresult);\\\\nNEG NEG(A, negresult);\\\\nMUL MUL(A, B, mulresult);\\\\nROR ROR(A, B, rorresult);\\\\nROL ROL(A, B, rolresult);\\\\nSHL SHL(A, B, shlresult);\\\\nSHR SHR(A, B, shrresult);\\\\nSHRA SHRA(A, B, shraresult);\\\\nSUB SUB(A, B, subresult);\\\\nDIV DIV(A, B, divresult);\\\\n\\\\n//... continue this\\\\n\\\\n//NEED TO IMPLEMENT AND, OR, SUB, MUL, DIV, SHR, SHRA, SHL, ROR, ROL, NEG, NOT\\\\n\\\\n//addresult or andresult or orresult or notresult or negresult or rorresult or rolresult or shlresult or shrresult or shraresult or mulresult\\\\n\\\\nalways @(*) begin\\\\n\\\\tcase(ops)\\\\n\\\\t\\\\t5'b00011: Zregin = addresult;\\\\n\\\\t\\\\t5'b01010: Zregin = andresult; \\\\n\\\\t\\\\t5'b01011: Zregin = orresult;\\\\n\\\\t\\\\t5'b10010: Zregin = notresult;\\\\n\\\\t\\\\t5'b10001: Zregin = negresult;\\\\n\\\\t\\\\t5'b01111: Zregin = mulresult;\\\\n\\\\t\\\\t5'b01000: Zregin = rorresult;\\\\n\\\\t\\\\t5'b01001: Zregin = rolresult;\\\\n\\\\t\\\\t5'b00111: Zregin = shlresult;\\\\n\\\\t\\\\t5'b00101: Zregin = shrresult;\\\\n\\\\t\\\\t5'b00110: Zregin = shraresult;\\\\n\\\\t\\\\t5'b10000: Zregin = divresult;\\\\n\\\\t\\\\t5'b00100: Zregin = subresult;\\\\n\\\\t //store\\\\n\\\\t\\\\t//5'b10011: //branch\\\\n\\\\t\\\\t//5'b10100: //jr\\\\n\\\\t\\\\t//5'b10101: //jal\\\\n\\\\t\\\\t//5'b11000: //mfhi\\\\n\\\\t\\\\t//5'b11001: //mflo\\\\n\\\\t\\\\t//5'b10110: //input\\\\n\\\\t\\\\t//5'b10111: //output\\\\n\\\\n\\\\nendcase\\\\nend\\\\n\\\\n\\\\n\\\\nendmodule"]
['module m2(output wire Y, input wire d0,d1,s);\\\\n \\\\n assign Y=s ? d1: d0;\\\\n\\\\nendmodule', 'module m4(output wire Y, input wire d0,d1,d2,d3,s0,s1);\\\\n \\\\n wire p0, p1;\\\\n \\\\n m2 x0(d0,d1,s0,p1);\\\\n m2 x1(d2,d3,s1,p2);\\\\n m2 x2(p0,p1,s1,Y);\\\\n\\\\nendmodule', 'module m8(output wire y2, input wire d0,d1,d2,d3,d4,d5,d6,d7,s0,s1,s2);\\\\n \\\\n wire p2, p3;\\\\n \\\\n m4 x3(d0,d1,d2,d3,s0,s1,p1);\\\\n m4 x4(d4,d5,d6,d7,s0,s1,p2);\\\\n m2 x5(p2,p3,s2,y2);\\\\nendmodule', 'module t1m2(input wire A, B, C, output wire Y);\\\\n\\\\n\\\\tassign Y= A ?(B~^C): (B^C);\\\\n\\\\t\\\\nendmodule', 'module t1m4(input wire A, B, C, output wire Y);\\\\n\\\\n\\\\tassign Y= A ? B ?\\\\n\\\\t(C, ~C, ~C, C, A, B, Y);\\\\n\\\\t\\\\nendmodule', 'module t1m8(input wire A, B, C, output wire Y);\\\\n\\\\n\\\\twire E, S;\\\\n\\\\tassign E = 1;\\\\n\\\\tassign S = 0;\\\\n\\\\tm8 J3(Sal, E, E, S, ENT, SAL, SAL, ENT, A, B, C, Y);\\\\n\\\\t\\\\nendmodule', 'module t2m2(input wire A, B, C, output wire Y);\\\\n\\\\t\\\\n\\\\tm2 U1(~(B|C), ~(B&C), A, Y);\\\\n\\\\t\\\\nendmodule', 'module t2m4(input wire A, B, C, output wire Y);\\\\n\\\\n\\\\tm4 U2(~C, ~C&C, ~C|C, ~C, A, B, Y);\\\\n\\\\t\\\\nendmodule', 'module t2m8(input wire A, B, C, output wire Y);\\\\n\\\\n\\\\twire E, S;\\\\n\\\\tassign E = 1;\\\\n\\\\tassign S = 0;\\\\n\\\\tm8 U3(E, S, S, S, E, E, E, S, A, B, C, Y);\\\\n\\\\t\\\\nendmodule']
['module Learning_Mode_Top(Clk,Rst,B_Inp,Switch,Seg_Alphabet_Out);\\\\n\\\\ninput Clk,Rst;\\\\ninput B_Inp; //B_In,\\\\ninput[5:0] Switch;\\\\n\\\\noutput[6:0] Seg_Alphabet_Out; \\\\n\\\\nwire enable;\\\\nwire B_Out; //,Pulse,B_Out;\\\\nwire [3:0] Alphabet;//,Counter_Out,RAG_Out,Count;\\\\nwire [5:0] SwitchOut;\\\\n//Seg_RAG_Out,\\\\n\\\\n//LFSR_RAG L2(Rst,Clk, q,RAG_Out,B_In,B_Out,Seg_RAG_Out); //Random Alphabet Displayed on 7-Segment Display When button is pushed\\\\n\\\\n//Learning_Mode L(Rst,Clk,RAG_Out,B_In,B_Out,Seg_RAG_Out,Count);\\\\n\\\\nButton_Shaper B1(B_Inp,B_Out,Clk,Rst);\\\\nload6b Lo (Switch, SwitchOut,B_Out,Clk,Rst, enable);//SwitchOut=Switch Value when load button pressed\\\\nSwitch2Alphabet SA(Alphabet,SwitchOut);//To convert SwitchOut from 6 bit to 4 bit to match 4 bit value of Alphabet\\\\n\\\\n//Compare Cmp(RAG_Out,Alphabet,Clk,Rst,Pulse);\\\\n//Counter Cntr(Rst,Clk,Pulse,Counter_Out);\\\\nSeven_Seg_Decoder S2(Alphabet,Seg_Alphabet_Out,enable);\\\\n\\\\nendmodule']
["module DataMemory(clk, wrtEn, addr, dIn, sw, key, ledr, ledg, hex, dOut);\\\\n\\\\tparameter MEM_INIT_FILE;\\\\n\\\\tparameter ADDR_BIT_WIDTH = 32;\\\\n\\\\tparameter DATA_BIT_WIDTH = 32;\\\\n\\\\tparameter TRUE_ADDR_BIT_WIDTH = 11;\\\\n\\\\tparameter N_WORDS = (1 << TRUE_ADDR_BIT_WIDTH);\\\\n\\\\t\\\\n\\\\tinput clk, wrtEn;\\\\n\\\\tinput [3:0] key;\\\\n\\\\tinput [9:0] sw;\\\\n\\\\tinput [ADDR_BIT_WIDTH - 1 : 0] addr;\\\\n\\\\tinput [DATA_BIT_WIDTH - 1 : 0] dIn;\\\\n\\\\toutput [DATA_BIT_WIDTH - 1 : 0] dOut;\\\\n\\\\toutput reg [9:0] ledr;\\\\t\\\\n\\\\toutput reg [7:0] ledg;\\\\n\\\\toutput reg [15:0] hex;\\\\n \\\\n\\\\t(* ram_init_file = MEM_INIT_FILE *)\\\\n\\\\treg [DATA_BIT_WIDTH - 1 : 0] data [0 : N_WORDS - 1];\\\\n\\\\treg [TRUE_ADDR_BIT_WIDTH - 1 :0] addr_reg;\\\\n\\\\treg [DATA_BIT_WIDTH - 1 : 0] sw_reg;\\\\n\\\\treg [DATA_BIT_WIDTH - 1 : 0] key_reg;\\\\n\\\\n\\\\talways @(posedge clk) begin\\\\n\\\\t\\\\tif (addr[29]) begin\\\\n\\\\t\\\\t\\\\tif (wrtEn) begin\\\\n\\\\t \\\\t\\\\t\\\\tif (addr[2]) ledr <= dIn[9:0];\\\\n\\\\t\\\\t\\\\t\\\\telse if (addr[3]) ledg <= dIn[7:0];\\\\n\\\\t\\\\t\\\\t\\\\telse hex <= dIn[15:0];\\\\n\\\\t \\\\tend else begin\\\\n\\\\t \\\\t\\\\tif (addr[2]) sw_reg <= sw;\\\\n\\\\t \\\\t\\\\telse key_reg <= (~key & 4'hf);\\\\n\\\\t \\\\tend\\\\n \\\\tend\\\\n end\\\\n\\\\n\\\\talways @(negedge clk) begin\\\\n\\\\t\\\\tif (wrtEn && !addr[29]) data[addr[13:2]] <= dIn;\\\\t\\\\n\\\\t\\\\taddr_reg <= addr[13:2];\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\n\\\\tend\\\\n\\\\n\\\\tassign dOut = addr[29] ? (addr[2] ? sw_reg : key_reg) : data[addr_reg];\\\\nendmodule"]
['module bit4_AdderSub(sum,cout,a,b,cin);\\\\ninput [3:0] a,b;\\\\ninput cin;\\\\noutput [3:0] sum;\\\\noutput cout;\\\\nwire [7:0]w,c;\\\\nxor(w[0],b[0],cin);\\\\nxor(w[1],b[1],cin);\\\\nxor(w[2],b[2],cin);\\\\nxor(w[3],b[3],cin);\\\\n Full_Adder f1(sum[0],c[0], a[0],w[0], cin);\\\\n Full_Adder f2(sum[1], c[1], a[1],w[1], c[0]);\\\\n Full_Adder f3(sum[2], c[2], a[2],w[2], c[1]);\\\\n Full_Adder f4(sum[3], cout, a[3],w[3], c[2]);\\\\n\\\\nendmodule', "module TB_bit4_AdderSub;\\\\nreg [3:0] a,b;\\\\nreg cin;\\\\nwire [3:0] sum;\\\\nwire cout;\\\\n\\\\nbit4_AdderSub as(sum,cout,a,b,cin);\\\\n\\\\ninitial\\\\n\\\\nbegin\\\\na=4'b1000; b=4'b0010; cin=1;\\\\n#100 a=4'b1010; b=4'b0010; cin=1;\\\\n#100 a=4'b0010; b=4'b1000; cin=1;\\\\n#100 a=4'b1000; b=4'b1000; cin=1;\\\\n#100 a=4'b0001; b=4'b0111; cin=1;\\\\nend\\\\nendmodule"]
['module one_approx_eight_bit_wallace_tree_top(\\\\n\\\\tinput clk,\\\\n\\\\tinput [7:0] A_in, B_in,\\\\n\\\\toutput reg [15:0] S_out\\\\n);\\\\n\\\\nreg [7:0] A, B;\\\\nwire [15:0] S;\\\\n\\\\nalways @( posedge clk ) begin\\\\n\\\\tA = A_in;\\\\n\\\\tB = B_in;\\\\n\\\\tS_out = S;\\\\nend\\\\n\\\\nwire [12:0] L_12;\\\\nwire [10:0] L_23;\\\\nwire [8:0] L_34;\\\\nwire [6:0] L_45;\\\\nwire [4:0] L_56;\\\\nwire [2:0] L_67;\\\\n\\\\none_approx_eight_bit_wallace_tree_reduc_layer_1 L1 (\\\\n\\\\t.A(A),\\\\n\\\\t.B(B),\\\\n\\\\t.w16385_in_L2(L_12[12]),\\\\n\\\\n\\\\t.w1_o(S[0]),\\\\n\\\\t.w2_o(S[1]),\\\\n\\\\t.w16385_o(S[14]),\\\\n\\\\t.w32768_o(S[15]),\\\\n\\\\n\\\\t.w4_o(L_12[0]),\\\\n\\\\t.w8_o(L_12[1]),\\\\n\\\\t.w16_o(L_12[2]),\\\\n\\\\t.w32_o(L_12[3]),\\\\n\\\\t.w64_o(L_12[4]),\\\\n\\\\t.w128_o(L_12[5]),\\\\n\\\\t.w256_o(L_12[6]),\\\\n\\\\t.w512_o(L_12[7]),\\\\n\\\\t.w1024_o(L_12[8]),\\\\n\\\\t.w2048_o(L_12[9]),\\\\n\\\\t.w4096_o(L_12[10]),\\\\n\\\\t.w8192_o(L_12[11])\\\\n);\\\\n\\\\n\\\\neight_bit_wallace_tree_reduc_layer_2 L2 (\\\\n\\\\t.A(A[5:0]),\\\\n\\\\t.B(B[7:2]),\\\\n\\\\t.w8192_in_L3(L_23[10]),\\\\n\\\\n\\\\t.w4_in(L_12[0]),\\\\n\\\\t.w8_in(L_12[1]),\\\\n\\\\t.w16_in(L_12[2]),\\\\n\\\\t.w32_in(L_12[3]),\\\\n\\\\t.w64_in(L_12[4]),\\\\n\\\\t.w128_in(L_12[5]),\\\\n\\\\t.w256_in(L_12[6]),\\\\n\\\\t.w512_in(L_12[7]),\\\\n\\\\t.w1024_in(L_12[8]),\\\\n\\\\t.w2048_in(L_12[9]),\\\\n\\\\t.w4096_in(L_12[10]),\\\\n\\\\t.w8192_in(L_12[11]),\\\\n\\\\n\\\\t.w4_o(S[2]),\\\\n\\\\t.w8192_o(S[13]),\\\\n\\\\t.w16385_o_L1(L_12[12]),\\\\n\\\\n\\\\t.w8_o(L_23[0]),\\\\n\\\\t.w16_o(L_23[1]),\\\\n\\\\t.w32_o(L_23[2]),\\\\n\\\\t.w64_o(L_23[3]),\\\\n\\\\t.w128_o(L_23[4]),\\\\n\\\\t.w256_o(L_23[5]),\\\\n\\\\t.w512_o(L_23[6]),\\\\n\\\\t.w1024_o(L_23[7]),\\\\n\\\\t.w2048_o(L_23[8]),\\\\n\\\\t.w4096_o(L_23[9])\\\\n);\\\\n\\\\neight_bit_wallace_tree_reduc_layer_3 L3 (\\\\n\\\\t.A(A[4:0]),\\\\n\\\\t.B(B[7:3]),\\\\n\\\\t.w4096_in_L4(L_34[8]),\\\\n\\\\n\\\\t.w8_in(L_23[0]),\\\\n\\\\t.w16_in(L_23[1]),\\\\n\\\\t.w32_in(L_23[2]),\\\\n\\\\t.w64_in(L_23[3]),\\\\n\\\\t.w128_in(L_23[4]),\\\\n\\\\t.w256_in(L_23[5]),\\\\n\\\\t.w512_in(L_23[6]),\\\\n\\\\t.w1024_in(L_23[7]),\\\\n\\\\t.w2048_in(L_23[8]),\\\\n\\\\t.w4096_in(L_23[9]),\\\\n\\\\n\\\\n\\\\t.w8_o(S[3]),\\\\n\\\\t.w4096_o(S[12]),\\\\n\\\\t.w8192_o_L2(L_23[10]),\\\\n\\\\n\\\\n\\\\t.w16_o(L_34[0]),\\\\n\\\\t.w32_o(L_34[1]),\\\\n\\\\t.w64_o(L_34[2]),\\\\n\\\\t.w128_o(L_34[3]),\\\\n\\\\t.w256_o(L_34[4]),\\\\n\\\\t.w512_o(L_34[5]),\\\\n\\\\t.w1024_o(L_34[6]),\\\\n\\\\t.w2048_o(L_34[7])\\\\n);\\\\n\\\\neight_bit_wallace_tree_reduc_layer_4 L4 (\\\\n\\\\t.A(A[3:0]),\\\\n\\\\t.B(B[7:4]),\\\\n\\\\t.w2048_in_L5(L_45[6]),\\\\n\\\\n\\\\t.w16_in(L_34[0]),\\\\n\\\\t.w32_in(L_34[1]),\\\\n\\\\t.w64_in(L_34[2]),\\\\n\\\\t.w128_in(L_34[3]),\\\\n\\\\t.w256_in(L_34[4]),\\\\n\\\\t.w512_in(L_34[5]),\\\\n\\\\t.w1024_in(L_34[6]),\\\\n\\\\t.w2048_in(L_34[7]),\\\\n\\\\n\\\\n\\\\t.w16_o(S[4]),\\\\n\\\\t.w2048_o(S[11]),\\\\n\\\\t.w4096_o_L3(L_34[8]),\\\\n\\\\n\\\\n\\\\t.w32_o(L_45[0]),\\\\n\\\\t.w64_o(L_45[1]),\\\\n\\\\t.w128_o(L_45[2]),\\\\n\\\\t.w256_o(L_45[3]),\\\\n\\\\t.w512_o(L_45[4]),\\\\n\\\\t.w1024_o(L_45[5])\\\\n);\\\\n\\\\neight_bit_wallace_tree_reduc_layer_5 L5 (\\\\n\\\\t.A(A[2:0]),\\\\n\\\\t.B(B[7:5]),\\\\n\\\\t.w1024_in_L6(L_56[4]),\\\\n\\\\n\\\\t.w32_in(L_45[0]),\\\\n\\\\t.w64_in(L_45[1]),\\\\n\\\\t.w128_in(L_45[2]),\\\\n\\\\t.w256_in(L_45[3]),\\\\n\\\\t.w512_in(L_45[4]),\\\\n\\\\t.w1024_in(L_45[5]),\\\\n\\\\n\\\\n\\\\t.w32_o(S[5]),\\\\n\\\\t.w1024_o(S[10]),\\\\n\\\\t.w2048_o_L4(L_45[6]),\\\\n\\\\n\\\\n\\\\t.w64_o(L_56[0]),\\\\n\\\\t.w128_o(L_56[1]),\\\\n\\\\t.w256_o(L_56[2]),\\\\n\\\\t.w512_o(L_56[3])\\\\n);\\\\n\\\\neight_bit_wallace_tree_reduc_layer_6 L6 (\\\\n\\\\t.A(A[1:0]),\\\\n\\\\t.B(B[7:6]),\\\\n\\\\t.w512_in_L7(L_67[2]),\\\\n\\\\n\\\\t.w64_in(L_56[0]),\\\\n\\\\t.w128_in(L_56[1]),\\\\n\\\\t.w256_in(L_56[2]),\\\\n\\\\t.w512_in(L_56[3]),\\\\n\\\\n\\\\n\\\\t.w64_o(S[6]),\\\\n\\\\t.w512_o(S[9]),\\\\n\\\\t.w1024_o_L5(L_56[4]),\\\\n\\\\n\\\\n\\\\t.w128_o(L_67[0]),\\\\n\\\\t.w256_o(L_67[1])\\\\n);\\\\n\\\\neight_bit_wallace_tree_reduc_layer_7 L7 (\\\\n\\\\t.A(A[0]),\\\\n\\\\t.B(B[7]),\\\\n\\\\n\\\\t.w128_in(L_67[0]),\\\\n\\\\t.w256_in(L_67[1]),\\\\n\\\\n\\\\n\\\\t.w128_o(S[7]),\\\\n\\\\t.w256_o(S[8]),\\\\n\\\\t.w512_o_L6(L_67[2])\\\\n);\\\\n\\\\nendmodule']
['module rightshiftb (input [31:0]a, input [4:0]b, input aorl, output [31:0]out);\\\\n//only b[4:0] are actually used, documentation states that only lowest 5 bits of reg or imm value are used\\\\n\\\\nwire [31:0]out1;\\\\nwire [31:0]out2;\\\\nwire [31:0]out4;\\\\nwire [31:0]out8;\\\\nwire [31:0]out16;\\\\nwire [31:0]out1m;\\\\nwire [31:0]out2m;\\\\nwire [31:0]out4m;\\\\nwire [31:0]out8m;\\\\nwire [4:0]shift;\\\\ngenvar i;\\\\n\\\\nfor (i = 0; i < 5; i = i + 1) begin\\\\n assign shift[i] = b[i] ^ aorl;\\\\nend\\\\n\\\\nrightshiftn u1 ( .a (a), .aorl (aorl), .out (out1));\\\\nmux m1 (.b (a), .a (out1), .ctrl (shift[0]), .out(out1m));\\\\n\\\\nrightshiftn #(2) u2 ( .a (out1m), .aorl (aorl), .out (out2));\\\\nmux m2 (.b (out1m), .a (out2), .ctrl (shift[1]), .out(out2m));\\\\n\\\\nrightshiftn #(4) u4 ( .a (out2m), .aorl (aorl), .out (out4));\\\\nmux m4 (.b (out2m), .a (out4), .ctrl (shift[2]), .out(out4m));\\\\n\\\\nrightshiftn #(8) u8 ( .a (out4m), .aorl (aorl), .out (out8));\\\\nmux m8 (.b (out4m), .a (out8), .ctrl (shift[3]), .out(out8m));\\\\n\\\\nrightshiftn #(16) u16 ( .a (out8m), .aorl (aorl), .out (out16));\\\\nmux m16 (.b (out8m), .a (out16), .ctrl (shift[4]), .out(out));\\\\n\\\\n\\\\nendmodule']
["module Multiplier16x16 (\\\\n\\\\tinput [15:0] A , // input [unsigned 16 bits]\\\\n\\\\tinput [15:0] B , // input [unsigned 16 bits]\\\\n\\\\toutput [31:0] P // output [unsigned 32 bits]\\\\n);\\\\n\\\\n\\\\t/* write your code here */\\\\n\\\\t\\\\n\\\\twire [15:0] out [0:3], qw;\\\\n\\\\twire [31:0] outp[1:0];\\\\t\\\\t\\\\n\\\\t\\\\n\\\\tMultiplier8x8 M_0(A[7:0], B[7:0], out[0]),\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t M_1(A[15:8], B[15:8], out[1]),\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t M_2(A[15:8], B[7:0], out[2]),\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t M_3(A[7:0], B[15:8], out[3]);\\\\n\\\\t\\\\t\\\\t\\\\n\\\\t\\\\n\\\\tAdderSubtractor32x32 A_0({16'b0 ,out[0]}, {out[1], 16'b0}, 1'b0, outp[0]),\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tA_1({8'b0, out[2], 8'b0}, {8'b0 ,out[3], 8'b0}, 1'b0, outp[1]),\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tA_2(outp[0], outp[1], 1'b0, P);\\\\n\\\\t\\\\n\\\\t/* write your code here */\\\\n\\\\nendmodule"]
['module top_level(f1,f2,p,in_1,in_2,out,clk,clk2);\\\\ninput [7:0]in_1, in_2;\\\\ninput clk;\\\\ninput clk2;\\\\ninput [15:0]p; //bias\\\\ninput [15:0]f1,f2; //weight for every two numbers\\\\noutput [15:0]out;\\\\n\\\\nwire [15:0]a,b;\\\\nwire [15:0]r1,r2,r3,r4,r5;\\\\n\\\\nconvert inst_1(.float(a), .int8(in_1), .clk(clk)); //parallel int to float16\\\\nconvert inst_2(.float(b), .int8(in_2), .clk(clk));\\\\nmult inst_3(.B(f1), .C(r1), .A(a), .clk(clk)); //parallel multi, .B(f) is the weight, .A(a) is the float16 .C is the multiply result\\\\nmult inst_4(.B(f2), .C(r2), .A(b), .clk(clk));\\\\nmain_adder inst_5 (.AA(r1), .BB(r2),.clk(clk), .R_add(r3));// sum of first two multi\\\\nmux inst_6(.in1(r4), .in2(p), .sel(clk2), .out(r5)); //p at port 1, r4 at port 0\\\\nmain_adder inst_7 (.AA(r3), .BB(r5),.clk(clk), .R_add(r4)); //the first value is intermediate data, should only keep the second one (for each 2*2 block)\\\\n//a mux can be added after inst_7, so the output can alway be the needed one..might add it later.\\\\nassign out=r4;\\\\n\\\\n\\\\n\\\\n\\\\nendmodule']
["module FFT_block(\\\\n clk, rst_n,\\\\n \\\\n // buffer interface\\\\n data_i,\\\\n address_o,\\\\n \\\\n // control signals\\\\n start_i\\\\n //end_o, per ora non serve\\\\n);\\\\n\\\\n// Parameters\\\\n//localparam SAMPLE_WIDTH = 16;\\\\n//localparam SAMPLE_NUM\\\\t= 1024;\\\\n//localparam FFT_DEPTH = $clog2(SAMPLE_NUM);\\\\nlocalparam s0 = 3'b000, CALC_FFT = 3'b10;\\\\n\\\\n// Ports definition\\\\ninput clk;\\\\ninput rst_n;\\\\n\\\\ninput [15:0] data_i;\\\\noutput [9:0] address_o;\\\\n\\\\n//output end_o;\\\\ninput start_i;\\\\n\\\\n// Private wires\\\\nwire memsel;\\\\nwire [9:0]address_a;\\\\nwire [9:0]address_b;\\\\nwire [9:0]pipe_address_a;\\\\nwire [9:0]pipe_address_b;\\\\nwire [9:0]mem1_address_a;\\\\nwire [9:0]mem1_address_b;\\\\nwire [9:0]mem2_address_a;\\\\nwire [9:0]mem2_address_b;\\\\nwire [31:0]a_real_ram1;\\\\nwire [31:0]a_img_ram1;\\\\nwire [31:0]b_real_ram1;\\\\nwire [31:0]b_img_ram1;\\\\nwire [31:0]a_real_ram2;\\\\nwire [31:0]a_img_ram2;\\\\nwire [31:0]b_real_ram2;\\\\nwire [31:0]b_img_ram2;\\\\nwire [31:0]a_real;\\\\nwire [31:0]a_img;\\\\nwire [31:0]b_real;\\\\nwire [31:0]b_img;\\\\nwire [31:0]anext_real_bfu;\\\\nwire [31:0]anext_img_bfu;\\\\nwire [31:0]bnext_real_bfu;\\\\nwire [31:0]bnext_img_bfu;\\\\nwire [31:0]anext_real;\\\\nwire [31:0]anext_img;\\\\nwire [31:0]bnext_real;\\\\nwire [31:0]bnext_img;\\\\nwire [31:0]tw_real;\\\\nwire [31:0]tw_img;\\\\nwire [8:0]tw_addr;\\\\nwire loading;\\\\n\\\\n// Private regs\\\\n//reg i2s_get = 0;\\\\n/*reg [DAC_BITS-1:0] data_R = 0;\\\\nreg [2:0]sreg = CALC_FFT;\\\\nreg [2:0]snext;\\\\nreg [8:0]j = 9'b0; //le coppie sono met\\\\u00e0 dei campioni, quindi bastano 9 bit\\\\nreg [3:0]i = 3'b0;*/\\\\n\\\\n\\\\n// Private assignments\\\\nassign a_real = memsel ? a_real_ram2 : a_real_ram1;\\\\nassign a_img = memsel ? a_img_ram2 : a_img_ram1;\\\\nassign b_real = memsel ? b_real_ram2 : b_real_ram1;\\\\nassign b_img = memsel ? b_img_ram2 : b_img_ram1;\\\\nassign mem1_address_a = memsel ? pipe_address_a : address_a;\\\\nassign mem1_address_b = memsel ? pipe_address_b : address_b;\\\\nassign mem2_address_a = memsel ? address_a : pipe_address_a;\\\\nassign mem2_address_b = memsel ? address_b : pipe_address_b;\\\\nassign anext_real = loading ? $signed(data_i) : anext_real_bfu;\\\\nassign anext_img = loading ? 0 : anext_img_bfu;\\\\nassign bnext_real = loading ? $signed(data_i) : bnext_real_bfu;\\\\nassign bnext_img = loading ? 0 : bnext_img_bfu;\\\\n\\\\n// Private instances\\\\naddr_gen_unit fft_agu(\\\\n .clk(clk),\\\\n .rst_n(rst_n),\\\\n .address_a_o(address_a),\\\\n .address_b_o(address_b),\\\\n\\\\t .memsel_o(memsel),\\\\n\\\\t .twiddle_addr_o(tw_addr),\\\\n\\\\t .start_i(start_i), //da aggiustare\\\\n\\\\t .read_address_buffer_o(address_o),\\\\n\\\\t .loading_o(loading)\\\\n);\\\\n\\\\nbutterfly_unit bfu(\\\\n //.clk(clk), //serve?\\\\n\\\\t //input\\\\n\\\\t .twiddle_real(tw_real), \\\\n\\\\t .twiddle_img(tw_img), \\\\n\\\\t .ina_real(a_real), \\\\n\\\\t .ina_img(a_img), \\\\n\\\\t .inb_real(b_real), \\\\n\\\\t .inb_img(b_img), \\\\n\\\\t //output\\\\n\\\\t .outa_real(anext_real_bfu), \\\\n\\\\t .outa_img(anext_img_bfu), \\\\n\\\\t .outb_real(bnext_real_bfu), \\\\n\\\\t .outb_img(bnext_img_bfu)\\\\n);\\\\n\\\\ntwiddle_fact twiddle(\\\\n .clk(clk),\\\\n //.rst_n(rst_n),\\\\n .twiddle_addr(tw_addr),\\\\n .twiddle_real_out(tw_real),\\\\n .twiddle_img_out(tw_img)\\\\n);\\\\n\\\\ncmplx_ram2port ram1(\\\\n\\\\t.address_a_in(mem1_address_a),\\\\n\\\\t.address_b_in(mem1_address_b),\\\\n\\\\t.clk(clk),\\\\n\\\\t.dreal_a(anext_real),\\\\n\\\\t.dimg_a(anext_img),\\\\n\\\\t.dreal_b(bnext_real),\\\\n\\\\t.dimg_b(bnext_img),\\\\n\\\\t.wren(~memsel),\\\\n\\\\t.qreal_a(a_real_ram1),\\\\n\\\\t.qimg_a(a_img_ram1),\\\\n\\\\t.qreal_b(b_real_ram1),\\\\n\\\\t.qimg_b(b_img_ram1)\\\\n);\\\\n\\\\ncmplx_ram2port ram2(\\\\n\\\\t.address_a_in(mem2_address_a),\\\\n\\\\t.address_b_in(mem2_address_b),\\\\n\\\\t.clk(clk),\\\\n\\\\t.dreal_a(anext_real),\\\\n\\\\t.dimg_a(anext_img),\\\\n\\\\t.dreal_b(bnext_real),\\\\n\\\\t.dimg_b(bnext_img),\\\\n\\\\t.wren(memsel),\\\\n\\\\t.qreal_a(a_real_ram2),\\\\n\\\\t.qimg_a(a_img_ram2),\\\\n\\\\t.qreal_b(b_real_ram2),\\\\n\\\\t.qimg_b(b_img_ram2)\\\\n);\\\\n\\\\npipe2 add_a_pipeline(\\\\n\\\\t.in(address_a), \\\\n\\\\t.out(pipe_address_a), \\\\n\\\\t.ck(clk)\\\\n);\\\\n\\\\npipe2 add_b_pipeline(\\\\n\\\\t.in(address_b), \\\\n\\\\t.out(pipe_address_b), \\\\n\\\\t.ck(clk)\\\\n);\\\\n\\\\n\\\\nendmodule"]
["module CombinedCode(clk,rst,switch, btn1, btn2,keypad_col,keypad_row, dot_row, dot_col, seven_right, led1, led2);\\\\n\\\\ninput clk,rst;\\\\ninput switch;\\\\n//gm1:\\\\ninput btn1, btn2;\\\\ninput [3:0] keypad_col;\\\\noutput [3:0] keypad_row;\\\\noutput reg [7:0] dot_row;\\\\noutput reg [15:0] dot_col;\\\\n//output wire [6:0] seven_left;\\\\noutput wire [6:0] seven_right;\\\\noutput wire led1, led2;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\nwire [15:0]col1;\\\\nwire [7:0]col2;\\\\nwire [7:0]row1;\\\\nwire[7:0]row2;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\nHeartDisease gm1(.game_mode(switch),.clk(clk),.rst(rst),.btn1(btn1),.btn2(btn2),\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t.dot_row(row1),.dot_col(col1),.led1(led1),.led2(led2));\\\\nMoleBuster gm2(.game_mode(switch),.clk(clk),.rst(rst),.keypad_row(keypad_row),\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t.keypad_col(keypad_col),.dot_row(row2),.dot_col(col2),.score(seven_right));\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\nalways@(*) begin\\\\ncase(switch)\\\\n\\\\t1'd0:begin\\\\n\\\\t\\\\tdot_col = col1;\\\\n\\\\t\\\\tdot_row = row1;\\\\n\\\\tend\\\\n\\\\t1'd1:begin\\\\n\\\\t\\\\tdot_col = {8'd0, col2};\\\\n\\\\t\\\\tdot_row = row2;\\\\n\\\\tend\\\\nendcase\\\\nend\\\\n\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\nendmodule"]
["module Reaction_Time_Game(buttonStart, buttonHit, buttonReset, GreenLed, RedLed, Screen1, Screen2, Screen3, Screen4, Screen5, Clock, state, delayCounterDone, reg0);\\\\n input buttonStart;\\\\n input buttonHit;\\\\n input buttonReset;\\\\n input Clock;\\\\n output GreenLed;\\\\n output RedLed;\\\\n output [6:0] Screen1; // Right most screen\\\\n output [6:0] Screen2; // ...\\\\n output [6:0] Screen3; // ...\\\\n output [6:0] Screen4; // Left most screen\\\\n output [6:0] Screen5; // run counter display AKA what is at reg[0]\\\\n output [2:0] state;\\\\n output delayCounterDone;\\\\n\\\\n output wire [12:0] reg0; // is going to be the data on DATAP which in our case will always be the value stored in register 0\\\\n\\\\n wire [12:0] dataQ;\\\\n\\\\n wire [2:0] rp;\\\\n assign rp = {1'b0, 1'b0, 1'b0};\\\\n\\\\n wire [2:0] rq;\\\\n wire [12:0] ld_data;\\\\n wire registerLoad;\\\\n wire [2:0] wa;\\\\n wire SCEn;\\\\n \\\\n assign buttonStartReal = (~buttonStart);\\\\n assign buttonHitReal = (~buttonHit);\\\\n assign buttonResetReal = (~buttonReset);\\\\n\\\\n // wire delayCounterDone;\\\\n wire delayCounterEnable;\\\\n \\\\n wire OneKhzClock;\\\\n\\\\n divideByFiftyThousandCounter dbftc (.Enable(1'b1), .Clock(Clock), .ClockOut(OneKhzClock));\\\\n \\\\n elevenBitUpCount dc (.Enable(delayCounterEnable), .Clock(OneKhzClock), .Reset(delayCounterEnable), .Done(delayCounterDone));\\\\n \\\\n wire [12:0] scoreFromCounter;\\\\n\\\\n\\\\n thirteenBitUpCounter scd (.Enable(SCEn), .Clock(OneKhzClock), .count(scoreFromCounter), .Reset(~SCEn));\\\\n\\\\n regfile rf (.DATAP(reg0), .DATAQ(dataQ), .RP(rp), .RQ(rq), .WA(wa), .LD_DATA(ld_data), .WR(registerLoad), .CLK(OneKhzClock), .CLRN(buttonReset));\\\\n \\\\n \\\\n wire [2:0] tbupcntr;\\\\n wire twobitClRN;\\\\n\\\\n twoBitUpCounterREAL tb2 (.EnableReal(twobitClRN), .CLK1(buttonHitReal), .Q0(tbupcntr[0]), .Q1(tbupcntr[1]), .Q3(tbupcntr[2]), .CLRN1(twobitClRN));\\\\n\\\\n fullstate fs (.buttonStart(buttonStartReal), .buttonHit(buttonHitReal), .buttonReset(buttonReset), .Clock(OneKhzClock), .ReadQ(rq), .registerLoad(registerLoad), .delayCounterDone(delayCounterDone), .delayCounterEnable(delayCounterEnable), .WriteAddress(wa), .ledGreen(GreenLed), .RedLed(RedLed), .scoreCounterEnable(SCEn), .scoreCounter(scoreFromCounter), .registerDataP(reg0), .registerDataQ(dataQ), .registerLoadData(ld_data), .twoBitCounterClear(twobitClRN), .State(state), .twoBitCounterCurrent(tbupcntr));\\\\n \\\\n wire [12:0] outputDisplay; // TODO: change if base 10 output\\\\n wire [3:0] Screen5Pre; \\\\n \\\\n assign Screen5Pre = /*(twobitClRN) ? (tbupcntr) : */ ({reg0[3], reg0[2], reg0[1], reg0[0]});\\\\n\\\\n wire RunScoreDisplay;\\\\n assign RunScoreDisplay = 1'b1;\\\\n\\\\n wire RunCountDisplay;\\\\n assign RunCountDisplay = 1'b1;\\\\n\\\\n seven_seg_decoder_bus ssd1 (.X({dataQ[3], dataQ[2], dataQ[1], dataQ[0]}), .En(RunScoreDisplay), .Result(Screen1));\\\\n seven_seg_decoder_bus ssd2 (.X({dataQ[7], dataQ[6], dataQ[5], dataQ[4]}), .En(RunScoreDisplay), .Result(Screen2));\\\\n seven_seg_decoder_bus ssd3 (.X({dataQ[11], dataQ[10], dataQ[9], dataQ[8]}), .En(RunScoreDisplay), .Result(Screen3));\\\\n seven_seg_decoder_bus ssd4 (.X({1'b0, 1'b0, 1'b0, dataQ[12]}), .En(RunScoreDisplay), .Result(Screen4));\\\\n seven_seg_decoder_bus ssd5 (.X(Screen5Pre), .En(RunCountDisplay), .Result(Screen5));\\\\n\\\\nendmodule"]
["module digi_clock ( clk, sw, btn, seg, Led, an );\\\\n\\\\ninput clk ;\\\\ninput [7:0] sw ;\\\\ninput [3:0] btn ;\\\\n\\\\noutput [4:1] Led ;\\\\noutput [7:0]\\\\tseg;\\\\noutput [3:0]\\\\tan;\\\\n\\\\nreg [3:0]\\\\tdisphex;\\\\nreg [3:0]\\\\tsel;\\\\n\\\\nwire sw_mshm, sw_setTime, sw_ringmode, sw_ring ;\\\\nwire [3:0] sw_en ;\\\\nassign sw_setTime = sw[7] ;\\\\nassign sw_ringmode = sw[6] ;\\\\nassign sw_ring = sw[5] ;\\\\nassign sw_en = { sw[4], sw[3], sw[2], sw[1] } ;\\\\nassign sw_mshm = sw[0] ;\\\\n\\\\nwire\\\\trst, load, hp, mp ;\\\\nassign\\\\trst = ~btn[3] ;\\\\nassign\\\\tload = btn[2] ;\\\\nassign\\\\thp = btn[1] ;\\\\nassign\\\\tmp = btn[0] ;\\\\n\\\\n\\\\nwire [3:0] w_sq0;\\\\nwire [2:0] w_sq1;\\\\nwire [3:0] w_mq0;\\\\nwire [2:0] w_mq1;\\\\nwire [3:0] w_hq0;\\\\nwire [1:0] w_hq1;\\\\n\\\\n\\\\n//-------- div to 1ms/1kHz --------//\\\\nwire\\\\tclk_01;\\\\nclk_gen\\\\t#(16,50000) div_5M(\\\\n .clk\\\\t(clk),\\\\n .rst_n\\\\t(rst),\\\\n .o_clk\\\\t(clk_01)\\\\n );\\\\n \\\\n//-------- 10Hz --------//\\\\nwire\\\\tclk_10;\\\\nclk_gen\\\\t#(7,100) div_100(\\\\n .clk\\\\t(clk_01),\\\\n .rst_n\\\\t(rst),\\\\n .o_clk\\\\t(clk_10)\\\\n );\\\\n \\\\n//-------- 5Hz --------//\\\\nwire\\\\tclk_5;\\\\nclk_gen\\\\t#(1,2) div_2(\\\\n .clk\\\\t(clk_10),\\\\n .rst_n\\\\t(rst),\\\\n .o_clk\\\\t(clk_5)\\\\n );\\\\n\\\\n//-------- div to 1s/1Hz --------//\\\\nwire\\\\tclk_1;\\\\nclk_gen\\\\t#(10,1000) div_10(\\\\n .clk\\\\t(clk_01),\\\\n .rst_n\\\\t(rst),\\\\n .o_clk\\\\t(clk_1)\\\\n );\\\\n \\\\n\\\\n\\\\n\\\\n// Set Time\\\\nwire [3:0] w_setmq0;\\\\nwire [2:0] w_setmq1;\\\\nwire [3:0] w_sethq0;\\\\nwire [1:0] w_sethq1;\\\\n\\\\nSetTime setT( \\\\n .clk( clk_10 ),\\\\n .en( sw_setTime ),\\\\n\\\\t.clr( ~rst ),\\\\n .mp( mp ),\\\\n .hp( hp ),\\\\n .mq0(w_setmq0),\\\\n .mq1(w_setmq1),\\\\n .hq0(w_sethq0),\\\\n .hq1(w_sethq1)\\\\n) ;\\\\n\\\\nclock c1 (\\\\n .clk(clk_1),\\\\n .en(1), // input enable\\\\n .clr(~rst), // input clear\\\\n .load( sw_setTime & load ), // input load\\\\n .sd0(0), // input second digit 0\\\\n .sd1(0), // input second digit 1\\\\n .md0(w_setmq0), // input minute digit 0\\\\n .md1(w_setmq1), // input minute digit 1\\\\n .hd0(w_sethq0), // input hour digit 0\\\\n .hd1(w_sethq1), // input hour digit 1\\\\n .sq0(w_sq0), // output second digit 0\\\\n .sq1(w_sq1), // output second digit 1\\\\n .mq0(w_mq0), // output minute digit 0\\\\n .mq1(w_mq1), // output minute digit 1\\\\n .hq0(w_hq0), // output hour digit 0\\\\n .hq1(w_hq1) // output hour digit 1\\\\n);\\\\n\\\\n\\\\n// Alarm Clock\\\\nwire [1:0] w_sw_ouput;\\\\n\\\\nwire [3:0] w_acmq0;\\\\nwire [2:0] w_acmq1;\\\\nwire [3:0] w_achq0;\\\\nwire [1:0] w_achq1;\\\\n\\\\nAlarmClock ac ( \\\\n .clk( clk_10 ),\\\\n .sw_en( sw_en ),\\\\n\\\\t.clr( ~rst ),\\\\n .mp( mp ),\\\\n .hp( hp ),\\\\n\\\\t.sw_ouput( w_sw_ouput ),\\\\n\\\\t.mq0(w_acmq0),\\\\n .mq1(w_acmq1),\\\\n .hq0(w_achq0),\\\\n .hq1(w_achq1)\\\\n) ;\\\\n\\\\nwire w_ringing, w_ringmode ;\\\\nassign w_ringmode = sw_ringmode ? clk_5 : 1'b1 ;\\\\nassign w_ringing = ( sw_en == 4'b0000 ) && ( sw_ring & w_ringmode ) && \\\\n\\\\t\\\\t\\\\t\\\\t ( w_mq0 == w_acmq0 ) && ( w_mq1 == w_acmq1 ) && ( w_hq0 == w_achq0 ) && ( w_hq1 == w_achq1 ) ;\\\\nassign Led[1] = ( w_sw_ouput == 2'd0 ) && w_ringing ;\\\\nassign Led[2] = ( w_sw_ouput == 2'd1 ) && w_ringing ;\\\\nassign Led[3] = ( w_sw_ouput == 2'd2 ) && w_ringing ;\\\\nassign Led[4] = ( w_sw_ouput == 2'd3 ) && w_ringing ;\\\\n\\\\n//-------- disp gen ----------//\\\\nreg\\\\t[1:0]\\\\tcnt ;\\\\nassign w_sw_ouput = cnt ;\\\\nalways @(posedge clk_01 or negedge rst)\\\\nbegin\\\\nif(~rst) begin\\\\n\\\\tcnt <= 2'd0;\\\\nend\\\\nelse begin\\\\n\\\\tcnt <= cnt + 1'b1;\\\\nend\\\\n\\\\nend\\\\n\\\\n\\\\nreg [3:0] tmphex [0:3] ;\\\\nalways @(cnt)\\\\nbegin\\\\n if ( sw_setTime ) begin\\\\n\\\\t\\\\ttmphex[0] <= w_setmq0 ;\\\\n\\\\t\\\\ttmphex[1] <= w_setmq1 ;\\\\n\\\\t\\\\ttmphex[2] <= w_sethq0 ;\\\\n\\\\t\\\\ttmphex[3] <= w_sethq1 ;\\\\n\\\\tend\\\\n else if ( sw[4] | sw[3] | sw[2] | sw[1] ) begin\\\\n\\\\t\\\\ttmphex[0] <= w_acmq0 ;\\\\n\\\\t\\\\ttmphex[1] <= w_acmq1 ;\\\\n\\\\t\\\\ttmphex[2] <= w_achq0 ;\\\\n\\\\t\\\\ttmphex[3] <= w_achq1 ;\\\\n\\\\tend\\\\n\\\\telse begin\\\\n\\\\t\\\\ttmphex[0] <= sw_mshm ? w_sq0 : w_mq0 ;\\\\n tmphex[1] <= { 1'b0, ( sw_mshm ? w_sq1 : w_mq1 ) } ;\\\\n tmphex[2] <= sw_mshm ? w_mq0 : w_hq0 ;\\\\n tmphex[3] <= sw_mshm ? { 1'b0, w_mq1 } : { 2'b00, w_hq1 } ;\\\\n\\\\tend\\\\n\\\\n\\\\tcase(cnt)\\\\n\\\\t2'd0: sel = 4'b1110;\\\\n\\\\t2'd1: sel = 4'b1101;\\\\n\\\\t2'd2: sel = 4'b1011;\\\\n\\\\t2'd3: sel = 4'b0111;\\\\n\\\\n\\\\tdefault: sel = 4'b1110;\\\\n\\\\t\\\\t\\\\n\\\\tendcase\\\\n\\\\t\\\\n\\\\tdisphex = tmphex[cnt] ;\\\\nend\\\\n\\\\t\\\\ndisp seg_disp( .seg(seg), .an(an), .sel(sel), .hex(disphex));\\\\n\\\\n\\\\nendmodule"]
['module AU2_2Stage(A, B, sel, clk, out);\\\\n\\\\tinput [7:0] A, B;\\\\n\\\\tinput [1:0] sel;\\\\n\\\\tinput clk;\\\\n\\\\toutput [7:0] out;\\\\n\\\\tgenvar i;\\\\n\\\\twire [7:0] B_xor, fa_out, sum_mux, a_mux, b_mux, mux1_mux2;\\\\n\\\\twire nSel1, nSel0, and1, or1, nSum7;\\\\n\\\\twire [3:0] out_df;\\\\n\\\\t\\\\n\\\\tnot n2(nSel1, sel[1]);\\\\n\\\\tnot n3(nSel0, sel[0]);\\\\n\\\\tnot n4(nSum7, sum_mux[7]);\\\\n\\\\tor o1(or1, nSum7, out_df[3], out_df[2]);\\\\n\\\\tand a1(and1, out_df[1], out_df[0]);\\\\n\\\\t\\\\n\\\\tgenerate\\\\n\\\\tfor(i=7; i>=0; i=i-1) begin: xor1\\\\n\\\\t\\\\txor x1(B_xor[i], B[i], sel[1]);\\\\n\\\\tend\\\\n\\\\tendgenerate\\\\n\\\\t\\\\n\\\\tFA_8bit fa1(.A(A[7:0]),\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t.B(B_xor[7:0]),\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t.C_in(sel[1]),\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t.sum(fa_out[7:0])\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t);\\\\n\\\\tdff_8bit df1(.D(fa_out[7:0]),\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t .Q(sum_mux[7:0]),\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t .clk(clk)\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t);\\\\n\\\\tdff_8bit df2(.D(A[7:0]),\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t .Q(a_mux[7:0]),\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t .clk(clk)\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t);\\\\n\\\\tdff_8bit df3(.D(B[7:0]),\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t .Q(b_mux[7:0]),\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t .clk(clk)\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t);\\\\n\\\\tmux2to1_8bit m1(.A1(a_mux[7:0]), \\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t .B0(sum_mux[7:0]),\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t .sel(and1),\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t .C(mux1_mux2[7:0])\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t);\\\\n\\\\tmux2to1_8bit m2(.A1(mux1_mux2[7:0]),\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t .B0(b_mux[7:0]),\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t .sel(or1),\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t .C(out[7:0])\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t);\\\\n\\\\td_ff df_sel0(.D(sel[0]),\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t .Q(out_df[0]),\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t .clk(clk)\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t);\\\\n\\\\td_ff df_sel1(.D(sel[1]),\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t .Q(out_df[1]),\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t .clk(clk)\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t);\\\\n\\\\td_ff df_sel2(.D(nSel0),\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t .Q(out_df[3]),\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t .clk(clk)\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t);\\\\n\\\\td_ff df_sel3(.D(nSel1),\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t .Q(out_df[2]),\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t .clk(clk)\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t);\\\\nendmodule']
["module alu(ALU_out,Carry_out,A,B,ALU_sel,clk);\\\\nparameter n=32;\\\\ninput [n-1:0] A,B;\\\\ninput [2:0] ALU_sel;\\\\ninput clk;\\\\noutput [n-1:0] ALU_out;\\\\noutput Carry_out;\\\\nreg [n-1:0] ALU_result;\\\\nwire [n:0] temp,prod;\\\\n\\\\nassign ALU_out = ALU_result;\\\\nassign temp = {1'b0,A}+{1'b0,B};\\\\nassign Carry_out = temp[n];\\\\n\\\\nalways @(*)\\\\nbegin\\\\n case(ALU_sel)\\\\n 3'b000: ALU_result = A + B;\\\\n 3'b001: ALU_result = A - B;\\\\n 3'b010: ALU_result = prod;\\\\n 3'b011: ALU_result = A / B;\\\\n 3'b100: ALU_result = A << B;\\\\n 3'b101: ALU_result = A >> B;\\\\n 3'b110: ALU_result = A & B;\\\\n 3'b111: ALU_result = A | B;\\\\n default: ALU_result = A + B;\\\\n endcase\\\\nend\\\\nbooth_multiplier mul(prod,A,B,clk,(ALU_sel==3'b010));\\\\nendmodule", "module booth_multiplier(ans, m, q, clk, start);\\\\n parameter n = 16;\\\\n input[n-1:0] m, q;\\\\n output reg [2*n-1:0] ans;\\\\n input clk, start;\\\\n reg[2:0] state;\\\\n reg[5:0] cnt;\\\\n reg[n-1:0] ab, qb;\\\\n reg qm1;\\\\n parameter s0 = 3'b000, s1 = 3'b001, s2 = 3'b010, s3 = 3'b011, s4 = 3'b100, s5 = 3'b101;\\\\n always @(posedge clk)\\\\n begin\\\\n case(state)\\\\n s0 : if (start) state = s1;\\\\n s1 : begin\\\\n ab = 0; cnt = n; qb = q; qm1 = 0;\\\\n state = s2;\\\\n end\\\\n s2 : begin\\\\n if ({qb[0],qm1} == 2'b10)\\\\n begin\\\\n ab = ab - m;\\\\n state = s3;\\\\n end\\\\n else if({qb[0],qm1} == 2'b01)\\\\n begin\\\\n ab = ab + m;\\\\n state = s3;\\\\n end\\\\n else \\\\n begin\\\\n state = s3;\\\\n end\\\\n end \\\\n s3 : begin\\\\n {ab,qb,qm1} = {qb[0],ab,qb};\\\\n cnt = cnt - 1;\\\\n if (|cnt) state = s2;\\\\n else state = s4;\\\\n end\\\\n s4 : begin\\\\n ans = {ab, qb};\\\\n state = s5;\\\\n end\\\\n s5 : state = s5; \\\\n default : state = s0;\\\\n \\\\n endcase\\\\n end\\\\n endmodule"]
["module exp09(clk,clk_ls,hsync,vsync,vga_sync_n,valid,vga_r,vga_g,vga_b,ascii,block_addr,vgasource);\\\\n\\\\tinput clk;\\\\n\\\\tinput vgasource;//0:\\\\u5c4f\\\\u4fdd\\\\uff1b1:\\\\u7cfb\\\\u7edf\\\\n\\\\t\\\\n\\\\tinput [7:0] ascii;\\\\n\\\\toutput clk_ls,hsync,vsync,vga_sync_n,valid;\\\\n\\\\toutput [7:0] vga_r,vga_g,vga_b;\\\\n\\\\tassign vga_sync_n = 0;\\\\n\\\\treg [23:0] data = 0;\\\\n\\\\t//wire [23:0]wiredata = data;\\\\n\\\\twire [23:0] scdata;\\\\n\\\\n\\\\toutput reg [11:0] block_addr = 0;\\\\n\\\\treg [11:0] addr;\\\\n\\\\t//reg wren = 0;\\\\n\\\\twire [9:0] h_addr,v_addr;\\\\n\\\\twire [7:0] vga_ret = ascii[7:0];\\\\n\\\\twire [8:0] font_ret;\\\\n\\\\twire [7:0] waste;\\\\n\\\\treg [23:0] datares;\\\\n\\\\tclkgen #25000000 c(clk,1'b0,1'b1,clk_ls);\\\\n\\\\t//wire datares =wiredata & {24{vgasource}} | scdata & {24{~vgasource}};\\\\n\\\\tvga_ctrl v(.pclk(clk_ls),.reset(1'b0),.vga_data(datares),.h_addr(h_addr),.v_addr(v_addr),.hsync(hsync),.vsync(vsync),.valid(valid),.vga_r(vga_r),.vga_g(vga_g),.vga_b(vga_b));\\\\n\\\\ttop_flyinglogo screen(.pclk(clk_ls), .rst(1'b0), .valid(valid), .h_cnt(h_addr), .v_cnt(v_addr), .vga_data(scdata));\\\\n\\\\trom_font my_rom_font(.address(addr),.clock(clk_ls),.q(font_ret));\\\\n\\\\n\\\\talways @(clk_ls) begin\\\\n\\\\t\\\\tif(vgasource==1)begin\\\\n\\\\t\\\\t\\\\tdatares <= data;\\\\n\\\\t\\\\tend\\\\t\\\\n\\\\t\\\\telse begin\\\\n\\\\t\\\\t\\\\tdatares <= scdata;\\\\n\\\\t\\\\tend\\\\n\\\\tend\\\\n\\\\n\\\\talways @ (clk_ls)\\\\n\\\\tbegin\\\\n\\\\t\\\\t\\\\tblock_addr <= ((v_addr / 16 ) << 7)+ ((h_addr - 4) / 9);\\\\n\\\\t\\\\t\\\\taddr <= (vga_ret << 4) + (v_addr % 16);\\\\n\\\\t\\\\t\\\\tif(font_ret[h_addr%9] == 1'b1) data <= 24'hffffff;\\\\n\\\\t\\\\t\\\\telse data <= 24'h000000;\\\\n\\\\tend\\\\nendmodule"]
["module mips32_single_cycle(result_2,clk,instruction,pc);\\\\n\\\\noutput wire [31:0] instruction;\\\\noutput wire [31:0] pc;\\\\noutput [31:0] result_2;\\\\ninput clk;\\\\nwire [31:0] result,alu_3;\\\\nwire [2:0] select_bits_ALU;\\\\nwire [31:0] read_data_1, read_data_2;\\\\nwire signal_reg_write, clk,Add,Sub,select_bit_sltu,selectBit,shamtBit,i_type_select;\\\\nwire [31:0] cable_1_reg, cable_2_reg, Alu_result,cable_3,cable_4,cable_5_shamt;\\\\nwire [31:0] sltuResult;\\\\nwire ALUsrc;\\\\nwire [31:0] readData;\\\\nwire [1:0] ALUop;\\\\nwire [5:0] Output;\\\\nwire regWrite, memtoReg,zeroextimm;\\\\nwire [31:0] imm32;\\\\nwire andi,orri,addiu,lw,sw,beq,j;\\\\nwire regDst;\\\\nwire branch;\\\\nwire [31:0] alu_2;\\\\nwire zero;\\\\nwire [31:0] writeRegister;\\\\n\\\\ncommon_control_unit UNit(clk, select_bit_sltu, selectBit, shamtBit,\\\\nandi,orri,addiu,lw,sw,beq,j,\\\\ninstruction[5:0],\\\\ninstruction[31:26],\\\\nALUsrc,\\\\nALUop,\\\\nregWrite, memtoReg, regDst,zeroextimm\\\\n);\\\\n\\\\n\\\\nand and_aluop(i_type_select,ALUop[0],ALUop[1]);\\\\n\\\\nsix_bi_mux mux(instruction[5:0],instruction[31:26],i_type_select,Output);\\\\n\\\\ncontrol_unit c_Unit(select_bits_ALU, ALUop, Output);\\\\n\\\\nbit32_2x1mux Mux_77(instruction[15:11], instruction[20:16], regDst, writeRegister);\\\\nmips_registers m_Reg(read_data_1, read_data_2, result_2, instruction[25:21], instruction[20:16], writeRegister, regWrite, clk );\\\\n\\\\nbit32_2x1mux Mux_1(read_data_1,read_data_2,select_bit_sltu,cable_1_reg);\\\\nbit32_2x1mux Mux_2(read_data_2,read_data_1,select_bit_sltu,cable_2_reg);\\\\n\\\\nshamtModule gate_1(instruction,cable_5_shamt);\\\\n\\\\t\\\\nbit32_2x1mux Mux_3(cable_1_reg,cable_2_reg,shamtBit,cable_3);\\\\nbit32_2x1mux Mux_4(cable_2_reg,cable_5_shamt,shamtBit,cable_4);\\\\n\\\\n\\\\nbit32_2x1mux Mux_5(cable_4, imm32, ALUsrc, alu_3);\\\\n\\\\nbit32_2x1mux Mux_6(alu_3, 32'b0, zeroextimm, alu_2);\\\\n\\\\nalu32 Alu_1(cable_3, alu_2, select_bits_ALU,Alu_result,Add,Sub,selectBit,zero);\\\\n\\\\nsltModule gate(Alu_result[31],sltuResult);\\\\n\\\\nbit32_2x1mux Mux_16(Alu_result,sltuResult,select_bit_sltu,result);\\\\n\\\\nbit32_2x1mux Mux_7(result, readData, memtoReg, result_2);\\\\n\\\\n\\\\nsignextend signextend_1(imm32, instruction[15:0]);\\\\n\\\\n\\\\nand and_34654(branch, beq, zero);\\\\n\\\\nnextpc nextpc_1(clk, imm32, branch, pc, j, instruction[25:0]);\\\\ninstructionMemory instructionMemory_1(clk, pc, instruction);\\\\n\\\\ndataMemory dataMemory1(clk, Alu_result, read_data_2, readData, lw, sw);\\\\n\\\\n\\\\nendmodule"]
['module fpgaLE \\\\n\\\\t( input [15:0] lut\\\\n\\\\t, input [3:0][1:0] lutIns\\\\n\\\\t, input [1:0] northOutputConf\\\\n\\\\t, input [1:0] eastOutputConf\\\\n\\\\t, input [1:0] westOutputConf\\\\n\\\\t, input [1:0] southOutputConf\\\\n\\\\t\\\\n\\\\t, input northInput\\\\n\\\\t, input eastInput\\\\n\\\\t, input westInput\\\\n\\\\t, input southInput\\\\n\\\\t\\\\n\\\\t, output northOutputLCell\\\\n\\\\t, output eastOutputLCell\\\\n\\\\t, output westOutputLCell\\\\n\\\\t, output southOutputLCell\\\\n\\\\t);\\\\n\\\\t\\\\n\\\\twire [3:0] inputs;\\\\n\\\\twire lutOut;\\\\n\\\\twire northOutput, eastOutput, westOutput, southOutput;\\\\n\\\\twire [3:0] northOutputs, eastOutputs, westOutputs, southOutputs;\\\\n\\\\t\\\\n\\\\tassign inputs = {southInput, westInput, eastInput, northInput};\\\\n\\\\tassign lutOut = lut[\\\\n\\\\t\\\\t{ inputs[lutIns[3]]\\\\n\\\\t\\\\t, inputs[lutIns[2]]\\\\n\\\\t\\\\t, inputs[lutIns[1]]\\\\n\\\\t\\\\t, inputs[lutIns[0]]\\\\n\\\\t\\\\t}];\\\\n\\\\t\\\\t\\\\n\\\\tassign northOutputs = {lutOut, southInput, westInput, eastInput};\\\\n\\\\tassign eastOutputs = {lutOut, southInput, westInput, northInput};\\\\n\\\\tassign westOutputs = {lutOut, southInput, eastInput, northInput};\\\\n\\\\tassign southOutputs = {lutOut, westInput, eastInput, northInput};\\\\n\\\\t\\\\t\\\\n\\\\tassign northOutput = northOutputs[northOutputConf];\\\\n\\\\tassign eastOutput = eastOutputs[eastOutputConf];\\\\n\\\\tassign westOutput = westOutputs[westOutputConf];\\\\n\\\\tassign southOutput = southOutputs[southOutputConf];\\\\n\\\\t\\\\n\\\\tLCELL lcellN\\\\n\\\\t\\\\t( .in(northOutput)\\\\n\\\\t\\\\t, .out(northOutputLCell)\\\\n\\\\t\\\\t);\\\\n\\\\t\\\\t\\\\n\\\\tLCELL lcellE\\\\n\\\\t\\\\t( .in(eastOutput)\\\\n\\\\t\\\\t, .out(eastOutputLCell)\\\\n\\\\t\\\\t);\\\\n\\\\t\\\\t\\\\n\\\\tLCELL lcellW\\\\n\\\\t\\\\t( .in(westOutput)\\\\n\\\\t\\\\t, .out(westOutputLCell)\\\\n\\\\t\\\\t);\\\\n\\\\t\\\\t\\\\n\\\\tLCELL lcellS\\\\n\\\\t\\\\t( .in(southOutput)\\\\n\\\\t\\\\t, .out(southOutputLCell)\\\\n\\\\t\\\\t);\\\\n\\\\nendmodule']
['module stopwatch_01(clk,key_reset,key_start_pause,key_display_stop,\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\thex0,hex1,hex2,hex3,hex4,hex5,\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tled0,led1,led2,led3);\\\\n\\\\tinput\\\\tclk,key_reset,key_start_pause,key_display_stop;\\\\n\\\\toutput [6:0] hex0,hex1,hex2,hex3,hex4,hex5;\\\\n\\\\toutput led0,led1,led2,led3;\\\\n\\\\treg led0,led1,led2,led3;\\\\n\\\\t\\\\n\\\\treg display_work;\\\\n\\\\treg counter_work;\\\\n\\\\t\\\\n\\\\tparameter DELAY_TIME = 10000000;\\\\n\\\\t\\\\n\\\\treg [3:0] minute_display_high;\\\\n\\\\treg [3:0] minute_display_low;\\\\n\\\\treg [3:0] second_display_high;\\\\n\\\\treg [3:0] second_display_low;\\\\n\\\\treg [3:0] msecond_display_high;\\\\n\\\\treg [3:0] msecond_display_low;\\\\n\\\\t\\\\n\\\\treg [3:0] minute_counter_high;\\\\n\\\\treg [3:0] minute_counter_low;\\\\n\\\\treg [3:0] second_counter_high;\\\\n\\\\treg [3:0] second_counter_low;\\\\n\\\\treg [3:0] msecond_counter_high;\\\\n\\\\treg [3:0] msecond_counter_low;\\\\n\\\\t\\\\n\\\\treg [31:0] counter_50M;\\\\n\\\\t\\\\n\\\\treg reset_1_time;\\\\n\\\\treg [31:0] counter_reset;\\\\n\\\\treg start_1_time;\\\\n\\\\treg [31:0] counter_start;\\\\n\\\\treg display_1_time;\\\\n\\\\treg [31:0] counter_display;\\\\n\\\\t\\\\n\\\\treg start;\\\\n\\\\treg display;\\\\n\\\\t\\\\n\\\\tsevenseg LED8_minute_display_high(minute_display_high,hex5);\\\\n\\\\tsevenseg LED8_minute_display_low(minute_display_low,hex4);\\\\n\\\\tsevenseg LED8_second_display_high(second_display_high,hex3);\\\\n\\\\tsevenseg LED8_second_display_low(second_display_low,hex2);\\\\n\\\\tsevenseg LED8_msecond_display_high(msecond_display_high,hex1);\\\\n\\\\tsevenseg LED8_msecond_display_low(msecond_display_low,hex0);\\\\n\\\\t\\\\n\\\\tinitial\\\\n\\\\tbegin\\\\n\\\\t\\\\tdisplay_work = 0;\\\\n\\\\t\\\\tcounter_work = 0;\\\\n\\\\t\\\\t\\\\n\\\\t\\\\tminute_display_high = 0;\\\\n\\\\t\\\\tminute_display_low = 0;\\\\n\\\\t\\\\tsecond_display_high = 0;\\\\n\\\\t\\\\tsecond_display_low = 0;\\\\n\\\\t\\\\tmsecond_display_high = 0;\\\\n\\\\t\\\\tmsecond_display_low = 0;\\\\n\\\\t\\\\t\\\\n\\\\t\\\\tminute_counter_high = 0;\\\\n\\\\t\\\\tminute_counter_low = 0;\\\\n\\\\t\\\\tsecond_counter_high = 0;\\\\n\\\\t\\\\tsecond_counter_low = 0;\\\\n\\\\t\\\\tmsecond_counter_high = 0;\\\\n\\\\t\\\\tmsecond_counter_low = 0;\\\\n\\\\t\\\\t\\\\n\\\\t\\\\tcounter_50M = 0;\\\\n\\\\t\\\\t\\\\n\\\\t\\\\treset_1_time = 0;\\\\n\\\\t\\\\tcounter_reset = 0;\\\\n\\\\t\\\\tstart_1_time = 0;\\\\n\\\\t\\\\tcounter_start = 0;\\\\n\\\\t\\\\tdisplay_1_time = 0;\\\\n\\\\t\\\\tcounter_display = 0;\\\\n\\\\t\\\\t\\\\n\\\\t\\\\tstart = 0;\\\\n\\\\t\\\\tdisplay = 0;\\\\n\\\\tend\\\\n\\\\t\\\\t\\\\n\\\\t// process with input and display at each clk posedge\\\\n\\\\talways@(posedge clk)\\\\n\\\\tbegin\\\\n\\\\t\\\\t\\\\n\\\\t\\\\t// increase the minimal counter when counter_work is true\\\\n\\\\t\\\\tif(counter_work)counter_50M = counter_50M + 1;\\\\n\\\\t\\\\t\\\\n\\\\t\\\\t// update LEDs when display_work is true\\\\n\\\\t\\\\tif(display_work)\\\\n\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\tminute_display_high = minute_counter_high;\\\\n\\\\t\\\\t\\\\tminute_display_low = minute_counter_low;\\\\n\\\\t\\\\t\\\\tsecond_display_high = second_counter_high;\\\\n\\\\t\\\\t\\\\tsecond_display_low = second_counter_low;\\\\n\\\\t\\\\t\\\\tmsecond_display_high = msecond_counter_high;\\\\n\\\\t\\\\t\\\\tmsecond_display_low = msecond_counter_low;\\\\n\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\n\\\\t\\\\t// check input with joggle removing\\\\n\\\\t\\\\t// it looks like triggering on the button pressed down rather up\\\\n\\\\t\\\\tif(!key_display_stop && !counter_display)counter_display = 1;\\\\n\\\\t\\\\tif(counter_display)counter_display = counter_display + 1;\\\\n\\\\t\\\\tif(!key_reset && !counter_reset)counter_reset = 1;\\\\n\\\\t\\\\tif(counter_reset)counter_reset = counter_reset + 1;\\\\n\\\\t\\\\tif(!key_start_pause&& !counter_start)counter_start = 1;\\\\n\\\\t\\\\tif(counter_start)counter_start = counter_start + 1;\\\\n\\\\t\\\\t\\\\n\\\\t\\\\tif(counter_reset == DELAY_TIME)\\\\n\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\tminute_display_high = 0;\\\\n\\\\t\\\\t\\\\tminute_display_low = 0;\\\\n\\\\t\\\\t\\\\tsecond_display_high = 0;\\\\n\\\\t\\\\t\\\\tsecond_display_low = 0;\\\\n\\\\t\\\\t\\\\tmsecond_display_high = 0;\\\\n\\\\t\\\\t\\\\tmsecond_display_low = 0;\\\\n\\\\t\\\\t\\\\t\\\\n\\\\t\\\\t\\\\tminute_counter_high = 0;\\\\n\\\\t\\\\t\\\\tminute_counter_low = 0;\\\\n\\\\t\\\\t\\\\tsecond_counter_high = 0;\\\\n\\\\t\\\\t\\\\tsecond_counter_low = 0;\\\\n\\\\t\\\\t\\\\tmsecond_counter_high = 0;\\\\n\\\\t\\\\t\\\\tmsecond_counter_low = 0;\\\\n\\\\t\\\\t\\\\t\\\\n\\\\t\\\\t\\\\tcounter_50M = 0;\\\\n\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\n\\\\t\\\\tif(counter_display == DELAY_TIME)\\\\n\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\tcounter_display = 0;\\\\n\\\\t\\\\t\\\\tdisplay_work = !display_work;\\\\n\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\n\\\\t\\\\tif(counter_start == DELAY_TIME)\\\\n\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\tcounter_start = 0;\\\\n\\\\t\\\\t\\\\tcounter_work = !counter_work;\\\\n\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\n\\\\t\\\\t// process counter\\\\n\\\\t\\\\tif(counter_50M == 500000)\\\\n\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\tcounter_50M = 0;\\\\n\\\\t\\\\t\\\\tmsecond_counter_low = msecond_counter_low + 1;\\\\n\\\\t\\\\t\\\\t\\\\n\\\\t\\\\t\\\\tif(msecond_counter_low == 10)\\\\n\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\tmsecond_counter_high = msecond_counter_high + 1;\\\\n\\\\t\\\\t\\\\t\\\\tmsecond_counter_low = 0;\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t\\\\n\\\\t\\\\t\\\\tif(msecond_counter_high == 10)\\\\n\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\tsecond_counter_low = second_counter_low + 1;\\\\n\\\\t\\\\t\\\\t\\\\tmsecond_counter_high = 0;\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t\\\\n\\\\t\\\\t\\\\tif(second_counter_low == 10)\\\\n\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\tsecond_counter_high = second_counter_high + 1;\\\\n\\\\t\\\\t\\\\t\\\\tsecond_counter_low = 0;\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t\\\\n\\\\t\\\\t\\\\tif(second_counter_high == 6)\\\\n\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\tminute_counter_low = minute_counter_low + 1;\\\\n\\\\t\\\\t\\\\t\\\\tsecond_counter_high = 0;\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t\\\\n\\\\t\\\\t\\\\tif(minute_counter_low == 10)\\\\n\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\tminute_counter_high = minute_counter_high + 1;\\\\n\\\\t\\\\t\\\\t\\\\tminute_counter_low = 0;\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t\\\\n\\\\t\\\\t\\\\tif(minute_counter_high == 10)\\\\n\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\tminute_counter_high = 0;\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\tend\\\\n\\\\tend\\\\n\\\\t\\\\nendmodule', "module sevenseg(data,ledsegments);\\\\n\\\\tinput [3:0] data;\\\\n\\\\toutput ledsegments;\\\\n\\\\treg [6:0] ledsegments;\\\\n\\\\t\\\\n\\\\talways@(*)\\\\n\\\\tcase(data)\\\\n\\\\t\\\\t0:ledsegments = 7'b100_0000;\\\\n\\\\t\\\\t1:ledsegments = 7'b111_1001;\\\\n\\\\t\\\\t2:ledsegments = 7'b010_0100;\\\\n\\\\t\\\\t3:ledsegments = 7'b011_0000;\\\\n\\\\t\\\\t4:ledsegments = 7'b001_1001;\\\\n\\\\t\\\\t5:ledsegments = 7'b001_0010;\\\\n\\\\t\\\\t6:ledsegments = 7'b000_0010;\\\\n\\\\t\\\\t7:ledsegments = 7'b111_1000;\\\\n\\\\t\\\\t8:ledsegments = 7'b000_0000;\\\\n\\\\t\\\\t9:ledsegments = 7'b001_0000;\\\\n\\\\t\\\\tdefault:ledsegments = 7'b111_1111;\\\\n\\\\tendcase \\\\nendmodule"]
["module alu_cskpa(operand1, operand2, opcode, result, carry_out, product);\\\\ninput [31:0]operand1, operand2;\\\\ninput [3:0]opcode;\\\\noutput reg [31:0]result;\\\\noutput reg carry_out;\\\\noutput reg [63:0]product;\\\\n\\\\nwire [31:0]sum;\\\\nwire cout;\\\\n\\\\nCSkipA32 ins1(.sum(sum), .cout(cout), .a(operand1), .b(operand2));\\\\n\\\\nalways@*\\\\ncase(opcode)\\\\n// 5- The Arithmetic operations\\\\n//addition, subtraction, multiplication, increment and decrement // 5 operations\\\\n\\\\n`ADD: {carry_out,result}={cout,sum};\\\\n`SUB: {carry_out,result}=operand1 - operand2;\\\\n\\\\n`MUL: product=operand1 * operand2;\\\\n\\\\n`INCR: {carry_out,result}=operand1 + 1'b1;\\\\n`DECR: {carry_out,result}=operand1 - 1'b1;\\\\n\\\\n//7-The Bitwise logical operations\\\\n//AND, OR, NOT, NAND, NOR, XOR, XNOR // 7 operations\\\\n`AND: result=operand1 & operand2;\\\\n`OR: result=operand1 | operand2;\\\\n`NOT: result=~operand1;\\\\n`NAND:result=~(operand1 & operand2);\\\\n`NOR:result=~(operand1 | operand2);\\\\n`XOR:result=operand1 ^ operand2;\\\\n`XNOR: result=operand1 ^~ operand2;\\\\n//Shifting operations performed are \\\\n//Arithmetic and logical, left and right shift operations // 4 operations\\\\n`ARSH: result=operand1 >>> 1;\\\\n`ALSH: result=operand1 <<< 1;\\\\n`LRSH: result=operand1 >> 1;\\\\n`LLSH: result=operand1 << 1;\\\\nendcase\\\\nendmodule"]
['module top_cnn_tb;\\\\n\\\\nparameter KERNEL_SIZE = 3;\\\\nparameter LEARNING_RATE = 16\\'d15552; // 0.95 using WL = 16 and FL = 14\\\\nparameter WL = 16;\\\\nparameter FL = 14;\\\\n\\\\nparameter FF_MODE = 0, FB_MODE = 1, GR_MODE = 2;\\\\n\\\\ninteger i;\\\\n\\\\nreg CLK, RESET, Start;\\\\nreg signed [(WL - 1):0] in1, in2, in3, in4, in5, in6, in7, in8, in9;\\\\nreg signed [(WL - 1):0] label1, label2, label3, label4, label5, label6, label7, label8, label9, label10;\\\\nwire signed [(WL - 1):0] out1, out2, out3, out4, out5, out6, out7, out8, out9, out10;\\\\nwire Done;\\\\n\\\\ntop_cnn #(.KERNEL_SIZE(KERNEL_SIZE), .LEARNING_RATE(LEARNING_RATE), .WL(WL), .FL(FL)) dut(\\\\n CLK, RESET, Start, Done, \\\\n in1, in2, in3, in4, in5, in6, in7, in8, in9, \\\\n label1, label2, label3, label4, label5, label6, label7, label8, label9, label10,\\\\n out1, out2, out3, out4, out5, out6, out7, out8, out9, out10\\\\n);\\\\n\\\\nalways #5 CLK = ~CLK;\\\\n\\\\ninitial begin\\\\n RESET = 0;\\\\n CLK = 0;\\\\n in1 = (1 << (FL - 2));\\\\n in2 = (1 << (FL - 2));\\\\n in3 = (1 << (FL - 2));\\\\n in4 = (1 << (FL - 2));\\\\n in5 = (1 << (FL - 2));\\\\n in6 = (1 << (FL - 2));\\\\n in7 = (1 << (FL - 2));\\\\n in8 = (1 << (FL - 2));\\\\n in9 = (1 << (FL - 2));\\\\n label1 = (1 << (FL - 2));\\\\n label2 = (1 << (FL - 2));\\\\n label3 = (1 << (FL - 2));\\\\n label4 = (1 << (FL - 2));\\\\n label5 = (1 << (FL - 2));\\\\n label6 = (1 << (FL - 2));\\\\n label7 = (1 << (FL - 2));\\\\n label8 = (1 << (FL - 2));\\\\n label9 = (1 << (FL - 2));\\\\n label10 = (1 << (FL - 2));\\\\n \\\\n #15\\\\n \\\\n RESET = 1;\\\\n \\\\n #10\\\\n \\\\n Start = 1;\\\\n \\\\n #((2*3 + 1 + 1)*32*32 * 10 + 20)\\\\n\\\\n #(2*16*16*10 + 10)\\\\n \\\\n #(3*16*4*10 + 10)\\\\n \\\\n #20\\\\n \\\\n #(3*16*4*10*10 + 10)\\\\n \\\\n #(2*16*4*10 + 20)\\\\n \\\\n #(2*3*16*16*10 + 16*10)\\\\n \\\\n #(3*32*32*3*10 + 10)\\\\n \\\\n #10\\\\n \\\\n $stop;\\\\nend\\\\n\\\\n////====fsdb\\\\ninitial begin\\\\n\\\\t$helloworld;\\\\n\\\\t$fsdbDumpvars(\\\\"+fsdbfile+tb_dut_top.fsdb\\\\");\\\\n\\\\t$fsdbDumpSVA;\\\\nend\\\\n\\\\nendmodule']
["module layer6(clk, rst, start, dout_layer5, addr_layer5, addr_layer6, dout, done);\\\\ninput clk, rst, start;\\\\ninput signed [37:0] dout_layer5;\\\\ninput [6:0] addr_layer6;\\\\noutput reg [6:0] addr_layer5;\\\\noutput signed [45:0] dout;\\\\noutput reg done;\\\\nreg [13:0] addr_w;\\\\nwire signed [10:0] dout_w;\\\\nreg [6:0] addr_b;\\\\nwire signed [45:0] dout_b;\\\\nwire signed [45:0] dout_mul;\\\\nreg [3:0] state; \\\\nreg [6:0] addr_layer6_reg;\\\\n\\\\nreg signed [45:0] din_layer6;\\\\nreg wea;\\\\nreg [15:0] cnt_addr_ctrl, cnt_weights_ctrl, cnt_400, cnt_entire, cnt_input_ctrl, cnt_weights_stride; \\\\nreg signed [45:0] sum_mul;\\\\nwire signed [45:0] dout_b_shift ;\\\\nlayer6_w u0(.clka(clk), .addra(addr_w), .douta(dout_w));\\\\nlayer6_b u1(.clka(clk), .addra(addr_b), .douta(dout_b));\\\\nmult_layer6 u2(.CLK(clk), .A(dout_layer5), .B(dout_w), .P(dout_mul));\\\\nlayer6_o u3(.clka(clk) ,.wea(wea), .addra(addr_layer6_reg), .dina(din_layer6), .clkb(clk), .addrb(addr_layer6), .doutb(dout));\\\\nlocalparam IDLE = 4'd0, FC = 4'd1, DONE = 4'd2;\\\\n\\\\nassign dout_b_shift = (dout_b[45] == 1'b1) ? {1'b1,dout_b[44:0]<<24} : {1'b0,dout_b[44:0]<<24};\\\\nalways@(posedge clk or posedge rst)\\\\nbegin\\\\n if(rst)\\\\n state <= IDLE;\\\\n else\\\\n case(state)\\\\n IDLE : if(start) state <= FC ; else state <= IDLE;\\\\n FC : if(addr_layer6_reg == 83&& cnt_addr_ctrl == 0) state <= DONE; else state <= FC;\\\\n //DONE : if(addr_layer6 == 83) state <= IDLE; else state <= DONE; //good write? confirm\\\\n DONE : state <= IDLE;\\\\n default state <= IDLE;\\\\n endcase\\\\nend\\\\n\\\\nalways@(posedge clk or posedge rst)\\\\nbegin\\\\n if(rst)\\\\n cnt_input_ctrl <= 7'd0;\\\\n else\\\\n case(state)\\\\n FC : if(cnt_input_ctrl == 119) cnt_input_ctrl <= 0; else cnt_input_ctrl <= cnt_input_ctrl + 1'd1;\\\\n default : cnt_input_ctrl <= 7'd0;\\\\n endcase\\\\nend\\\\n\\\\nalways@(posedge clk or posedge rst)\\\\nbegin\\\\n if(rst)\\\\n addr_layer5 <= 7'd0;\\\\n else\\\\n case(state)\\\\n FC : if(addr_layer5 == 119) addr_layer5 <= 7'd0; else addr_layer5 <= cnt_input_ctrl ;\\\\n default : addr_layer5 <= 7'd0;\\\\n endcase\\\\nend \\\\nalways@(posedge clk or posedge rst)\\\\nbegin\\\\n if(rst)\\\\n cnt_weights_ctrl <= 16'd0; \\\\n else\\\\n case(state)\\\\n IDLE: cnt_weights_ctrl<= 16'd0;\\\\n default : if(cnt_weights_ctrl == 119) cnt_weights_ctrl <= 16'd0; else cnt_weights_ctrl <= cnt_weights_ctrl + 1'd1;\\\\n endcase\\\\nend\\\\n\\\\nalways@(posedge clk or posedge rst)\\\\nbegin\\\\n if(rst)\\\\n cnt_weights_stride <= 16'd0;\\\\n else\\\\n case(state)\\\\n IDLE : cnt_weights_stride <= 16'd0;\\\\n DONE : cnt_weights_stride <= 16'd0;\\\\n default :if(cnt_weights_ctrl == 119) cnt_weights_stride <= cnt_weights_stride + 9'd120; \\\\n else cnt_weights_stride <= cnt_weights_stride;\\\\n endcase\\\\nend \\\\n\\\\nalways@(posedge clk or posedge rst)\\\\nbegin\\\\n if(rst)\\\\n cnt_400 <= 16'd0;\\\\n else\\\\n case(state)\\\\n IDLE : cnt_400 <= 16'd0;\\\\n default : if(cnt_400 == 16'd119) cnt_400 <= 0; else cnt_400 <= cnt_400 + 1'd1;\\\\n endcase\\\\nend \\\\nalways@(posedge clk or posedge rst)\\\\nbegin\\\\n if(rst)\\\\n addr_w <= 16'd0;\\\\n else\\\\n case(state)\\\\n FC : if(addr_w == cnt_weights_stride + 9'd119) addr_w <= cnt_weights_stride; else addr_w <= cnt_weights_stride + cnt_400;\\\\n default : addr_w <= 16'd0;\\\\n endcase\\\\nend\\\\n\\\\n\\\\nalways@(posedge clk or posedge rst)\\\\nbegin\\\\n if(rst)\\\\n cnt_entire <= 32'd0;\\\\n else\\\\n case(state)\\\\n IDLE: cnt_entire <= 32'd0;\\\\n DONE: cnt_entire <= 32'd0;\\\\n default : cnt_entire <= cnt_entire + 1'd1;\\\\n endcase\\\\nend\\\\n\\\\n\\\\n\\\\nalways@(posedge clk or posedge rst)\\\\nbegin\\\\n if(rst)\\\\n cnt_addr_ctrl <= 16'd0;\\\\n else\\\\n case(state)\\\\n FC: if(cnt_entire < 7) cnt_addr_ctrl <= 16'd0; else if(cnt_addr_ctrl == 119) cnt_addr_ctrl <=16'd0; else cnt_addr_ctrl <= cnt_addr_ctrl + 1'd1;\\\\n default : cnt_addr_ctrl <= 16'd0;\\\\n endcase\\\\nend\\\\n\\\\nalways@(posedge clk or posedge rst)\\\\nbegin\\\\n if(rst)\\\\n sum_mul <= 32'd0;\\\\n else\\\\n case(state)\\\\n FC : if(cnt_entire < 6) sum_mul <= 0; \\\\n else if(cnt_addr_ctrl == 119) sum_mul <= dout_mul; \\\\n else sum_mul <= sum_mul + dout_mul;\\\\n default : sum_mul <= 0;\\\\n endcase\\\\nend\\\\n\\\\nalways@(posedge clk or posedge rst)\\\\nbegin\\\\n if(rst)\\\\n addr_b <= 3'd0;\\\\n else\\\\n begin\\\\n case(state)\\\\n IDLE : addr_b <= 3'd0;\\\\n DONE : addr_b <= 3'd0;\\\\n default :if(cnt_weights_ctrl == 119 && cnt_weights_stride != 16'd9960) addr_b <= addr_b + 1'd1; \\\\n else addr_b <= addr_b;\\\\n endcase\\\\n end\\\\nend \\\\n\\\\n\\\\n\\\\nalways@(posedge clk or posedge rst)\\\\nbegin\\\\n if(rst)\\\\n din_layer6 <= 16'd0;\\\\n else\\\\n case(state)\\\\n FC :if(cnt_addr_ctrl == 119) din_layer6 <= (sum_mul+ dout_b_shift > 0) ? sum_mul + dout_b_shift : 0; else din_layer6 <= din_layer6;\\\\n default : din_layer6 <= din_layer6;\\\\n endcase\\\\nend\\\\n\\\\nalways@(posedge clk or posedge rst)\\\\nbegin\\\\n if(rst)\\\\n addr_layer6_reg <= 0;\\\\n else\\\\n case(state)\\\\n FC : if(cnt_addr_ctrl == 16'd0 && cnt_entire > 20 && addr_layer6_reg != 83) addr_layer6_reg <= addr_layer6_reg + 1'd1; \\\\n else if(addr_layer6_reg == 83 && cnt_addr_ctrl == 16'd0) addr_layer6_reg <= 0;\\\\n else addr_layer6_reg <= addr_layer6_reg;\\\\n default addr_layer6_reg <= addr_layer6_reg;\\\\n endcase\\\\nend\\\\n\\\\nalways@(posedge clk or posedge rst)\\\\nbegin\\\\n if(rst)\\\\n wea <= 1'd0;\\\\n else\\\\n case(state)\\\\n FC : if(cnt_addr_ctrl == 119) wea <= 1'd1; else wea <= 1'd0;\\\\n default : wea <= 1'd0;\\\\n endcase\\\\nend\\\\n\\\\nalways@(posedge clk or posedge rst)\\\\nbegin\\\\n if(rst)\\\\n done <= 1'd0;\\\\n else\\\\n case(state)\\\\n DONE : done <= 1'd1;\\\\n default : done <= 1'd0;\\\\n endcase\\\\nend\\\\n\\\\n/*\\\\nalways@(posedge clk or posedge rst)\\\\nbegin\\\\n if(rst)\\\\n addr_layer6 <= 7'd0;\\\\n else\\\\n case(state)\\\\n DONE : addr_layer6 <= addr_layer6 + 1'd1;\\\\n default : done <= 1'd0;\\\\n endcase\\\\nend\\\\n*/\\\\nendmodule"]
["module test_Processing_Unit();\\\\n\\\\tparameter word_size = 10;\\\\n\\\\tparameter data_size = 8;\\\\n\\\\tparameter op_size = 4;\\\\n\\\\tparameter Sel1_size = 3;\\\\n\\\\tparameter Sel2_size = 3;\\\\n\\\\treg [6:0] address_decoded;\\\\n\\\\treg [7:0] constant_decoded;\\\\n\\\\treg [word_size-1: 0] \\\\tmem_word;\\\\n\\\\treg \\\\t\\\\tLoad_R0, Load_R1, Load_R2, Load_R3, Load_PC, Inc_PC;\\\\n\\\\treg [Sel1_size-1: 0] \\\\tSel_Bus_1a_Mux,Sel_Bus_1b_Mux;\\\\n\\\\treg [Sel2_size-1: 0] \\\\tSel_Bus_2_Mux;\\\\n\\\\treg \\\\t\\\\t\\\\tLoad_IR, Load_Add_R, Load_Reg_Z;\\\\n\\\\treg \\\\t\\\\t\\\\tclk, rst;\\\\n\\\\n\\\\twire [word_size-1: 0] \\\\tinstruction;\\\\n\\\\twire [6:0]\\\\taddress;\\\\n\\\\twire [data_size-1: 0] \\\\tBus_1a,Bus_1b;\\\\n\\\\twire \\\\t\\\\tZflag;\\\\n\\\\twire [data_size-1: 0] R0_out, R1_out, R2_out, R3_out,PC_count;\\\\n\\\\tinitial\\\\n\\\\tbegin\\\\n\\\\t\\\\tclk = 0;\\\\n\\\\tend\\\\n\\\\talways #5 clk = ~clk;\\\\n\\\\t\\\\n\\\\t//begin test signal\\\\n\\\\t\\\\n\\\\twire [7:0] r0 = process1.R0.data_out[7:0];\\\\n\\\\twire [7:0] r1 = process1.R1.data_out[7:0];\\\\t\\\\n\\\\twire [7:0] r2 = process1.R2.data_out[7:0];\\\\n\\\\twire [7:0] r3 = process1.R3.data_out[7:0];\\\\n\\\\twire [9:0] bus2 = process1.Bus_2[9:0];\\\\n\\\\t//end test signal\\\\n\\\\t\\\\t\\\\n Processing_Unit process1(instruction, Zflag, address, address_decoded, constant_decoded, Bus_1a,Bus_1b, mem_word, Load_R0, Load_R1, Load_R2, Load_R3, Load_PC, Inc_PC, Sel_Bus_1a_Mux,Sel_Bus_1b_Mux, Load_IR, Load_Add_R, Load_Reg_Z, Sel_Bus_2_Mux, clk, rst,R0_out, R1_out, R2_out, R3_out,PC_count);\\\\n\\\\t\\\\n\\\\t\\\\n initial \\\\n begin\\\\n \\\\taddress_decoded[6:0]=0;\\\\n\\\\tconstant_decoded[7:0] = 0;\\\\n\\\\tmem_word[word_size-1: 0] =0;\\\\n\\\\tLoad_R0 = 0; Load_R1 = 0; Load_R2 = 0; Load_R3 = 0; Load_PC = 0; Inc_PC = 0;\\\\n\\\\tSel_Bus_1a_Mux [2:0] = 0;\\\\n\\\\tSel_Bus_1b_Mux [2:0] = 0;\\\\n\\\\tSel_Bus_2_Mux[2: 0] = 0 ;\\\\n\\\\tLoad_IR = 0; Load_Add_R = 0; Load_Reg_Z = 0;\\\\n\\\\t//r0 = r1 + r2 =>> r2 = r1 + r2\\\\n\\\\t#10 \\\\n\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\tmem_word[9:0] = 10'b0000100110;\\\\n\\\\t\\\\t\\\\tprocess1.R0.data_out=0;process1.R1.data_out=1;process1.R2.data_out=2;process1.R3.data_out=3;\\\\n\\\\t\\\\t\\\\tSel_Bus_1a_Mux[2:0]=4; //sel_PCa = 1\\\\n\\\\t\\\\t\\\\tSel_Bus_2_Mux[2:0]=1;\\\\n\\\\t\\\\t\\\\tLoad_Add_R=1;\\\\n\\\\t\\\\tend\\\\n\\\\t // S_fet2\\\\n\\\\t#10\\\\n\\\\t\\\\tbegin \\\\n\\\\t\\\\t\\\\tSel_Bus_2_Mux[2:0] =2 ; //Sel_Mem = 1;\\\\n\\\\t\\\\t\\\\tLoad_IR = 1; \\\\n\\\\t\\\\t\\\\tInc_PC = 1; \\\\n\\\\t\\\\tend \\\\n\\\\t//S_dec\\\\n\\\\t#10\\\\n\\\\t\\\\tbegin\\\\n\\\\t\\\\tSel_Bus_1a_Mux[2:0]=1; //Sel_R1a = 1;\\\\n\\\\t\\\\tSel_Bus_1b_Mux[2:0]=2;\\\\t\\\\t//Sel_R2b = 1;\\\\t\\\\t\\\\n\\\\t\\\\tend\\\\n\\\\t//ex1\\\\n\\\\t#10\\\\n\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\tLoad_Reg_Z = 1;\\\\n\\\\t\\\\t\\\\tSel_Bus_2_Mux[2:0]=0;\\\\t\\\\t//Sel_ALU = 1; \\\\n\\\\t\\\\t\\\\tLoad_R0 = 1;\\\\n\\\\t\\\\tend\\\\n\\\\t//r0 = r3-r1 =>> r0 = 3-1 = 2\\\\n end\\\\nendmodule"]
['module bit8_2to1mux(out,sel,in1,in2);\\\\n\\\\tinput [7:0] in1,in2;\\\\n\\\\toutput [7:0] out;\\\\n\\\\tinput sel;\\\\n\\\\tmux2to1 m0(out[0],sel,in1[0],in2[0]);\\\\n\\\\tmux2to1 m1(out[1],sel,in1[1],in2[1]);\\\\n\\\\tmux2to1 m2(out[2],sel,in1[2],in2[2]);\\\\n\\\\tmux2to1 m3(out[3],sel,in1[3],in2[3]);\\\\n\\\\tmux2to1 m4(out[4],sel,in1[4],in2[4]);\\\\n\\\\tmux2to1 m5(out[5],sel,in1[5],in2[5]);\\\\n\\\\tmux2to1 m6(out[6],sel,in1[6],in2[6]);\\\\n\\\\tmux2to1 m7(out[7],sel,in1[7],in2[7]);\\\\nendmodule', 'module bit8_2to1mux(out,sel,in1,in2);\\\\n\\\\tinput [7:0] in1,in2;\\\\n\\\\toutput [7:0] out;\\\\n\\\\tinput sel;\\\\n\\\\tgenvar j;\\\\n\\\\t//this is the variable that is be used in the generate //block\\\\n\\\\tgenerate for (j=0; j<8;j=j+1) \\\\n\\\\tbegin: mux_loop //mux_loop is the name of the loop\\\\n\\\\t\\\\tmux2to1 m1(out[j],sel,in1[j],in2[j]);\\\\n\\\\t\\\\t//mux2to1 is instantiated every time it is called\\\\n\\\\tend\\\\n\\\\tendgenerate\\\\nendmodule']
['module fourToOneMux(V0,V1,V2,V3,Op1,Op0,O);\\\\n\\\\tinput V0,V1,V2,V3,Op1,Op0;\\\\n\\\\toutput O;\\\\n\\\\n\\\\t//create negative\\\\n\\\\twire Op1Neg,Op0Neg;\\\\n\\\\tnand Op1NegGate(Op1Neg,Op1,Op1);\\\\n\\\\tnand Op0NegGate(Op0Neg,Op0,Op0);\\\\n\\\\t\\\\n\\\\t//3way and outputs\\\\n\\\\twire V0Out,V1Out,V2Out,V3Out;\\\\n\\\\t\\\\n\\\\t//V0\\\\n\\\\tthreeWayAnd V0Gate(Op1Neg,Op0Neg,V0,V0Out);\\\\n\\\\t\\\\n\\\\t//V1\\\\n\\\\tthreeWayAnd V1Gate(Op1Neg,Op0,V1,V1Out);\\\\n\\\\t\\\\n\\\\t//V2\\\\n\\\\tthreeWayAnd V2Gate(Op1,Op0Neg,V2,V2Out);\\\\n\\\\t\\\\n\\\\t//V3\\\\n\\\\tthreeWayAnd V3Gate(Op1,Op0,V3,V3Out);\\\\n\\\\t\\\\n\\\\t//OR the outputs together\\\\n\\\\twire outputWire;\\\\n\\\\tfourWayOr outputOr(V0Out,V1Out,V2Out,V3Out,outputWire);\\\\n\\\\t\\\\n\\\\tassign O=outputWire;\\\\nendmodule', 'module twoToOneMux(A,B,Op,O);\\\\n\\\\tinput A,B,Op;\\\\n\\\\toutput O;\\\\n\\\\t\\\\n\\\\twire OpNeg;\\\\n\\\\tnand OpNegGate(OpNeg,Op,Op);\\\\n\\\\t\\\\n\\\\t//A\\\\n\\\\twire firstNandwire,AOut;\\\\n\\\\tnand firstNand1(firstNandwire,A,OpNeg);\\\\n\\\\tnand secondNand1(AOut,firstNandwire,firstNandwire);\\\\n\\\\t\\\\n\\\\t//B\\\\n\\\\twire secondNandwire,BOut;\\\\n\\\\tnand firstNand2(secondNandwire,B,Op);\\\\n\\\\tnand secondNand2(BOut,secondNandwire,secondNandwire);\\\\n\\\\t\\\\n\\\\t// A or B\\\\n\\\\twire topGate,botGate;\\\\n\\\\tnand leftGateTop(topGate,AOut,AOut);\\\\n\\\\tnand leftGateBot(botGate,BOut,BOut);\\\\n\\\\tnand finGate(O,topGate,botGate);\\\\n\\\\nendmodule', 'module sixteenBitTwoToOneMux(A,B,Op,O);\\\\n\\\\tinput [15:0] A;\\\\n\\\\tinput [15:0] B;\\\\n\\\\tinput Op;\\\\n\\\\toutput [15:0] O;\\\\n\\\\t\\\\n\\\\t\\\\n\\\\ttwoToOneMux bits0(A[0],B[0],Op,O[0]);\\\\n\\\\ttwoToOneMux bits1(A[1],B[1],Op,O[1]);\\\\n\\\\ttwoToOneMux bits2(A[2],B[2],Op,O[2]);\\\\n\\\\ttwoToOneMux bits3(A[3],B[3],Op,O[3]);\\\\n\\\\ttwoToOneMux bits4(A[4],B[4],Op,O[4]);\\\\n\\\\ttwoToOneMux bits5(A[5],B[5],Op,O[5]);\\\\n\\\\ttwoToOneMux bits6(A[6],B[6],Op,O[6]);\\\\n\\\\ttwoToOneMux bits7(A[7],B[7],Op,O[7]);\\\\n\\\\ttwoToOneMux bits8(A[8],B[8],Op,O[8]);\\\\n\\\\ttwoToOneMux bits9(A[9],B[9],Op,O[9]);\\\\n\\\\ttwoToOneMux bits10(A[10],B[10],Op,O[10]);\\\\n\\\\ttwoToOneMux bits11(A[11],B[11],Op,O[11]);\\\\n\\\\ttwoToOneMux bits12(A[12],B[12],Op,O[12]);\\\\n\\\\ttwoToOneMux bits13(A[13],B[13],Op,O[13]);\\\\n\\\\ttwoToOneMux bits14(A[14],B[14],Op,O[14]);\\\\n\\\\ttwoToOneMux bits15(A[15],B[15],Op,O[15]);\\\\n\\\\t\\\\nendmodule', 'module TwoToOneMux32(A,B,Op,O);\\\\n\\\\tinput [31:0] A;\\\\n\\\\tinput [31:0] B;\\\\n\\\\tinput Op;\\\\n\\\\toutput reg [31:0] O;\\\\n\\\\t\\\\n\\\\t\\\\n\\\\talways@(A or B or Op) begin\\\\n\\\\t if(Op == 0) begin\\\\n\\\\t O = A;\\\\n\\\\t end\\\\n\\\\t if(Op == 1) begin\\\\n\\\\t O = B;\\\\n\\\\t end\\\\n\\\\tend\\\\n\\\\t\\\\n\\\\t/*twoToOneMux bits0(A[0],B[0],Op,O[0]);\\\\n\\\\ttwoToOneMux bits1(A[1],B[1],Op,O[1]);\\\\n\\\\ttwoToOneMux bits2(A[2],B[2],Op,O[2]);\\\\n\\\\ttwoToOneMux bits3(A[3],B[3],Op,O[3]);\\\\n\\\\ttwoToOneMux bits4(A[4],B[4],Op,O[4]);\\\\n\\\\ttwoToOneMux bits5(A[5],B[5],Op,O[5]);\\\\n\\\\ttwoToOneMux bits6(A[6],B[6],Op,O[6]);\\\\n\\\\ttwoToOneMux bits7(A[7],B[7],Op,O[7]);\\\\n\\\\ttwoToOneMux bits8(A[8],B[8],Op,O[8]);\\\\n\\\\ttwoToOneMux bits9(A[9],B[9],Op,O[9]);\\\\n\\\\ttwoToOneMux bits10(A[10],B[10],Op,O[10]);\\\\n\\\\ttwoToOneMux bits11(A[11],B[11],Op,O[11]);\\\\n\\\\ttwoToOneMux bits12(A[12],B[12],Op,O[12]);\\\\n\\\\ttwoToOneMux bits13(A[13],B[13],Op,O[13]);\\\\n\\\\ttwoToOneMux bits14(A[14],B[14],Op,O[14]);\\\\n\\\\ttwoToOneMux bits15(A[15],B[15],Op,O[15]);\\\\n\\\\ttwoToOneMux bits16(A[16],B[16],Op,O[16]);\\\\n\\\\ttwoToOneMux bits17(A[17],B[17],Op,O[17]);\\\\n\\\\ttwoToOneMux bits18(A[18],B[18],Op,O[18]);\\\\n\\\\ttwoToOneMux bits19(A[19],B[19],Op,O[19]);\\\\n\\\\ttwoToOneMux bits20(A[20],B[20],Op,O[20]);\\\\n\\\\ttwoToOneMux bits21(A[21],B[21],Op,O[21]);\\\\n\\\\ttwoToOneMux bits22(A[22],B[22],Op,O[22]);\\\\n\\\\ttwoToOneMux bits23(A[23],B[23],Op,O[23]);\\\\n\\\\ttwoToOneMux bits24(A[24],B[24],Op,O[24]);\\\\n\\\\ttwoToOneMux bits25(A[25],B[25],Op,O[25]);\\\\n\\\\ttwoToOneMux bits26(A[26],B[26],Op,O[26]);\\\\n\\\\ttwoToOneMux bits27(A[27],B[27],Op,O[27]);\\\\n\\\\ttwoToOneMux bits28(A[28],B[28],Op,O[28]);\\\\n\\\\ttwoToOneMux bits29(A[29],B[29],Op,O[29]);\\\\n\\\\ttwoToOneMux bits30(A[30],B[30],Op,O[30]);\\\\n\\\\ttwoToOneMux bits31(A[31],B[31],Op,O[31]);*/\\\\n\\\\t\\\\n\\\\t\\\\nendmodule', "module OneToTwoMux32(In,A,B,Op);\\\\n\\\\tinput [31:0] In;\\\\n\\\\tinput Op;\\\\n\\\\toutput reg [31:0] A,B;\\\\n\\\\n always@(In or Op) begin\\\\n\\\\t if(Op == 0) begin\\\\n\\\\t A = In;\\\\n\\\\t B = 32'b0;\\\\n\\\\t end\\\\n\\\\t if(Op == 1) begin\\\\n\\\\t B = In;\\\\n\\\\t A = 32'b0;\\\\n\\\\t end\\\\n\\\\tend\\\\n\\\\n\\\\t/*OneToTwoMux bit0(In[0],A[0],B[0],Op);\\\\n\\\\tOneToTwoMux bit1(In[1],A[1],B[1],Op);\\\\n\\\\tOneToTwoMux bit2(In[2],A[2],B[2],Op);\\\\n\\\\tOneToTwoMux bit3(In[3],A[3],B[3],Op);\\\\n\\\\tOneToTwoMux bit4(In[4],A[4],B[4],Op);\\\\n\\\\tOneToTwoMux bit5(In[5],A[5],B[5],Op);\\\\n\\\\tOneToTwoMux bit6(In[6],A[6],B[6],Op);\\\\n\\\\tOneToTwoMux bit7(In[7],A[7],B[7],Op);\\\\n\\\\tOneToTwoMux bit8(In[8],A[8],B[8],Op);\\\\n\\\\tOneToTwoMux bit9(In[9],A[9],B[9],Op);\\\\n\\\\tOneToTwoMux bit10(In[10],A[10],B[10],Op);\\\\n\\\\tOneToTwoMux bit11(In[11],A[11],B[11],Op);\\\\n\\\\tOneToTwoMux bit12(In[12],A[12],B[12],Op);\\\\n\\\\tOneToTwoMux bit13(In[13],A[13],B[13],Op);\\\\n\\\\tOneToTwoMux bit14(In[14],A[14],B[14],Op);\\\\n\\\\tOneToTwoMux bit15(In[15],A[15],B[15],Op);\\\\n\\\\tOneToTwoMux bit16(In[16],A[16],B[16],Op);\\\\n\\\\tOneToTwoMux bit17(In[17],A[17],B[17],Op);\\\\n\\\\tOneToTwoMux bit18(In[18],A[18],B[18],Op);\\\\n\\\\tOneToTwoMux bit19(In[19],A[19],B[19],Op);\\\\n\\\\tOneToTwoMux bit20(In[20],A[20],B[20],Op);\\\\n\\\\tOneToTwoMux bit21(In[21],A[21],B[21],Op);\\\\n\\\\tOneToTwoMux bit22(In[22],A[22],B[22],Op);\\\\n\\\\tOneToTwoMux bit23(In[23],A[23],B[23],Op);\\\\n\\\\tOneToTwoMux bit24(In[24],A[24],B[24],Op);\\\\n\\\\tOneToTwoMux bit25(In[25],A[25],B[25],Op);\\\\n\\\\tOneToTwoMux bit26(In[26],A[26],B[26],Op);\\\\n\\\\tOneToTwoMux bit27(In[27],A[27],B[27],Op);\\\\n\\\\tOneToTwoMux bit28(In[28],A[28],B[28],Op);\\\\n\\\\tOneToTwoMux bit29(In[29],A[29],B[29],Op);\\\\n\\\\tOneToTwoMux bit30(In[30],A[30],B[30],Op);\\\\n\\\\tOneToTwoMux bit31(In[31],A[31],B[31],Op);*/\\\\n\\\\t\\\\nendmodule", 'module OneToTwoMux(In,A,B,Op);\\\\n\\\\tinput In,Op;\\\\n\\\\toutput A,B;\\\\n\\\\t\\\\n\\\\tnot(Op_bar,Op);\\\\n\\\\tand(A,In,Op);\\\\n\\\\tand(B,In,Op_bar);\\\\n\\\\t\\\\nendmodule']
['module cpu(start, rst, instruction, data_var, clk, done, reg0_tri, reg1_tri, reg2_tri, reg3_tri, state);\\\\n\\\\t//TODO\\\\n\\\\t//ADD A FREAKING ALU!!!!!11!1!11!!11!!!!111\\\\n\\\\tinput start;\\\\n\\\\tinput rst;\\\\n\\\\tinput [8:0] instruction;\\\\n\\\\tinput [15:0] data_var;\\\\n\\\\tinput clk;\\\\n\\\\toutput done;\\\\n\\\\toutput [15:0] reg0_tri, reg1_tri, reg2_tri, reg3_tri;\\\\n\\\\toutput [3:0] state;\\\\n\\\\n\\\\twire [15:0] bus;\\\\n\\\\n\\\\twire [15:0] reg4_tri, reg5_tri, reg6_tri, reg7_tri, regG_tri;\\\\n\\\\twire [7:0] in_reg, out_reg;\\\\n\\\\twire [15:0] regA_output;\\\\n\\\\twire [15:0] result;\\\\n\\\\twire data, Ain, Gin, Gout;\\\\n\\\\n\\\\n\\\\n\\\\t// THE BRAINS OF THE OPERATION\\\\n\\\\tcontrol_circuit control(.start(start), .rst(rst), .instruction(instruction), .in_reg(in_reg), .out_reg(out_reg), .data(data), .Ain(Ain), .Gin(Gin), .Gout(Gout), .done(done), .clk(clk), .curr_state(state)); \\\\n\\\\n\\\\t// 8 BIT CPU REGISTERS\\\\n\\\\tsixteen_bit_register reg0 (.D(bus), .enable(in_reg[0]), .clk(clk), .rst(rst), .Q(reg0_tri));\\\\n\\\\ttri_buf buf0(.a(reg0_tri), .b(bus), .enable(out_reg[0]));\\\\n\\\\n\\\\tsixteen_bit_register reg1 (.D(bus), .enable(in_reg[1]), .clk(clk), .rst(rst), .Q(reg1_tri));\\\\n\\\\ttri_buf buf1(.a(reg1_tri), .b(bus), .enable(out_reg[1]));\\\\n\\\\n\\\\tsixteen_bit_register reg2 (.D(bus), .enable(in_reg[2]), .clk(clk), .rst(rst), .Q(reg2_tri));\\\\n\\\\ttri_buf buf2(.a(reg2_tri), .b(bus), .enable(out_reg[2]));\\\\n\\\\n\\\\tsixteen_bit_register reg3 (.D(bus), .enable(in_reg[3]), .clk(clk), .rst(rst), .Q(reg3_tri));\\\\n\\\\ttri_buf buf3(.a(reg3_tri), .b(bus), .enable(out_reg[3]));\\\\n\\\\n\\\\tsixteen_bit_register reg4 (.D(bus), .enable(in_reg[4]), .clk(clk), .rst(rst), .Q(reg4_tri));\\\\n\\\\ttri_buf buf4(.a(reg4_tri), .b(bus), .enable(out_reg[4]));\\\\n\\\\n\\\\tsixteen_bit_register reg5 (.D(bus), .enable(in_reg[5]), .clk(clk), .rst(rst), .Q(reg5_tri));\\\\n\\\\ttri_buf buf5(.a(reg5_tri), .b(bus), .enable(out_reg[5]));\\\\n\\\\n\\\\tsixteen_bit_register reg6 (.D(bus), .enable(in_reg[6]), .clk(clk), .rst(rst), .Q(reg6_tri));\\\\n\\\\ttri_buf buf6(.a(reg6_tri), .b(bus), .enable(out_reg[6]));\\\\n\\\\n\\\\tsixteen_bit_register reg7 (.D(bus), .enable(in_reg[7]), .clk(clk), .rst(rst), .Q(reg7_tri));\\\\n\\\\ttri_buf buf7(.a(reg7_tri), .b(bus), .enable(out_reg[7]));\\\\n\\\\n\\\\t// ADDITIONAL REGISTERS\\\\n\\\\tsixteen_bit_register regA (.D(bus), .clk(clk), .enable(Ain), .rst(rst), .Q(regA_output));\\\\n\\\\n\\\\tALU calculator(.clk(clk), .A(regA_output), .B(bus), .instr(instruction), .result(result));\\\\n\\\\n\\\\tsixteen_bit_register regG (.D(result), .clk(clk), .enable(Gin), .rst(rst), .Q(regG_tri));\\\\n\\\\ttri_buf bufG(.a(regG_tri), .b(bus), .enable(Gout));\\\\n\\\\ttri_buf bufData(.a(data_var), .b(bus), .enable(data));\\\\n\\\\n\\\\nendmodule']
["module multdiv(data_operandA, data_operandB, ctrl_MULT, ctrl_DIV, clock, data_result, data_exception, data_resultRDY);\\\\n input [31:0] data_operandA, data_operandB;\\\\n input ctrl_MULT, ctrl_DIV, clock;\\\\n\\\\n output [31:0] data_result;\\\\n output data_exception, data_resultRDY;\\\\t\\\\n\\\\t\\\\n\\\\twire mult_adder_en, mult_adder_sub, buffer_bit, product_enable, count_enable, exception, sign, en_int_1, en_int_2,\\\\n\\\\t\\\\t\\\\tisZeroA, isZeroB, noZero, notStateEn, n_enable, isMaxA, isMaxB, maxOverflow, exception1, state_enable, state,\\\\n\\\\t\\\\t\\\\tnotState, rqb_enable, adderSub, gt_or_et, div_exception;\\\\n\\\\twire [63:0] product_in, product_out, product_unshifted, product_shifted, rqb_unshifted, rqb_shifted;\\\\n\\\\twire [31:0] adderOut, shifted_product_anded, shifted_product_ored, adderIn, rqb_in, p_in, rqbr, inverted_a, inverted_b, \\\\n\\\\t\\\\t\\\\t\\\\t\\\\tin_a, in_b, uninverted_div_out, div_out;\\\\n\\\\twire [5:0] count, countIncremented, notCount;\\\\n\\\\t\\\\n\\\\t\\\\n\\\\t\\\\n\\\\t\\\\n\\\\t\\\\n\\\\t// Make inputs positive for div, invert final product if necessary\\\\n\\\\tinverter32Mult inva(inverted_a, data_operandA, data_operandA[31]);\\\\n\\\\tinverter32Mult invb(inverted_b, data_operandB, data_operandB[31]);\\\\n\\\\tinverter32Mult invp(uninverted_div_out, rqb_shifted[31:0], sign);\\\\n\\\\t\\\\t\\\\t\\\\t\\\\n\\\\t// Chooses inputs based on mult or div\\\\n\\\\tmuxBusMult mina(in_a, inverted_a, data_operandA, state);\\\\n\\\\tmuxBusMult minb(in_b, inverted_b, data_operandB, state);\\\\n\\\\t\\\\t\\\\t\\\\t\\\\n\\\\t// Sets output to 0 if divisor is 0\\\\n\\\\tmuxBusMult divo(div_out, 32'h0, uninverted_div_out, isZeroB);\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\n\\\\t// Stores state as either multiplying (0) or dividing (1)\\\\n\\\\tor stateEn(state_enable, ctrl_MULT, ctrl_DIV);\\\\n\\\\tnot enInv(n_enable, state_enable);\\\\n\\\\tdflipflopMult storeState(ctrl_DIV, ~clock, 1'b1, 1'b1, state_enable, state);\\\\n\\\\tnot nState(notState, state);\\\\n\\\\t\\\\t\\\\n\\\\t// Exception checking\\\\n\\\\txor excxor (sign, data_operandA[31], data_operandB[31]); \\\\t// Sign is 1 if negative, 0 if positive\\\\n\\\\txor excand (exception, sign, data_result[31]);\\\\n\\\\tcheckIfZeroMult checkA(isZeroA, data_operandA);\\\\n\\\\tcheckIfZeroMult checkB(isZeroB, data_operandB);\\\\n\\\\tisMaxMult checkMaxA(isMaxA, data_operandA);\\\\n\\\\tisMaxMult checkMaxB(isMaxB, data_operandB);\\\\n\\\\tand checkMaxOver(maxOverflow, isMaxA, isMaxB, notState);\\\\n\\\\tnor checkNoZero(noZero, isZeroA, isZeroB);\\\\n\\\\tand excnot (exception1, exception, data_resultRDY, noZero, notState);\\\\t\\\\n\\\\tand divideByZero(div_exception, isZeroB, state);\\\\n\\\\tor exor(data_exception, exception1, maxOverflow, div_exception);\\\\t\\\\n\\\\t\\\\n\\\\t\\\\n\\\\t// Counts to 31, sets result ready\\\\n\\\\tnot notCo[5:0](notCount, count);\\\\n\\\\tnot outRDY(data_resultRDY, count_enable);\\\\n\\\\tnand cEnable(count_enable, notCount[0], notCount[1], notCount[2], notCount[3], notCount[4], count[5]);\\\\n\\\\tincrement6bitMult incrementer(countIncremented, count);\\\\n\\\\tregister6Mult counter(count, countIncremented, state_enable, ~clock, count_enable);\\\\t// Counts every step, resets at new signal\\\\n\\\\t\\\\n\\\\t// Allows product register to change\\\\n\\\\tor pEnable(product_enable, count_enable, state_enable);\\\\n\\\\n\\\\t// For multiplication: shifting the combined adder output/product\\\\n\\\\tassign product_unshifted[63:32] = adderOut;\\\\n\\\\tassign product_unshifted[31:0] = product_out[31:0];\\\\n\\\\tshifterMult shift (product_shifted, product_unshifted);\\\\n\\\\t\\\\n\\\\t// For multiplication: initializing product if ctrl_MULT is asserted, or updating if multiplying\\\\n\\\\tand andDiv [31:0] (rqb_in, n_enable, rqb_shifted[63:32]);\\\\n\\\\tand ands1[31:0] (p_in, n_enable, product_shifted[63:32]);\\\\n\\\\tmuxBusMult orgsg(product_in[63:32], rqb_in, p_in, state);\\\\n\\\\tand ands3 [31:0] (shifted_product_anded, n_enable, product_shifted[31:0], notState);\\\\n\\\\tand ands2[31:0](shifted_product_ored, state_enable, in_a);\\\\n\\\\tand anfaf[31:0](rqbr, rqb_shifted[31:0], state, n_enable);\\\\n\\\\tor ors1 [31:0] (product_in[31:0], shifted_product_ored, shifted_product_anded, rqbr);\\\\n\\\\t\\\\n\\\\t// Wires correct result out\\\\n\\\\tmuxBusMult resultOut(data_result, div_out, product_out[31:0], state);\\\\n\\\\t\\\\n\\\\t// Sets sub and enable values for multiplication adder\\\\n\\\\txor xorE(mult_adder_en, buffer_bit, product_out[0]);\\\\n\\\\tnot notS(mult_adder_sub, buffer_bit);\\\\n\\\\tor addSub(adderSub, mult_adder_sub, state);\\\\n\\\\t\\\\n\\\\tand cond1(en_int_1, mult_adder_en, n_enable, notState);\\\\n\\\\tor cond2(en_int_2, en_int_1, state);\\\\n\\\\t\\\\n\\\\t// Stores booth buffer bit in register\\\\n\\\\tdflipflopMult bb(product_out[0], ~clock, n_enable, 1'b1, 1'b1, buffer_bit);\\\\n\\\\t\\\\n\\\\t// Product/RQB register and adder/comparator\\\\n\\\\tregister64Mult productReg(product_out, product_in, 1'b0, ~clock, product_enable);\\\\n\\\\tfull32AdderMult adder(adderOut, product_out[63:32], in_b, adderSub, en_int_2);\\\\n\\\\t\\\\t \\\\n\\\\t// Logic for greater than or equal to output of comparator\\\\n\\\\tassign gt_or_et = (~adderOut[31]) & ((product_out[63] & in_b[31]) + ((~product_out[63]) & (~in_b[31]))) +\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t((~product_out[63]) & in_b[31]);\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\n\\\\tmuxBusMult ifgtoret(rqb_unshifted[63:32], adderOut, product_out[63:32], gt_or_et);\\\\n\\\\tassign rqb_unshifted[31:0] = product_out[31:0];\\\\n\\\\t\\\\n\\\\tleftShift1Mult leftshifter(rqb_shifted, rqb_unshifted, gt_or_et);\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\n\\\\t\\\\t \\\\nendmodule", 'module shifterMult(out, in);\\\\n\\\\tinput [63:0] in;\\\\n\\\\toutput [63:0] out;\\\\n\\\\t\\\\n\\\\twire [63:0] intermediate;\\\\n\\\\t\\\\n\\\\tassign intermediate = in >>> 1;\\\\n\\\\t\\\\n\\\\tassign out[63] = intermediate[62];\\\\n\\\\tassign out[62:0] = intermediate[62:0];\\\\n\\\\t\\\\nendmodule', "module register64Mult(data_out, data_in, rst, clk, en);\\\\n\\\\tinput clk, en, rst;\\\\n\\\\tinput [63:0] data_in;\\\\n\\\\t\\\\n\\\\toutput [63:0] data_out;\\\\n\\\\t\\\\n\\\\twire reset;\\\\n\\\\t\\\\n\\\\tnot notrst(reset, rst);\\\\n\\\\t\\\\n\\\\tdflipflopMult flops [63:0] (data_in, clk, reset, 1'b1, en, data_out);\\\\n\\\\t\\\\nendmodule", "module register6Mult(data_out, data_in, rst, clk, en);\\\\n\\\\tinput clk, en, rst;\\\\n\\\\tinput [5:0] data_in;\\\\n\\\\t\\\\n\\\\toutput [5:0] data_out;\\\\n\\\\t\\\\n\\\\twire reset;\\\\n\\\\t\\\\n\\\\tnot notrst(reset, rst);\\\\n\\\\t\\\\n\\\\tdflipflopMult flops [5:0] (data_in, clk, reset, 1'b1, en, data_out);\\\\n\\\\t\\\\nendmodule", 'module muxBusMult(out, ina, inb, s);\\\\n\\\\tinput [31:0] ina, inb;\\\\n\\\\tinput s;\\\\n\\\\toutput [31:0] out;\\\\n\\\\t\\\\n\\\\tassign out = (s) ? ina : inb;\\\\n\\\\t\\\\nendmodule', 'module leftShift1Mult(out, in, lastVal);\\\\n\\\\tinput [63:0] in;\\\\n\\\\tinput lastVal;\\\\n\\\\toutput [63:0] out;\\\\n\\\\t\\\\n\\\\tassign out[63:1] = in[62:0];\\\\n\\\\tassign out[0] = lastVal;\\\\n\\\\t\\\\nendmodule', 'module isMaxMult(out, in);\\\\n\\\\tinput [31:0] in;\\\\n\\\\toutput out;\\\\n\\\\t\\\\n\\\\tassign out = ~in[31] & in[30] & in[29] & in[28] & in[27] & in[26] & in[25] & in[24] &\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t in[23] & in[22] & in[21] & in[20] & in[19] & in[18] & in[17] & in[16] &\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t in[15] & in[14] & in[13] & in[12] & in[11] & in[10] & in[9] & in[8] &\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t in[7] & in[6] & in[5] & in[4] & in[3] & in[2] & in[1] & in[0];\\\\n\\\\nendmodule', "module inverter32Mult(out, in, en);\\\\n\\\\tinput [31:0] in;\\\\n\\\\tinput en;\\\\n\\\\toutput [31:0] out;\\\\n\\\\t\\\\t\\\\n\\\\tfull32AdderMult add(out, 32'b0, in, en, 1'b1);\\\\n\\\\t\\\\nendmodule", "module increment6bitMult(s, a);\\\\n\\\\tinput [5:0] a;\\\\n\\\\twire [5:0] b;\\\\n\\\\twire c;\\\\n\\\\t\\\\n\\\\t\\\\n\\\\toutput [5:0] s;\\\\n\\\\t\\\\n\\\\tassign b = 5'b000001;\\\\n\\\\tassign c = 1'b0;\\\\n\\\\t\\\\n\\\\twire [5:0] p,g;\\\\n\\\\t\\\\n\\\\twire c1, c2, c3, c4, c5;\\\\n\\\\twire p0c, p1p0c, p1g0, p2p1p0c, p2p1g0, p2g1, p3p2p1p0c, p3p2p1g0, p3p2g1, p3g2, p4p3p2p1p0c, p4p3p2p1g0, p4p3p2g1, p4p3g2, p4g3;\\\\n\\\\t\\\\n\\\\tadderMult adder0(s[0], p[0], g[0], a[0], b[0], c);\\\\n\\\\t\\\\n\\\\tand and0(p0c, p[0], c);\\\\n\\\\tor or0(c1, p0c, g[0]);\\\\n\\\\t\\\\n\\\\tadderMult adder1(s[1], p[1], g[1], a[1], b[1], c1);\\\\n\\\\t\\\\n\\\\tand and1(p1p0c, p0c, p[1]);\\\\n\\\\tand and2(p1g0, p[1], g[0]);\\\\n\\\\tor or1(c2, g[1], p1g0, p1p0c);\\\\n\\\\t\\\\n\\\\tadderMult adder2(s[2], p[2], g[2], a[2], b[2], c2);\\\\n\\\\t\\\\n\\\\tand and3(p2p1p0c, p[2], p1p0c);\\\\n\\\\tand and4(p2p1g0, p[2], p1g0);\\\\n\\\\tand and5(p2g1, p[2], g[1]);\\\\n\\\\tor or2(c3, g[2], p2g1, p2p1g0, p2p1p0c);\\\\n\\\\t\\\\n\\\\tadderMult adder3(s[3], p[3], g[3], a[3], b[3], c3);\\\\n\\\\t\\\\n\\\\tand and6(p3p2p1p0c, p[3], p2p1p0c);\\\\n\\\\tand and7(p3p2p1g0, p[3], p2p1g0);\\\\n\\\\tand and8(p3p2g1, p[3], p2g1);\\\\n\\\\tand and9(p3g2, p[3], g[2]);\\\\n\\\\tor or3(c4, p3p2p1p0c, p3p2p1g0, p3p2g1, p3g2, g[3]);\\\\n\\\\t\\\\n\\\\tadderMult adder4(s[4], p[4], g[4], a[4], b[4], c4);\\\\n\\\\t\\\\n\\\\n\\\\tand and10(p4p3p2p1p0c, p[4], p3p2p1p0c);\\\\n\\\\tand and11(p4p3p2p1g0, p[4], p3p2p1g0);\\\\n\\\\tand and12(p4p3p2g1, p[4], p3p2g1);\\\\n\\\\tand and13(p4p3g2, p[4], p3g2);\\\\n\\\\tand and14(p4g3, p[4], g[3]);\\\\n\\\\tor or4(c5, p4p3p2p1p0c, p4p3p2p1g0, p4p3p2g1, p4p3g2, p4g3, g[4]);\\\\n\\\\t\\\\n\\\\tadderMult adder5(s[5], p[5], g[5], a[5], b[5], c5);\\\\n\\\\t\\\\nendmodule", 'module full32AdderMult(out, a, b, sub, en);\\\\n\\\\t\\\\n\\\\tinput [31:0] a, b;\\\\n\\\\tinput sub, en;\\\\n\\\\toutput [31:0] out;\\\\n\\\\n\\\\twire [3:0] G, P;\\\\n\\\\twire [31:0] bin, bin1;\\\\n\\\\twire c8, c16, c24, c32, P0c, P1G0, P1P0c, P2G1, P2P1G0, P2P1P0c, P3G2, P3P2G1, P3P2P1G0, P3P2P1P0c, notA, notB, notC;\\\\n\\\\twire over1, over2, over3, notSub, subin;\\\\n\\\\t\\\\n\\\\tand(subin, sub, en);\\\\n\\\\t\\\\n\\\\txor xorB [31:0] (bin1, b, subin);\\\\n\\\\t\\\\n\\\\tand andB [31:0] (bin, bin1, en);\\\\n\\\\t\\\\n\\\\tcla8BlockMult cla8Block0(out[7:0], G[0], P[0], a[7:0], bin[7:0], subin);\\\\n\\\\t\\\\n\\\\tand and0(P0c, P[0], subin);\\\\n\\\\tor or0(c8, G[0], P0c);\\\\n\\\\t\\\\n\\\\tcla8BlockMult cla8Block1(out[15:8], G[1], P[1], a[15:8], bin[15:8], c8);\\\\n\\\\t\\\\n\\\\tand and1(P1P0c, P[1], P0c);\\\\n\\\\tand and2(P1G0, P[1], G[0]);\\\\n\\\\tor or1(c16, G[1], P1G0, P1P0c);\\\\n\\\\t\\\\n\\\\tcla8BlockMult cla8Block2(out[23:16], G[2], P[2], a[23:16], bin[23:16], c16);\\\\n\\\\t\\\\n\\\\tand and3(P2P1P0c, P[2], P1P0c);\\\\n\\\\tand and4(P2P1G0, P[2], P1G0);\\\\n\\\\tand and5(P2G1, P[2], G[1]);\\\\n\\\\tor or2(c24, G[2], P2G1, P2P1G0, P2P1P0c);\\\\n\\\\t\\\\n\\\\tcla8BlockMult cla8Block3(out[31:24], G[3], P[3], a[31:24], bin[31:24], c24);\\\\n\\\\t\\\\n\\\\t\\\\nendmodule', "module dflipflopMult(d, clk, clrn, prn, ena, q);\\\\n input d, clk, ena, clrn, prn;\\\\n wire clr;\\\\n wire pr;\\\\n\\\\n output q;\\\\n reg q;\\\\n\\\\n assign clr = ~clrn;\\\\n assign pr = ~prn;\\\\n\\\\n initial\\\\n begin\\\\n q = 1'b0;\\\\n end\\\\n\\\\n always @(posedge clk) begin\\\\n if (q == 1'bx) begin\\\\n q <= 1'b0;\\\\n end else if (clr) begin\\\\n q <= 1'b0;\\\\n end else if (ena) begin\\\\n q <= d;\\\\n end\\\\n end\\\\nendmodule", 'module cla8BlockMult(s, bigG, bigP, a, b, c);\\\\n\\\\tinput [7:0] a, b;\\\\n\\\\tinput c;\\\\n\\\\toutput [7:0] s;\\\\n\\\\toutput bigG, bigP;\\\\n\\\\twire p0c, c1, c2, c3, c4, c5, c6, c7, p1p0c, p1g0, p2p1p0c, p2p1g0, p2g1, p3p2p1p0c, p3p2p1g0, p3p2g1, p3g2;\\\\n\\\\twire p4p3p2p1p0c, p4p3p2p1g0, p4p3p2g1, p4p3g2, p4g3, p5p4p3p2p1p0c, p5p4p3p2p1g0, p5p4p3p2g1, p5p4p3g2, p5p4g3, p5g4;\\\\n\\\\twire p6p5p4p3p2p1p0c, p6p5p4p3p2p1g0, p6p5p4p3p2g1, p6p5p4p3g2, p6p5p4g3, p6p5g4, p6g5, p7g6;\\\\n\\\\twire p7p6p5p4p3p2p1g0, p7p6p5p4p3p2g1, p7p6p5p4p3g2, p7p6p5p4g3, p7p6p5g4, p7p6g5;\\\\n\\\\twire [7:0] g, p;\\\\n\\\\t\\\\n\\\\tadderMult adder0(s[0], p[0], g[0], a[0], b[0], c);\\\\n\\\\t\\\\n\\\\tand and0(p0c, p[0], c);\\\\n\\\\tor or0(c1, p0c, g[0]);\\\\n\\\\t\\\\n\\\\tadderMult adder1(s[1], p[1], g[1], a[1], b[1], c1);\\\\n\\\\t\\\\n\\\\tand and1(p1p0c, p0c, p[1]);\\\\n\\\\tand and2(p1g0, p[1], g[0]);\\\\n\\\\tor or1(c2, g[1], p1g0, p1p0c);\\\\n\\\\t\\\\n\\\\tadderMult adder2(s[2], p[2], g[2], a[2], b[2], c2);\\\\n\\\\t\\\\n\\\\tand and3(p2p1p0c, p[2], p1p0c);\\\\n\\\\tand and4(p2p1g0, p[2], p1g0);\\\\n\\\\tand and5(p2g1, p[2], g[1]);\\\\n\\\\tor or2(c3, g[2], p2g1, p2p1g0, p2p1p0c);\\\\n\\\\t\\\\n\\\\tadderMult adder3(s[3], p[3], g[3], a[3], b[3], c3);\\\\n\\\\t\\\\n\\\\tand and6(p3p2p1p0c, p[3], p2p1p0c);\\\\n\\\\tand and7(p3p2p1g0, p[3], p2p1g0);\\\\n\\\\tand and8(p3p2g1, p[3], p2g1);\\\\n\\\\tand and9(p3g2, p[3], g[2]);\\\\n\\\\tor or3(c4, p3p2p1p0c, p3p2p1g0, p3p2g1, p3g2, g[3]);\\\\n\\\\t\\\\n\\\\tadderMult adder4(s[4], p[4], g[4], a[4], b[4], c4);\\\\n\\\\t\\\\n\\\\tand and10(p4p3p2p1p0c, p[4], p3p2p1p0c);\\\\n\\\\tand and11(p4p3p2p1g0, p[4], p3p2p1g0);\\\\n\\\\tand and12(p4p3p2g1, p[4], p3p2g1);\\\\n\\\\tand and13(p4p3g2, p[4], p3g2);\\\\n\\\\tand and14(p4g3, p[4], g[3]);\\\\n\\\\tor or4(c5, p4p3p2p1p0c, p4p3p2p1g0, p4p3p2g1, p4p3g2, p4g3, g[4]);\\\\n\\\\t\\\\n\\\\tadderMult adder5(s[5], p[5], g[5], a[5], b[5], c5);\\\\n\\\\t\\\\n\\\\tand and15(p5p4p3p2p1p0c, p[5], p4p3p2p1p0c);\\\\n\\\\tand and16(p5p4p3p2p1g0, p[5], p4p3p2p1g0);\\\\n\\\\tand and17(p5p4p3p2g1, p[5], p4p3p2g1);\\\\n\\\\tand and18(p5p4p3g2, p[5], p4p3g2);\\\\n\\\\tand and19(p5p4g3, p[5], p4g3);\\\\n\\\\tand and20(p5g4, p[5], g[4]);\\\\n\\\\tor or5(c6, p5p4p3p2p1p0c, p5p4p3p2p1g0, p5p4p3p2g1, p5p4p3g2, p5p4g3, p5g4, g[5]);\\\\n\\\\t\\\\n\\\\tadderMult adder6(s[6], p[6], g[6], a[6], b[6], c6);\\\\n\\\\t\\\\n\\\\tand and21(p6p5p4p3p2p1p0c, p[6], p5p4p3p2p1p0c);\\\\n\\\\tand and22(p6p5p4p3p2p1g0, p[6], p5p4p3p2p1g0);\\\\n\\\\tand and23(p6p5p4p3p2g1, p[6], p5p4p3p2g1);\\\\n\\\\tand and24(p6p5p4p3g2, p[6], p5p4p3g2);\\\\n\\\\tand and25(p6p5p4g3, p[6], p5p4g3);\\\\n\\\\tand and26(p6p5g4, p[6], p5g4);\\\\n\\\\tand and27(p6g5, p[6], g[5]);\\\\n\\\\tor or6(c7, p6p5p4p3p2p1p0c, p6p5p4p3p2p1g0, p6p5p4p3p2g1, p6p5p4p3g2, p6p5p4g3, p6p5g4, p6g5, g[6]);\\\\n\\\\t\\\\n\\\\tadderMult adder7(s[7], p[7], g[7], a[7], b[7], c7);\\\\n\\\\t\\\\n\\\\tand and28(bigP, p[7], p[6], p[5], p[4], p[3], p[2], p[1], p[0]);\\\\n\\\\t\\\\n\\\\tand and29(p7p6p5p4p3p2p1g0, p[7], p6p5p4p3p2p1g0);\\\\n\\\\tand and30(p7p6p5p4p3p2g1, p[7], p6p5p4p3p2g1);\\\\n\\\\tand and31(p7p6p5p4p3g2, p[7], p6p5p4p3g2);\\\\n\\\\tand and32(p7p6p5p4g3, p[7], p6p5p4g3);\\\\n\\\\tand and33(p7p6p5g4, p[7], p6p5g4);\\\\n\\\\tand and34(p7p6g5, p[7], p6g5);\\\\n\\\\tand and35(p7g6, p[7], g[6]);\\\\n\\\\tor or7(bigG, g[7], p7g6, p7p6g5, p7p6p5g4, p7p6p5p4g3, p7p6p5p4p3g2, p7p6p5p4p3p2g1, p7p6p5p4p3p2p1g0);\\\\n\\\\t\\\\nendmodule', 'module checkIfZeroMult(out, in);\\\\n\\\\tinput [31:0] in;\\\\n\\\\toutput out;\\\\n\\\\t\\\\n\\\\tnor check(out, in[0], in[1], in[2], in[3], in[4], in[5], in[6], in[7], \\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tin[8], in[9], in[10],in[11],in[12],in[13],in[14],in[15],\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tin[16],in[17],in[18],in[19],in[20],in[21],in[22],in[23],\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tin[24],in[25],in[26],in[27],in[28],in[29],in[30],in[31]);\\\\n\\\\t\\\\nendmodule', 'module adderMult(out, p, g, a, b, cin);\\\\n\\\\tinput a, b, cin;\\\\n\\\\toutput out, p, g;\\\\n\\\\t\\\\n\\\\txor outxor(out, a, b, cin);\\\\n\\\\tand andg(g, a, b);\\\\n\\\\tor orp(p, a, b);\\\\n\\\\t\\\\nendmodule']
['module datapath(\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tinput [7:0]Q,\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tinput [7:0]M,\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tinput mux_e,\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tinput clr,\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tinput clk,\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tinput ld,\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tinput sh,\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\toutput done,\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\toutput [16:0]Sh_out);\\\\n\\\\nwire [16:0]in1_mux1;\\\\nwire [16:0]shift_out;\\\\nwire [7:0]mux_169;\\\\n\\\\nassign in1_mux1[0] = 0;\\\\nassign in1_mux1[8:1]=Q;\\\\nassign in1_mux1[16:9]=0;\\\\n\\\\nwire [16:0]in0_mux1;\\\\nassign in0_mux1[8:0] = shift_out[8:0];\\\\nassign in0_mux1[16:9] = mux_169;\\\\n\\\\nwire [16:0]mux1_out;\\\\n\\\\nassign mux1_out = (mux_e)?in1_mux1:in0_mux1;\\\\n\\\\nshiftreg shi(.clk(clk),.rst(clr),.load(ld),.data(mux1_out),.shren(sh),.din(mux1_out[16]),.dout(shift_out));\\\\n\\\\nwire don;\\\\nwire [4:0]sum_count;\\\\nwire [4:0]D_count;\\\\nreg [4:0]Q_count;\\\\nwire en;\\\\nassign en = ~don;\\\\n\\\\nassign D_count = Q_count +1;\\\\nassign don = (Q_count==19)?1:0;\\\\n\\\\nalways @ (posedge clk)\\\\n\\\\tif(en)\\\\n\\\\t\\\\tQ_count<=D_count;\\\\n\\\\telse\\\\n\\\\t\\\\tQ_count <= Q_count;\\\\n\\\\nassign done = don;\\\\n\\\\nreg [16:0]Q_shift;\\\\n\\\\nalways @ (posedge clk)\\\\nbegin\\\\n\\\\tif(en)\\\\n\\\\t\\\\tQ_shift <= shift_out;\\\\nend\\\\nassign done = don;\\\\nassign Sh_out = Q_shift;\\\\n\\\\nwire [7:0]sum1;\\\\nassign sum1 = ~M +1;\\\\nwire [7:0]mux1_Sum;\\\\nassign mux1_Sum = (shift_out[1])?sum1:M;\\\\nwire [7:0]sum2;\\\\nassign sum2 = mux1_Sum + shift_out[16:9];\\\\n\\\\nwire xor_out;\\\\nassign xor_out = shift_out[1] | shift_out[0];\\\\n\\\\n\\\\nassign mux_169 = (xor_out)?sum2 : shift_out[16:9];\\\\n\\\\n\\\\n\\\\n\\\\nendmodule']
["module mul_main(a,b,m,overflow,underflow);\\\\ninput[31:0] a,b;\\\\noutput reg[31:0] m;\\\\noutput reg overflow,underflow;\\\\nwire[8:0] exp_o,newexp;\\\\nwire[7:0] expo_r;\\\\nwire[48:0] mul_o;\\\\nwire[4:0] normalize_o;\\\\nwire[23:0] dinhtri_o;\\\\nwire[22:0] dinhtri_r;\\\\nwire c1,c3,s1;\\\\nwire[1:0] c2,c4;\\\\nadd_exp u1({1'b0,a[30:23]},{1'b0,b[30:23]},exp_o);\\\\nadd_mul u2({1'b1,a[22:0]},{1'b1,b[22:0]},mul_o);\\\\nnormalize u3(mul_o[48:25],normalize_o);\\\\nnormalizeExpo u4(normalize_o,exp_o,newexp);\\\\nnormalizeFrac u5(normalize_o,mul_o[48:25],dinhtri_o);\\\\nRounding u7(dinhtri_o[22:0],newexp[7:0],dinhtri_r,expo_r);\\\\ncheck0 kt0(a[30:23],c1);\\\\ncheckinf ktinf(a[30:23],a[22:0],c2);\\\\ncheck0 kt0_2(b[30:23],c3);\\\\ncheckinf ktinf_2(b[30:23],b[22:0],c4);\\\\nxor(s1,a[31],b[31]);\\\\nalways @(c1 or c2 or c3 or c4 or s1 or expo_r or dinhtri_r)\\\\nbegin\\\\ncase({c1,c2,c3,c4}) \\\\n 7'b100000: begin m = 31'b0; end\\\\n 7'b000100: begin m = 31'b0; end\\\\n 7'b011000: begin m = 31'bx; end\\\\n 7'b001000: begin m = 31'bx; end\\\\n 7'b000011: begin m = 31'bx; end\\\\n 7'b000001: begin m = 31'bx; end\\\\n 7'b100100: begin m = 31'b0; end\\\\n 7'b011011: begin m = 31'bx; end\\\\n 7'b001001: begin m = 31'bx; end\\\\n 7'b110010: begin m = 31'b0; end \\\\n 7'b010110: begin m = 31'b0; end\\\\n 7'b110110: begin m = 31'b0; end \\\\n 7'b110000: begin m = 31'b0; end \\\\n 7'b000110: begin m = 31'b0; end\\\\n 7'b110100: begin m = 31'b0; end \\\\n 7'b100010: begin m = 31'b0; end \\\\n 7'b010100: begin m = 31'b0; end\\\\n 7'b100110: begin m = 31'b0; end \\\\n default: \\\\n begin \\\\n if(newexp<9'd0)\\\\n\\\\t begin\\\\n\\\\t underflow = 1'b1;\\\\n\\\\t overflow = 1'b0;\\\\n\\\\t m = 31'bx;\\\\n\\\\t end\\\\n\\\\t else if(newexp>9'd254)\\\\n\\\\t begin\\\\n\\\\t underflow = 1'b0;\\\\n\\\\t overflow = 1'b1;\\\\n\\\\t m = 31'bx;\\\\n\\\\t end\\\\n\\\\t else\\\\n\\\\t begin\\\\n\\\\t underflow = 1'b0;\\\\n\\\\t overflow = 1'b0;\\\\n\\\\t m = {s1,expo_r,dinhtri_r};\\\\n\\\\t end\\\\n end\\\\n endcase\\\\nend\\\\nendmodule"]
["module loadValDatapath(first_letter, second_letter, third_letter, fourth_letter, fifth_letter, sixth_letter, seventh_letter, eighth_letter, ninth_letter, tenth_letter, letterNum, clock, reset_n, enable, col_out, X, Y, done);\\\\n input [7:0]first_letter; \\\\n input [7:0]second_letter; \\\\n input [7:0]third_letter; \\\\n input [7:0]fourth_letter; \\\\n input [7:0]fifth_letter;\\\\n input [7:0]sixth_letter; \\\\n input [7:0]seventh_letter;\\\\n input [7:0]eighth_letter;\\\\n input [7:0]ninth_letter;\\\\n input [7:0]tenth_letter;\\\\n\\\\tinput reset_n, enable, clock;\\\\n\\\\toutput done;\\\\n\\\\toutput [6:0] X, Y; // location out\\\\n\\\\tinput [3:0] letterNum;\\\\n\\\\t\\\\n\\\\t\\\\n // cover \\\\n\\\\treg [8:0] q; // 0-328 draw black, 329 - 368 draw underlines, 369 - 529 draw letters, 480 - 496 draw box\\\\n\\\\t reg [6:0] px;\\\\n\\\\t reg [6:0] py;\\\\n\\\\toutput reg [2:0] col_out;\\\\n\\\\twire drawImage; \\\\n\\\\twire [6:0] drawAllLetterX, drawAllLetterY;\\\\n\\\\twire [6:0] drawX, drawY;\\\\n\\\\t\\\\n\\\\tdrawAllLetters dr(first_letter, second_letter, third_letter, fourth_letter, fifth_letter, sixth_letter, seventh_letter, eighth_letter, ninth_letter, tenth_letter, q-9'd386, drawAllLetterX,drawAllLetterY);\\\\n\\\\tdraw dr1(60-40+letterNum*4, 100, 1, 5'd32, q-5'd368 , drawX, drawY);\\\\n\\\\n\\\\talways @(posedge clock)\\\\n\\\\tbegin\\\\n\\\\t\\\\tif (reset_n == 1'b0)\\\\n\\\\t\\\\t\\\\tq <= 0;\\\\n\\\\t\\\\telse if (enable == 1'b1)\\\\n\\\\t\\\\t\\\\tq <= q + 1'b1;\\\\n\\\\t\\\\t\\\\n\\\\tend\\\\n\\\\n\\\\talways @(*)\\\\n\\\\tbegin\\\\n\\\\t\\\\tif (reset_n == 1'b0)\\\\n\\\\t\\\\t\\\\tq <= 0;\\\\n\\\\t\\\\telse if (enable == 1'b1) begin\\\\n\\\\t\\\\t\\\\tif (q < 10'd328) // black out everything drawn before\\\\n\\\\t\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tcol_out <= 3'b000;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tpy <= q[2:0];\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tpx <= q[8:3];\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\telse if (q <= 10'd368)\\\\n\\\\t\\\\t\\\\t\\\\tbegin\\\\t\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tpy <= 100;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tpx <= q - 329 + 60 - 40;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\n\\\\t\\\\t\\\\t\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tif (q[2:0] == 4)\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tcol_out <= 3'b111;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\telse\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tcol_out <= 3'b000;\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t\\\\n\\\\t\\\\t\\\\telse if (q <= 10'd385) begin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\n\\\\t\\\\t\\\\t\\\\t \\\\n\\\\t\\\\t\\\\t\\\\tcol_out <= 3'b000;\\\\n\\\\t\\\\t\\\\t\\\\tpx <= drawX;\\\\n\\\\t\\\\t\\\\t\\\\tpy <= drawY;\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t\\\\t\\\\n\\\\t\\\\t\\\\telse if (q <= 10'd550) begin\\\\n\\\\t\\\\t\\\\t\\\\tcol_out <= 3'b000;\\\\n\\\\t\\\\t\\\\t\\\\tpx <= drawAllLetterX;\\\\n\\\\t\\\\t\\\\t\\\\tpy <= drawAllLetterY;\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\tend\\\\n\\\\tend\\\\n\\\\n\\\\t\\\\n\\\\tassign X = px; //q1;\\\\n\\\\tassign Y = py; //q2;\\\\n\\\\tassign done = (q == 10'd550) ? 1 : 0;\\\\nendmodule", "module drawAllLetters(first_letter, second_letter, third_letter, fourth_letter, fifth_letter, sixth_letter, seventh_letter, eighth_letter, ninth_letter, tenth_letter, counter, ox, oy);\\\\n input [7:0]first_letter; \\\\n input [7:0]second_letter; \\\\n input [7:0]third_letter; \\\\n input [7:0]fourth_letter; \\\\n input [7:0]fifth_letter;\\\\n input [7:0]sixth_letter; \\\\n input [7:0]seventh_letter;\\\\n input [7:0]eighth_letter;\\\\n input [7:0]ninth_letter;\\\\n input [7:0]tenth_letter;\\\\n input [8:0]counter;\\\\n wire [6:0] x1 ,x2 , x3 , x4 , x5 , x6 , x7 , x8 , x9 , x10;\\\\n wire [6:0] y1 , y2 ,y3, y4, y5, y6, y7, y8, y9, y10;\\\\n\\\\n draw dr_1(q - 329 + 60, 100+6, 1, first_letter, counter[3:0], x1, y1);\\\\n draw dr_2(q - 329 + 60, 100+6, 1, second_letter, counter[3:0] , x2, y2);\\\\n draw dr_3(q - 329 + 60, 100+6, 1, third_letter, counter[3:0] , x3, y3);\\\\n draw dr_4(q - 329 + 60, 100+6, 1, fourth_letter, counter[3:0] , x4, y4);\\\\n draw dr_5(q - 329 + 60, 100+6, 1, fifth_letter, counter[3:0] , x5, y5);\\\\n draw dr_6(q - 329 + 60, 100+6, 1, sixth_letter, counter[3:0] , x6, y6);\\\\n draw dr_7(q - 329 + 60, 100+6, 1, seventh_letter, counter[3:0] , x7, y7);\\\\n draw dr_8(q - 329 + 60, 100+6, 1, eighth_letter, counter[3:0] , x8, y8);\\\\n draw dr_9(q - 329 + 60, 100+6, 1, ninth_letter, counter[3:0] , x9, y9);\\\\n draw dr_10(q - 329 + 60, 100+6, 1, tenth_letter, counter[3:0] , x10, y10);\\\\n\\\\n output reg [6:0] ox, oy;\\\\n\\\\n always @(*)\\\\n case (counter[8:4])\\\\n 4'b0000: begin\\\\n ox <= x1;\\\\n oy <= y1;\\\\n end\\\\n 4'b0001: begin\\\\n ox <= x2;\\\\n oy <= y2;\\\\n end\\\\n 4'b0010: begin\\\\n ox <= x3;\\\\n oy <= y3;\\\\n end\\\\n 4'b0011: begin\\\\n ox <= x4;\\\\n oy <= y4;\\\\n end\\\\n 4'b0100: begin\\\\n ox <= x5;\\\\n oy <= y5;\\\\n end\\\\n 4'b0101: begin\\\\n ox <= x6;\\\\n oy <= y6;\\\\n end\\\\n 4'b0110: begin\\\\n ox <= x7;\\\\n oy <= y7;\\\\n end\\\\n 4'b0111: begin\\\\n ox <= x8;\\\\n oy <= y8;\\\\n end\\\\n 4'b1000: begin\\\\n ox <= x9;\\\\n oy <= y9;\\\\n end\\\\n 4'b1001: begin\\\\n ox <= x10;\\\\n oy <= y10;\\\\n end\\\\n endcase\\\\n\\\\nendmodule"]
["module test_hvsync_top(clk, reset, hsync, vsync, rgb, switches_p1);\\\\n\\\\n input clk, reset;\\\\t// clock and reset signals (input)\\\\n input [7:0] switches_p1;\\\\n output hsync, vsync;\\\\t// H/V sync signals (output)\\\\n output [2:0] rgb;\\\\t// RGB output (BGR order)\\\\n wire display_on;\\\\t// display_on signal\\\\n wire [8:0] hpos;\\\\t// 9-bit horizontal position\\\\n wire [8:0] vpos;\\\\t// 9-bit vertical position\\\\n\\\\n wire playfield_gfx;\\\\n reg [15:0] maze [0:27];\\\\n wire [3:0] x = hpos[6:3];\\\\n wire [4:0] y = vpos[7:3] - 2;\\\\n assign playfield_gfx = maze[y][x];\\\\n \\\\n initial begin\\\\n maze[0] = 16'b1111111111111111;\\\\n maze[1] = 16'b1000000000000001;\\\\n maze[2] = 16'b1000000000000001;\\\\n maze[3] = 16'b1000000000000001;\\\\n maze[4] = 16'b1000000000000001;\\\\n maze[5] = 16'b1000000000000001;\\\\n maze[6] = 16'b1000000000000001;\\\\n maze[7] = 16'b1000000000000001;\\\\n maze[8] = 16'b1000000000000001;\\\\n maze[9] = 16'b1000000000000001;\\\\n maze[10] = 16'b1000000000000001;\\\\n maze[11] = 16'b1000000000000001;\\\\n maze[12] = 16'b1000000000000001;\\\\n maze[13] = 16'b1000000000000001;\\\\n maze[14] = 16'b1000000000000001;\\\\n maze[15] = 16'b1000000000000001;\\\\n maze[16] = 16'b1000000000000001;\\\\n maze[17] = 16'b1000000000000001;\\\\n maze[18] = 16'b1000000000000001;\\\\n maze[19] = 16'b1000000000000001;\\\\n maze[20] = 16'b1000000000000001;\\\\n maze[21] = 16'b1000000000000001;\\\\n maze[22] = 16'b1000000000000001;\\\\n maze[23] = 16'b1000000000000001;\\\\n maze[24] = 16'b1000000000000001;\\\\n maze[25] = 16'b1000000000000001;\\\\n maze[26] = 16'b1000000000000001;\\\\n maze[27] = 16'b1111111111111111;\\\\n end\\\\n \\\\n`define CMDWIDTH 8\\\\n`define PROGRAMSIZE 1024\\\\n\\\\n`define INIT 0\\\\n`define MOVL 1\\\\n`define MOVR 2\\\\n`define FIRE 3\\\\n`define UP 4\\\\n`define DEL 5\\\\n`define JMP 6\\\\n\\\\n\\\\n`define DEF_MAZE 16'b1000000000000001\\\\n\\\\nreg [$clog2(`PROGRAMSIZE) - 1 : 0] pc, new_pc;\\\\nreg [`CMDWIDTH - 1 : 0] Program [0 : `PROGRAMSIZE - 1];\\\\n\\\\nwire [3:0] command_current;\\\\nassign command_current = Program[pc][7:4];\\\\nwire [3:0] op;\\\\nassign op = Program[pc][3:0];\\\\n\\\\n\\\\n \\\\nreg fire;\\\\nreg del;\\\\nreg sync;\\\\nreg fire_l;\\\\nreg [4:0] left_pos;\\\\nreg [3:0] dota2;\\\\nreg [19:0] divider;\\\\nreg [15:0] ship [0:2];\\\\n\\\\ninteger i, fire_reload;\\\\n \\\\ninitial\\\\nbegin\\\\n fire_reload = 0;\\\\n new_pc = 0;\\\\n pc = 0;\\\\t\\\\n // \\\\u0418\\\\u043d\\\\u0438\\\\u0446\\\\u0438\\\\u0430\\\\u043b\\\\u0438\\\\u0437\\\\u0430\\\\u0446\\\\u0438\\\\u044f \\\\u043f\\\\u0430\\\\u043c\\\\u044f\\\\u0442\\\\u0438 \\\\u043f\\\\u0440\\\\u043e\\\\u0433\\\\u0440\\\\u0430\\\\u043c\\\\u043c\\\\u044b\\\\n for(i = 0; i < `PROGRAMSIZE; i = i + 1)\\\\n Program[i] = 8'b00000000;\\\\n Program[0] = 8'h00; // INIT\\\\n Program[1] = 8'h10; // MOVL\\\\n Program[2] = 8'h20; // MOVR\\\\n Program[3] = 8'h30; // FIRE\\\\n Program[4] = 8'h40; // UP\\\\n Program[5] = 8'h50; // DEL\\\\n Program[6] = 8'h61; // JMP 1\\\\t\\\\nend\\\\t\\\\n\\\\n \\\\n//\\\\u041e\\\\u043f\\\\u0440\\\\u0435\\\\u0434\\\\u0435\\\\u043b\\\\u0435\\\\u043d\\\\u0438\\\\u0435 \\\\u043b\\\\u043e\\\\u0433\\\\u0438\\\\u043a\\\\u0438 \\\\u0443\\\\u0441\\\\u0442\\\\u0430\\\\u043d\\\\u043e\\\\u0432\\\\u043a\\\\u0438 \\\\u0444\\\\u043b\\\\u0430\\\\u0433\\\\u043e\\\\u0432\\\\nalways@(posedge clk) \\\\nbegin\\\\n divider <= divider + 1;\\\\n if (divider == 20'b10000000000000000000) begin\\\\n sync <= 1;\\\\n if (fire_reload < 5) begin\\\\n fire_reload <= fire_reload + 1;\\\\n end\\\\n else begin\\\\n fire <= 1;\\\\n fire_reload <= 0;\\\\n end\\\\n end\\\\nend\\\\n \\\\n\\\\n \\\\n initial begin\\\\n fire_l = 1;\\\\n left_pos = 6;\\\\n del = 0;\\\\n ship[0] = 16'b1000000110000001;\\\\n ship[1] = 16'b1000001111000001;\\\\n ship[2] = 16'b1000001001000001;\\\\n end\\\\n \\\\n\\\\n \\\\n always@(posedge clk) begin\\\\n case(command_current)\\\\n `INIT: begin // \\\\u0418\\\\u043d\\\\u0438\\\\u0446\\\\u0438\\\\u0430\\\\u043b\\\\u0438\\\\u0437\\\\u0430\\\\u0446\\\\u0438\\\\u044f \\\\u043d\\\\u0430\\\\u0448\\\\u0435\\\\u0433\\\\u043e \\\\u043a\\\\u043e\\\\u0440\\\\u0430\\\\u0431\\\\u043b\\\\u044f \\\\u0438 \\\\u043a\\\\u043e\\\\u0440\\\\u0430\\\\u0431\\\\u043b\\\\u044f \\\\u0432\\\\u0440\\\\u0430\\\\u0433\\\\u0430\\\\n if (switches_p1[4]) begin\\\\n maze[1] <= ship[0];\\\\n maze[2] <= ship[0];\\\\n maze[3] <= ship[1];\\\\n maze[4] <= ship[2];\\\\n maze[5] <= ship[2];\\\\n maze[23] <= 16'b1000000110000001;\\\\n maze[24] <= 16'b1000001111000001;\\\\n maze[25] <= 16'b1000001001000001;\\\\n pc <= pc + 1;\\\\n end\\\\n end \\\\n\\\\n `FIRE: begin // \\\\u0412\\\\u044b\\\\u043f\\\\u0443\\\\u0441\\\\u043a \\\\u0441\\\\u043d\\\\u0430\\\\u0440\\\\u044f\\\\u0434\\\\u0430\\\\n if (switches_p1[2] && fire)\\\\n if (fire_l) begin\\\\n maze[22][left_pos + 1] <= 1;\\\\n fire_l <= 0;\\\\n fire <= 0;\\\\n end\\\\n else begin\\\\n maze[22][left_pos + 2] <= 1;\\\\n fire_l <= 1;\\\\n fire <= 0;\\\\n end\\\\n pc <= pc + 1;\\\\n end\\\\n\\\\n `UP: begin // \\\\u0414\\\\u0432\\\\u0438\\\\u0436\\\\u0435\\\\u043d\\\\u0438\\\\u0435 \\\\u0441\\\\u043d\\\\u0430\\\\u0440\\\\u044f\\\\u0434\\\\u0430\\\\n if (sync) begin\\\\n maze[6:21] <= maze[7:22];\\\\n maze[22] <= 16'b1000000000000001;\\\\n if (!del && ((maze[5][9:6] & maze[6][9:6] ) != 4'b0000))\\\\n del <= 1;\\\\n maze[5] <= maze[6] | ship[2];\\\\n maze[4] <= maze[5] | ship[2];\\\\n if (!del && ((maze[4][9:6] & maze[3][9:6]) != ship[2][9:6]))\\\\n del <= 1;\\\\n maze[3] <= maze[4] | ship[1];\\\\n maze[2] <= (maze[3] | ship[0]) & 16'b1111110110111111;\\\\n maze[1] <= (maze[2] | ship[0]) & 16'b1111110110111111;\\\\n sync <= 0;\\\\n end\\\\n pc <= pc + 1;\\\\n end\\\\n\\\\n `MOVR: begin // \\\\u0414\\\\u0432\\\\u0438\\\\u0436\\\\u0435\\\\u043d\\\\u0438\\\\u0435 \\\\u043d\\\\u0430\\\\u0448\\\\u0435\\\\u0433\\\\u043e \\\\u043a\\\\u043e\\\\u0440\\\\u0430\\\\u0431\\\\u043b\\\\u044f \\\\u0432\\\\u043f\\\\u0440\\\\u0430\\\\u0432\\\\u043e\\\\n if (switches_p1[1] && sync) begin\\\\n if (left_pos < 11) begin\\\\n left_pos <= left_pos + 1;\\\\n maze[23][14:2] <= maze[23][13:1];\\\\n maze[24][14:2] <= maze[24][13:1];\\\\n maze[25][14:2] <= maze[25][13:1];\\\\n maze[23][1] <= 1'b0;\\\\n maze[24][1] <= 1'b0;\\\\n maze[25][1] <= 1'b0;\\\\n end\\\\n end\\\\n pc <= pc + 1;\\\\n end\\\\n \\\\n `MOVL: begin // \\\\u0414\\\\u0432\\\\u0438\\\\u0436\\\\u0435\\\\u043d\\\\u0438\\\\u0435 \\\\u043d\\\\u0430\\\\u0448\\\\u0435\\\\u0433\\\\u043e \\\\u043a\\\\u043e\\\\u0440\\\\u0430\\\\u0431\\\\u043b\\\\u044f \\\\u0441\\\\u043b\\\\u0435\\\\u0432\\\\u043e\\\\n if (switches_p1[0] && sync) begin\\\\n if (left_pos > 1) begin\\\\n left_pos <= left_pos - 1;\\\\n maze[23][13:1] <= maze[23][14:2];\\\\n maze[24][13:1] <= maze[24][14:2];\\\\n maze[25][13:1] <= maze[25][14:2];\\\\n maze[23][14] <= 1'b0;\\\\n maze[24][14] <= 1'b0;\\\\n maze[25][14] <= 1'b0;\\\\n end\\\\n end\\\\n pc <= pc + 1;\\\\n end\\\\n\\\\n `JMP: begin // \\\\u0411\\\\u0435\\\\u0437\\\\u0443\\\\u0441\\\\u043b\\\\u043e\\\\u0432\\\\u043d\\\\u044b\\\\u0439 \\\\u043f\\\\u0440\\\\u044b\\\\u0436\\\\u043e\\\\u043a \\\\u043a \\\\u043f\\\\u0435\\\\u0440\\\\u0432\\\\u043e\\\\u0439 \\\\u043a\\\\u043e\\\\u043c\\\\u0430\\\\u043d\\\\u0434\\\\u0435\\\\n pc <= {6'b000000, op};\\\\n end\\\\n\\\\n `DEL: begin // \\\\u0423\\\\u0434\\\\u0430\\\\u043b\\\\u0435\\\\u043d\\\\u0438\\\\u0435 \\\\u0432\\\\u0440\\\\u0430\\\\u0436\\\\u0435\\\\u0441\\\\u043a\\\\u043e\\\\u0433\\\\u043e \\\\u043a\\\\u043e\\\\u0440\\\\u0430\\\\u0431\\\\u043b\\\\u044f \\\\u043f\\\\u0440\\\\u0438 \\\\u043f\\\\u043e\\\\u043f\\\\u0430\\\\u0434\\\\u0430\\\\u043d\\\\u0438\\\\u0438\\\\n if (del) begin\\\\n ship[0] <= 16'b1000000000000001;\\\\n ship[1] <= 16'b1000000000000001;\\\\n ship[2] <= 16'b1000000000000001;\\\\n del <= 0;\\\\n end\\\\n pc <= pc + 1;\\\\n end\\\\n endcase\\\\n \\\\nend\\\\n \\\\n\\\\n hvsync_generator hvsync_gen(\\\\n .clk(clk),\\\\n .reset(0),\\\\n .hsync(hsync),\\\\n .vsync(vsync),\\\\n .display_on(display_on),\\\\n .hpos(hpos),\\\\n .vpos(vpos)\\\\n );\\\\n\\\\n wire r = 0;\\\\n wire g = display_on & ((playfield_gfx & vpos > 23 & vpos < 232 & hpos > 7 & hpos < 120));\\\\n wire b = display_on & playfield_gfx & hpos < 129;\\\\n \\\\n assign rgb = {b,g,r};\\\\nendmodule"]
['module FourBit_Adder_Subtractor( RCOSum, RCOCarryOut, RCOAddX, RCOAddY, RCOCarryIn);\\\\n\\\\n output [3:0] RCOSum;\\\\n output \\\\t\\\\t RCOCarryOut;\\\\n input [3:0] RCOAddX;\\\\n input [3:0] RCOAddY;\\\\n\\\\tinput\\\\t\\\\t RCOCarryIn;\\\\n\\\\n\\\\n// create wires for intermediate carries\\\\n\\\\nwire C1,C2,C3;\\\\nwire [3:0] Y_temp;\\\\n\\\\nassign Y_temp[3] = RCOAddY[3] ^ RCOCarryIn;\\\\nassign Y_temp[2] = RCOAddY[2] ^ RCOCarryIn;\\\\nassign Y_temp[1] = RCOAddY[1] ^ RCOCarryIn;\\\\nassign Y_temp[0] = RCOAddY[0] ^ RCOCarryIn;\\\\n// instantiate the set of full adders \\\\nFullAdder\\\\tRCO_FA0(RCOSum[0],C1,RCOAddX[0],Y_temp[0],RCOCarryIn);\\\\nFullAdder\\\\tRCO_FA1(RCOSum[1],C2,RCOAddX[1],Y_temp[1],C1);\\\\nFullAdder\\\\tRCO_FA2(RCOSum[2],C3,RCOAddX[2],Y_temp[2],C2);\\\\nFullAdder\\\\tRCO_FA3(RCOSum[3],RCOCarryOut,RCOAddX[3],Y_temp[3],C3);\\\\n\\\\t\\\\t\\\\t\\\\t\\\\n\\\\nendmodule']
["module SingleCycleCPU (\\\\n input clk,\\\\n input start,\\\\n output signed [31:0] r [0:31]\\\\n);\\\\n\\\\n// When input start is zero, cpu should reset\\\\n// When input start is high, cpu start running\\\\n\\\\n// TODO: connect wire to realize SingleCycleCPU\\\\n// The following provides simple template,\\\\n// you can modify it as you wish except I/O pin and register module\\\\n\\\\nwire [31:0] pc_o, adder_o, inst, writeData, readData1, readData2, imm, shift_o, adder_o2, MuxPC_o, MuxALU_o, ALUOut, readData;\\\\nwire branch, memRead, memtoReg, memWrite, ALUSrc, regWrite, zero, and_o;\\\\nwire [3:0] ALUCtl;\\\\nwire [1:0] ALUOp;\\\\n\\\\nPC m_PC(\\\\n .clk(clk),\\\\n .rst(start),\\\\n .pc_i(MuxPC_o),\\\\n .pc_o(pc_o)\\\\n);\\\\n\\\\nAdder m_Adder_1(\\\\n .a(pc_o),\\\\n .b(32'd4),\\\\n .sum(adder_o)\\\\n);\\\\n\\\\nInstructionMemory m_InstMem(\\\\n .readAddr(pc_o),\\\\n .inst(inst)\\\\n);\\\\n\\\\nControl m_Control(\\\\n .opcode(inst[6:0]),\\\\n .branch(branch),\\\\n .memRead(memRead),\\\\n .memtoReg(memtoReg),\\\\n .ALUOp(ALUOp),\\\\n .memWrite(memWrite),\\\\n .ALUSrc(ALUSrc),\\\\n .regWrite(regWrite)\\\\n);\\\\n\\\\n// For Student:\\\\n// Do not change the Register instance name!\\\\n// Or you will fail validation.\\\\n\\\\nRegister m_Register(\\\\n .clk(clk),\\\\n .rst(start),\\\\n .regWrite(regWrite),\\\\n .readReg1(inst[19:15]),\\\\n .readReg2(inst[24:20]),\\\\n .writeReg(inst[11:7]),\\\\n .writeData(writeData),\\\\n .readData1(readData1),\\\\n .readData2(readData2)\\\\n);\\\\n\\\\n// ======= for validation =======\\\\n// == Dont change this section ==\\\\nassign r = m_Register.regs;\\\\n// ======= for vaildation =======\\\\n\\\\nImmGen m_ImmGen(\\\\n .inst(inst),\\\\n .imm(imm)\\\\n);\\\\n\\\\nShiftLeftOne m_ShiftLeftOne(\\\\n .i(imm),\\\\n .o(shift_o)\\\\n);\\\\n\\\\nAdder m_Adder_2(\\\\n .a(pc_o),\\\\n .b(shift_o),\\\\n .sum(adder_o2)\\\\n);\\\\n\\\\nand A1(and_o, branch, zero);\\\\n\\\\nMux2to1 #(.size(32)) m_Mux_PC(\\\\n .sel(and_o),\\\\n .s0(adder_o),\\\\n .s1(adder_o2),\\\\n .out(MuxPC_o)\\\\n);\\\\n\\\\nMux2to1 #(.size(32)) m_Mux_ALU(\\\\n .sel(ALUSrc),\\\\n .s0(readData2),\\\\n .s1(imm),\\\\n .out(MuxALU_o)\\\\n);\\\\n\\\\nALUCtrl m_ALUCtrl(\\\\n .ALUOp(ALUOp),\\\\n .funct7(inst[30]),\\\\n .funct3(inst[14:12]),\\\\n .ALUCtl(ALUCtl)\\\\n);\\\\n\\\\nALU m_ALU(\\\\n .ALUctl(ALUCtl),\\\\n .A(readData1),\\\\n .B(MuxALU_o),\\\\n .ALUOut(ALUOut),\\\\n .zero(zero)\\\\n);\\\\n\\\\nDataMemory m_DataMemory(\\\\n .rst(start),\\\\n .clk(clk),\\\\n .memWrite(memWrite),\\\\n .memRead(memRead),\\\\n .address(ALUOut),\\\\n .writeData(readData2),\\\\n .readData(readData)\\\\n);\\\\n\\\\nMux2to1 #(.size(32)) m_Mux_WriteData(\\\\n .sel(memtoReg),\\\\n .s0(ALUOut),\\\\n .s1(readData),\\\\n .out(writeData)\\\\n);\\\\n\\\\nendmodule"]
["module Lab4(\\\\n\\\\tinput R1, R2, R3, arm_sw_n, panic_sw_n, RESET, clock50,\\\\n\\\\toutput DISARM_LED, ARM_TRIG_LED, SIREN, STROBE, R1_LED, R2_LED, R3_LED\\\\n);\\\\n\\\\n\\\\nwire AT, ST, armed, panic;\\\\t\\\\t//Alarm timer and Set timer wires\\\\nreg FiveSecMr = 0;\\\\nreg FiveSecEn = 0;\\\\nreg FiveSecLoad_en = 0;\\\\nreg TwentySecMr = 0;\\\\nreg TwentySecEn = 0;\\\\nreg TwentySecload_en = 0;\\\\nreg sir = 0, str = 0;\\\\nreg Strload_en =0;\\\\nreg StrMr=0;\\\\nreg arm_reset =0;\\\\nreg panic_reset =1;\\\\n\\\\nassign DISARM_LED = ~armed;\\\\nassign ARM_TRIG_LED = armed;\\\\nassign R1_LED = R1;\\\\nassign R2_LED = R2;\\\\nassign R3_LED = R3;\\\\n\\\\nreg SD_Load =0;\\\\nreg SD_En =1;\\\\nreg [9:0]SD_LoadV = 0;\\\\nreg [9:0]qout11;\\\\nreg [9:0]qout12;\\\\nreg SD_Mr = 0;\\\\n\\\\n\\\\nwire first_step_down, new_clock;\\\\nTenbitcounter SD1 (clock50, SD_Mr, SD_En, SD_Load, SD_LoadV, Qout11, first_step_down);\\\\nTenbitcounter SD2 (first_step_down, SD_Mr, SD_En, SD_Load, SD_LoadV, Qout11, new_clock);\\\\n\\\\nSwitch SW1(arm_sw_n, RESET, armed);\\\\nSwitch SW2(panic_sw_n, RESET, panic);\\\\nFiveSecondTimer TS1(clock50, FiveSecMr, FiveSecEn, FiveSecLoad_en, ST);\\\\nTwentySecondTimer TWS1(clock50, TwentySecMr, TwentySecEn, TwentySecload_en, AT);\\\\n\\\\nFiveHzBlink FHZ(clock50, StrMr, str, Strload_en, STROBE);\\\\nassign SIREN = sir;\\\\n\\\\n\\\\nalways@(posedge(new_clock))\\\\nbegin\\\\n\\\\tTwentySecMr = 0;\\\\n\\\\tFiveSecMr = 0;\\\\n\\\\t\\\\n\\\\tif(RESET)\\\\t\\\\t\\\\t\\\\t//Reset handler\\\\n\\\\tbegin\\\\n\\\\tFiveSecMr = 1;\\\\n\\\\tTwentySecMr = 1;\\\\n\\\\tsir = 0;\\\\n\\\\tstr = 0;\\\\n\\\\tend\\\\n\\\\t\\\\n\\\\telse if (armed | panic ==1)\\\\t\\\\t\\\\t\\\\t//ASM first condition\\\\n\\\\tbegin\\\\n\\\\t\\\\tTwentySecEn = 1;\\\\n\\\\t\\\\tFiveSecEn = 1;\\\\n\\\\t\\\\n\\\\t\\\\tif (AT == 0 | panic==1)\\\\t\\\\t\\\\t\\\\t\\\\t//ASM second condition\\\\n\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\n\\\\t\\\\t\\\\tif ((R1 == 1'b1) | (R2 == 1'b1) | (R3 == 1'b1) | panic==1) //ASM third condition\\\\n\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\tTwentySecMr = 1;\\\\n\\\\t\\\\t\\\\t\\\\tif (ST == 1 | panic ==1)\\\\t\\\\t//ASM fourth condition. If met alarm =>triggered\\\\n\\\\t\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tsir = 1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tstr = 1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\tend\\\\t\\\\n\\\\t\\\\tend\\\\n\\\\n\\\\t\\\\telse\\\\n\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\tsir =0;\\\\n\\\\t\\\\t\\\\tstr =0;\\\\n\\\\t\\\\t\\\\tTwentySecMr = 1;\\\\n\\\\t\\\\tend\\\\n\\\\tend\\\\n\\\\telse if (~armed | AT)\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t//Disarm register set.\\\\n\\\\tbegin\\\\n\\\\t\\\\tTwentySecMr = 1;\\\\n\\\\t\\\\tFiveSecMr = 1;\\\\n\\\\t\\\\tsir = 0;\\\\n\\\\t\\\\tstr = 0;\\\\n\\\\t\\\\tTwentySecEn = 0;\\\\n\\\\t\\\\tFiveSecEn = 0;\\\\n\\\\tend\\\\t\\\\nend\\\\n\\\\n\\\\n\\\\nendmodule"]
["module div_32_tb;\\\\nreg PCout, Zhighout, Zlowout, MDRout, R6out, R7out, HIout, LOout; \\\\nreg MARin, Zin, PCin, MDRin, IRin, Yin, HIin, LOin;\\\\nreg IncPC, Read, R6in, R7in;\\\\nreg [4:0] opcode;\\\\nreg Clock;\\\\nreg flag;\\\\nreg [31:0] Mdatain;\\\\n\\\\nparameter Default = 4'b0000, Reg_load1a = 4'b0001, Reg_load1b = 4'b0010, Reg_load2a = 4'b0011, Reg_load2b = 4'b0100, Reg_load3a = 4'b0101, Reg_load3b = 4'b0110, T0 = 4'b0111, T1 = 4'b1000, T2 = 4'b1001, T3 = 4'b1010, T4 = 4'b1011, T5 = 4'b1100, T6 = 4'b1101;\\\\n\\\\nreg [3:0] Present_state = Default;\\\\n\\\\ndatapath DUT(Clock, 1'b0, Mdatain, Read, IncPC, {8'd0, R7in, R6in, 6'b0}, {8'd0, R7out, R6out, 6'd0}, PCin, Zin, MDRin, MARin, Yin, HIin, LOin, IRin, PCout, Zhighout, Zlowout, HIout, LOout, MDRout, 1'b0, opcode);\\\\n\\\\ninitial begin\\\\n Clock = 0;\\\\n flag = 0;\\\\n forever #10 Clock = ~ Clock;\\\\nend\\\\n\\\\nalways @(posedge Clock) begin\\\\n if (flag == 1) begin\\\\n case (Present_state)\\\\n Default: Present_state = Reg_load1a;\\\\n Reg_load1a: Present_state = Reg_load1b;\\\\n Reg_load1b: Present_state = Reg_load2a;\\\\n Reg_load2a: Present_state = Reg_load2b;\\\\n Reg_load2b: Present_state = Reg_load3a;\\\\n Reg_load3a: Present_state = Reg_load3b;\\\\n Reg_load3b: Present_state = T0;\\\\n T0: Present_state = T1;\\\\n T1: Present_state = T2;\\\\n T2: Present_state = T3;\\\\n T3: Present_state = T4;\\\\n T4: Present_state = T5;\\\\n\\\\t T5: Present_state = T6;\\\\n endcase\\\\n flag = 0;\\\\n end else begin\\\\n flag = 1;\\\\n end\\\\nend\\\\n\\\\nalways @(Present_state) begin\\\\n case (Present_state)\\\\n Default: begin\\\\n PCout <= 0; Zlowout <= 0; Zhighout <= 0; MDRout <= 0; HIout <= 0; LOout <= 0;\\\\n R6out <= 0; R7out <= 0; MARin <= 0; Zin <= 0;\\\\n PCin <= 0; MDRin <= 0; IRin <= 0; Yin <= 0; HIin <= 0; LOin <= 0;\\\\n IncPC <= 0; Read <= 0; opcode <= 5'b00000;\\\\n R6in <= 0; R7in <= 0; Mdatain <= 32'h00000000;\\\\n end\\\\n Reg_load1a: begin\\\\n Mdatain <= 32'hFFFFFFEB;\\\\n Read = 0; MDRin = 0;\\\\n #10 Read <= 1; MDRin <= 1;\\\\n #15 Read <= 0; MDRin <= 0;\\\\n end\\\\n Reg_load1b: begin\\\\n #10 MDRout <= 1; R6in <= 1;\\\\n #15 MDRout <= 0; R6in <= 0;\\\\n end\\\\n Reg_load2a: begin\\\\n Mdatain <= 32'hFFFFFFFB;\\\\n #10 Read <= 1; MDRin <= 1;\\\\n #15 Read <= 0; MDRin <= 0;\\\\n end\\\\n Reg_load2b: begin\\\\n #10 MDRout <= 1; R7in <= 1;\\\\n #15 MDRout <= 0; R7in <= 0;\\\\n end\\\\n Reg_load3a: begin\\\\n end\\\\n Reg_load3b: begin\\\\n end\\\\n T0: begin\\\\n PCout <= 1; MARin <= 1; IncPC <= 1;\\\\n #10 PCout <= 0; MARin <= 0; PCin <= 1;\\\\n\\\\t\\\\t\\\\t#10 PCin <= 0; IncPC <= 0;\\\\n end\\\\n T1: begin\\\\n Mdatain <= 32'h28918000; // opcode for \\\\u201cand R1, R2, R3\\\\u201d\\\\n #10 Read <= 1; MDRin <= 1;\\\\n #15 Read <= 0; MDRin <= 0;\\\\n end\\\\n T2: begin\\\\n #10 MDRout <= 1; IRin <= 1;\\\\n #15 MDRout <= 0; IRin <= 0;\\\\n end\\\\n T3: begin\\\\n #10 R6out <= 1; Yin <= 1;\\\\n #15 R6out <= 0; Yin <= 0;\\\\n end\\\\n T4: begin\\\\n #10 R7out <= 1; opcode <= 5'b10000; Zin <= 1;\\\\n #15 R7out <= 0; Zin <= 0;\\\\n end\\\\n T5: begin\\\\n #10 Zlowout <= 1; LOin <= 1;\\\\n #15 Zlowout <= 0; LOin <= 0;\\\\n end\\\\n\\\\t\\\\tT6: begin\\\\n\\\\t\\\\t\\\\t#10 Zhighout <= 1; HIin <= 1;\\\\n\\\\t\\\\t\\\\t#15 Zhighout <= 0; HIin <= 0;\\\\n\\\\t\\\\tend\\\\n endcase\\\\nend\\\\nendmodule"]
["module multicore_processor(clk,core_status,dm_write_en,im_write_en,dm_addr,im_addr,dm_input_data,im_input_data,terminate,dm_output_data);\\\\n\\\\ninput clk;\\\\ninput [3:0] core_status;\\\\ninput dm_write_en;\\\\ninput [15:0] dm_addr;\\\\ninput [15:0] dm_input_data;\\\\n\\\\noutput reg terminate = 1'd0;\\\\noutput wire [15:0] dm_output_data;\\\\n\\\\ninput im_write_en;\\\\ninput [15:0] im_addr;\\\\ninput [15:0] im_input_data;\\\\n//wire f_in;\\\\nwire dm_en1,dm_en2,dm_en3,dm_en4;\\\\n\\\\nwire [15:0] dar_out1,dar_out2,dar_out3,dar_out4;\\\\nwire [15:0] bus_out1,bus_out2,bus_out3,bus_out4;\\\\nwire [15:0] data_out1,data_out2,data_out3,data_out4;\\\\nwire [15:0] pc_out1,pc_out2,pc_out3,pc_out4;\\\\nwire [15:0] ins_out1,ins_out2,ins_out3,ins_out4;\\\\nwire [15:0] ins_out_c1,ins_out_c2,ins_out_c3,ins_out_c4;\\\\nwire [3:0] f_out;\\\\nwire end_process1,end_process2,end_process3,end_process4;\\\\n\\\\n\\\\nprocessor processor1(.clk(clk), .f_in(f_out[0]),.dm_out(data_out1), .im_out(ins_out_c1), .status(core_status[0]), .dm_en(dm_en1), .pc_out(pc_out1), .dar_out(dar_out1), .bus_out(bus_out1), .end_process(end_process1));\\\\nprocessor processor2(.clk(clk), .f_in(f_out[1]),.dm_out(data_out2), .im_out(ins_out_c2), .status(core_status[1]), .dm_en(dm_en2), .pc_out(pc_out2), .dar_out(dar_out2), .bus_out(bus_out2), .end_process(end_process2));\\\\nprocessor processor3(.clk(clk), .f_in(f_out[2]),.dm_out(data_out3), .im_out(ins_out_c3), .status(core_status[2]), .dm_en(dm_en3), .pc_out(pc_out3), .dar_out(dar_out3), .bus_out(bus_out3), .end_process(end_process3));\\\\nprocessor processor4(.clk(clk), .f_in(f_out[3]),.dm_out(data_out4), .im_out(ins_out_c4), .status(core_status[3]), .dm_en(dm_en4), .pc_out(pc_out4), .dar_out(dar_out4), .bus_out(bus_out4), .end_process(end_process4));\\\\n\\\\n\\\\n\\\\nins_memory im1(.clk(clk), .im_write_en(im_write_en), .im_input_data(im_input_data), .im_addr(im_addr), .addr1(pc_out1), .addr2(pc_out2), .addr3(pc_out3), .addr4(pc_out4), .ins_out1(ins_out1),.ins_out2(ins_out2), .ins_out3(ins_out3),.ins_out4(ins_out4));\\\\ndata_memory dm1(.clk(clk), .dm_write_en(dm_write_en), .dm_input_data(dm_input_data), .dm_addr(dm_addr), .write_en1(dm_en1), .write_en2(dm_en2), .write_en3(dm_en3), .write_en4(dm_en4), .addr1(dar_out1),.addr2(dar_out2), .addr3(dar_out3),.addr4(dar_out4), .data_in1(bus_out1),.data_in2(bus_out2), .data_in3(bus_out3),.data_in4(bus_out4), .dm_output_data(dm_output_data), .data_out1(data_out1), .data_out2(data_out2),.data_out3(data_out3), .data_out4(data_out4));\\\\n\\\\ncore_init core_init1(.clk(clk),.ins_in1(ins_out1),.ins_in2(ins_out2),.ins_in3(ins_out3),.ins_in4(ins_out4),.ins_out1(ins_out_c1),.ins_out2(ins_out_c2),.ins_out3(ins_out_c3),.ins_out4(ins_out_c4),.f_out(f_out));\\\\n\\\\t\\\\n\\\\nalways@(posedge clk) begin\\\\n\\\\tif(core_status==4'b0001)\\\\n\\\\t\\\\tif (end_process1 == 1'd1)\\\\n\\\\t\\\\t\\\\tterminate <= 1'd1;\\\\n\\\\t\\\\n\\\\tif(core_status==4'b0011)\\\\n\\\\t\\\\tif (end_process1 == 1'd1 & end_process2==1'd1)\\\\n\\\\t\\\\t\\\\tterminate <= 1'd1;\\\\n\\\\t\\\\n\\\\tif(core_status==4'b0111)\\\\n\\\\t\\\\tif (end_process1 == 1'd1 & end_process2==1'd1 && end_process3==1'd1)\\\\n\\\\t\\\\t\\\\tterminate <= 1'd1;\\\\n\\\\t\\\\n\\\\tif(core_status==4'b1111)\\\\t\\\\n\\\\t\\\\tif (end_process1 == 1'd1 & end_process2==1'd1 && end_process3 ==1'd1 && end_process4 == 1'd1)\\\\n\\\\t\\\\t\\\\tterminate <= 1'd1;\\\\nend\\\\t\\\\nendmodule"]
["module controller(input start, clk, rst, getA, getB, put1, put2, input[2:0] op,\\\\n\\\\t\\\\t \\\\t\\\\toutput reg initA, initP, initC, loadlsbA, loadmsbA, loadP, loadA, loadlsbB, loadmsbB, SA2, select, ready,\\\\n\\\\t\\\\t\\\\t\\\\toutput reg[1:0] SA);\\\\n\\\\n\\\\treg cen;\\\\n\\\\twire co;\\\\n\\\\treg[3:0]ps,ns;\\\\n\\\\tparameter[3:0] Idle = 0, Begins = 1, LA1 = 2, WA = 3, LA2 = 4, LB1 = 5, WB = 6, LB2 = 7, Count = 8, Put1 = 9, Put2 = 10;\\\\n\\\\n\\\\talways@(ps,co ,start, getA,getB,op,put1)begin\\\\n\\\\t\\\\t{initA,initP,initC,loadlsbA,loadmsbA,loadlsbB,loadmsbB,loadP,cen,SA2,loadA,select,ready}=13'b0;\\\\n\\\\t\\\\tSA=2'b0;ns=Idle;\\\\n\\\\t\\\\tcase(ps)\\\\n\\\\t\\\\t\\\\tIdle:begin ns = start ? Begins : Idle;end\\\\n\\\\t\\\\t\\\\tBegins:begin ns = getA ? Begins : LA1; loadlsbA = 1; initA=1; initP = 1; initC = 1;end\\\\n\\\\t\\\\t\\\\tLA1:begin ns = getA ? WA : LA1; loadlsbA = 1;end\\\\n\\\\t\\\\t\\\\tWA: begin ns = getA ? WA: LA2;end\\\\n\\\\t\\\\t\\\\tLA2:begin ns = getB ? LA2: LB1; loadmsbA = 1;end\\\\n\\\\t\\\\t\\\\tLB1:begin ns = getB ? WB: LB1; loadlsbB = 1;end\\\\n\\\\t\\\\t\\\\tWB:ns = getB ? WB : LB2;\\\\n\\\\t\\\\t\\\\tLB2:begin ns = Count; loadmsbB = 1;end\\\\n\\\\t\\\\t\\\\tCount:begin ns = co ? Put1 : Count; loadA = 1; loadP = 1; cen = 1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tif (op == 3'b000 || op==3'b111)begin SA = 2'b00; SA2 = 1;end\\\\n\\\\t\\\\t\\\\t\\\\t\\\\telse if (op == 3'b101 || op == 3'b110)begin SA=2'b01; SA2 = 0;end\\\\n\\\\t\\\\t\\\\t\\\\t\\\\telse if (op == 3'b001 || op == 3'b010) begin SA = 2'b01; SA2 = 1;end\\\\n\\\\t\\\\t\\\\t\\\\t\\\\telse if (op == 3'b011) begin SA = 2'b10; SA2 = 1;end\\\\n\\\\t\\\\t\\\\t\\\\t\\\\telse if (op == 3'b100) begin SA = 2'b10; SA2 = 0;end\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\tPut1:begin ns = put1 ? Put1 : Put2; select = 0;end\\\\n\\\\t\\\\t\\\\tPut2:begin ns = put1 ? Put2 : Idle; select = 1; ready = 1;end\\\\n\\\\t\\\\t\\\\tdefault: ns = Idle;\\\\n\\\\t\\\\tendcase\\\\n\\\\tend\\\\n\\\\n\\\\talways@(posedge clk,posedge rst)begin\\\\n\\\\t\\\\tif(rst) ps <= Idle;\\\\n\\\\t\\\\telse ps <= ns;\\\\n\\\\tend\\\\n\\\\n\\\\twire[2:0]out;\\\\n\\\\tCounter counter( clk,rst,initC,cen,out, co);\\\\nendmodule"]
['module adder_4bit(input [3:0]x,input [3:0]y,input cin,\\\\noutput [3:0]s, output cout);\\\\n\\\\nwire p,q,r;\\\\n\\\\nfull_adder m1(x[0], y[0], cin, s[0], p);\\\\nfull_adder m2(x[1], y[1], p, s[1], q);\\\\nfull_adder m3(x[2], y[2], q, s[2], r);\\\\nfull_adder m4(x[3], y[3], r, s[3], cout);\\\\n\\\\nendmodule', 'module adder_4bit_tb();\\\\nreg [3:0]x;reg [3:0]y;reg cin;\\\\nwire [3:0]s; wire cout;\\\\n//adder_4bit u1(.[3:0]x([3:0]x),.[3:0]y([3:0]y),.cin(cin),.[3:0]s([3:0]s),.cout(cout));\\\\nadder_4bit ua(.x(x),.y(y),.cin(cin),.s(s),.cout(cout));\\\\ninitial begin\\\\n\\\\t$dumpfile(\\\\"add.vcd\\\\");\\\\n\\\\t$dumpvars(-1,ua);\\\\nend\\\\n\\\\ninitial begin\\\\nx=4\\'b0000;y=4\\'b0000;cin=1\\'b0;#0;\\\\nx=4\\'b0100;y=4\\'b0011;cin=1\\'b1;#10;\\\\nx=4\\'b0011;y=4\\'b0111;cin=1\\'b1;#20;\\\\nx=4\\'b1000;y=4\\'b0100;cin=1\\'b0;#30;\\\\nx=4\\'b0101;y=4\\'b0101;cin=1\\'b1;#40;\\\\nend\\\\nendmodule']
["module div (\\\\n input [`DMEMA_W+2:0] adr,\\\\n output [5:0] mem_adr,\\\\n output [3:0] mem_adr_i\\\\n);\\\\n\\\\t\\\\nwire [8:0] adr_1, adr_2, adr_3, adr_4, adr_5;\\\\n\\\\nwire [3:0] div_num;\\\\nassign div_num = 4'b1100;\\\\n\\\\nassign mem_adr[5] = adr < {div_num,5'b0} ? 1'b0 : 1'b1;\\\\nassign adr_5 = mem_adr[5] == 1'b0 ? adr : adr - {div_num, 5'b0};\\\\nassign mem_adr[4] = adr_5 < {1'b0,div_num,4'b0} ? 1'b0 : 1'b1;\\\\nassign adr_4 = mem_adr[4] == 1'b0 ? adr_5 : adr_5 - {1'b0,div_num,4'b0};\\\\nassign mem_adr[3] = adr_4 < {2'b0,div_num,3'b0} ? 1'b0 : 1'b1;\\\\nassign adr_3 = mem_adr[3] == 1'b0 ? adr_4 : adr_4 - {2'b0,div_num,3'b0};\\\\nassign mem_adr[2] = adr_3 < {3'b0,div_num,2'b0} ? 1'b0 : 1'b1;\\\\nassign adr_2 = mem_adr[2] == 1'b0 ? adr_3 : adr_3 - {3'b0,div_num,2'b0};\\\\nassign mem_adr[1] = adr_2 < {4'b0,div_num,1'b0} ? 1'b0 : 1'b1;\\\\nassign adr_1 = mem_adr[1] == 1'b0 ? adr_2 : adr_2 - {4'b0,div_num,1'b0};\\\\nassign mem_adr[0] = adr_1 < {5'b0,div_num} ? 1'b0 : 1'b1;\\\\nassign mem_adr_i = mem_adr[0] == 1'b0 ? adr_1 : adr_1 - {5'b0,div_num};\\\\n\\\\nendmodule"]
["module mult8x8(\\\\n input [7:0] dataa,datab,\\\\n input start,clk,reset_a,\\\\n output [15:0] product8x8_out,\\\\n output wire done_flag,\\\\n output seg_a,seg_b,seg_c,seg_d,seg_e,seg_f,seg_g\\\\n);\\\\n\\\\nwire [1:0] sel,shift,count;\\\\nwire [2:0] state_out;\\\\nwire clk_ena,sclr_n;\\\\n\\\\nwire [3:0] aout,bout;\\\\n\\\\nwire [7:0] product;\\\\n\\\\nwire [15:0] shift_out,sum;\\\\nwire cout;\\\\n\\\\nmux u1 (dataa[3:0],dataa[7:4],sel[1],aout);\\\\nmux u2 (datab[3:0],datab[7:4],sel[0],bout);\\\\n\\\\nmult4x4 u3 (aout,bout,product);\\\\n\\\\nleft_shifter u4 (product,shift,shift_out);\\\\n\\\\nFA_generic #(.N(16)) u5 (shift_out,product8x8_out,1'b0,sum,cout);\\\\n\\\\nSync16BitRegister u6 (sum,sclr_n,clk_ena,clk,product8x8_out);\\\\n\\\\nFSM1 u7 (clk,reset_a,start,count,sel,shift,state_out,done_flag,clk_ena,sclr_n);\\\\n\\\\nCounter u8 ((!start),clk,count);\\\\nseven_segment_encoder u9 (state_out,{seg_a,seg_b,seg_c,seg_d,seg_e,seg_f,seg_g});\\\\n\\\\nendmodule"]
["module BIN_converter_BCD(\\\\n\\\\tin,\\\\n\\\\tunits,\\\\n\\\\ttens,\\\\n\\\\thunds\\\\n);\\\\n\\\\n\\\\t// Defs\\\\n\\\\tinput [7:0] in;\\\\n\\\\toutput [3:0] units, tens, hunds;\\\\n\\\\twire [3:0] c1,c2,c3,c4,c5,c6,c7;\\\\n\\\\twire [3:0] d1,d2,d3,d4,d5,d6,d7;\\\\n\\\\t\\\\n\\\\t// Converter\\\\n\\\\tassign d1 = {1'b0,in[7:5]};\\\\n\\\\tassign d2 = {c1[2:0],in[4]};\\\\n\\\\tassign d3 = {c2[2:0],in[3]};\\\\n\\\\tassign d4 = {c3[2:0],in[2]};\\\\n\\\\tassign d5 = {c4[2:0],in[1]};\\\\n\\\\tassign d6 = {1'b0,c1[3],c2[3],c3[3]};\\\\n\\\\tassign d7 = {c6[2:0],c4[3]};\\\\n\\\\tadd3 m1(d1,c1);\\\\n\\\\tadd3 m2(d2,c2);\\\\n\\\\tadd3 m3(d3,c3);\\\\n\\\\tadd3 m4(d4,c4);\\\\n\\\\tadd3 m5(d5,c5);\\\\n\\\\tadd3 m6(d6,c6);\\\\n\\\\tadd3 m7(d7,c7);\\\\n\\\\tassign units = {c5[2:0],in[0]};\\\\n\\\\tassign tens = {c7[2:0],c5[3]};\\\\n\\\\tassign hunds = {c6[3],c7[3]};\\\\n\\\\n\\\\nendmodule"]
["module Multiplication(A, B, C);\\\\n input [31:0]A,B;\\\\n output [31:0]C; //A, B, C are represented according to IEEE standard 754 floating point representation\\\\n wire sign;\\\\n assign sign = A[31]^B[31];\\\\n wire [7:0]ae, be;\\\\n assign ae = A[30:23] - 8'd127;\\\\n assign be = B[30:23] - 8'd127; // ae, be are unbiased exponents\\\\n wire [23:0]am, bm;\\\\n wire [22:0]cman;\\\\n wire [47:0]cm;\\\\n assign am = {1'b1,A[22:0]}; // Reprentation of (1.A_mantissa) as 24 bits\\\\n assign bm = {1'b1,B[22:0]}; // Reprentation of (1.B_mantissa) as 24 bits\\\\n wire [7:0]ce,cexp;\\\\n assign ce = (ae + be) + 8'd127; // Biasing exponent.\\\\n // Sum of unbiased exponents should be in the range (-127,128] to avoid overflow\\\\n radix4booth mul({8'd0,am},{8'd0,bm},cm); // 24 bit multiplication \\\\n \\\\n// assign cman = cm[47] ? (cm[23] ? cm[46:24]+1'b1 : cm[46:24]) : (cm[22] ? cm[45:23]+1'b1 : cm[45:23]); //This includes rounding off mantissa product to 23 bits\\\\n assign cman = cm[47] ? cm[46:24] : cm[45:23]; //This step is truncation instead of rounding\\\\n assign cexp = cm[47]? (ce + 1'b1):ce; // Exponent increases by 1 depending on mantiassas multiplication.\\\\n assign C = {sign,cexp,cman};\\\\n\\\\n \\\\nendmodule"]