Datasets:
abi011020
/
eda_verilog_code_100k

Dataset card Data Studio Files
xet
Community
1
code
stringlengths
3
84.9M
['module CTRL(instr,\\\\n\\\\t\\\\t\\\\t\\\\tbranch,npcop,extop,regdst,otherctrl,aluop,alusrc,memwrite,memtoreg,regwrite,isbeq,isbne,\\\\n\\\\t\\\\t\\\\t\\\\tismtc0,ismfc0,\\\\n\\\\t\\\\t\\\\t\\\\twordmode,\\\\n\\\\t\\\\t\\\\t\\\\tusemd,start,mdop);\\\\ninteger debug;\\\\t\\\\t\\\\t\\\\t\\\\ninput [31:0] instr;\\\\noutput reg branch,memwrite,regwrite;\\\\noutput reg[1:0] extop,regdst,otherctrl,alusrc,memtoreg;\\\\noutput reg [2:0]npcop;\\\\noutput isbeq,ismtc0,ismfc0,isbne;\\\\noutput [2:0] wordmode;\\\\noutput start,usemd;\\\\noutput [1:0]mdop;\\\\noutput reg[4:0] aluop;\\\\n\\\\n\\\\nwire [5:0] op,funct;\\\\nassign op=instr[31:26];\\\\nassign funct=instr[5:0];\\\\nwire [4:0] rs,rt,rd,shamt;\\\\nassign rs=instr[25:21];\\\\nassign rt=instr[20:16];\\\\nassign rd=instr[15:11];\\\\nassign shamt=instr[10:6];\\\\n\\\\nassign isbeq=(op==`beq);\\\\nassign isbne=(op==`bne);\\\\nassign ismfc0=(op==`cop0&&rs==`mfc0_rs);\\\\nassign ismtc0=(op==`cop0&&rs==`mtc0_rs);\\\\nassign wordmode=(op==`lbu)?`wm_bu:\\\\n (op==`lh||op==`sh)?`wm_hs:\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t (op==`lhu)?`wm_hu:\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t (op==`lb||op==`sb)?`wm_bs:\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t `wm_wd;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t \\\\nassign mdop=((op==`special)&&funct==`divu_funct&&instr[15:6]==0)?`md_divu:\\\\n\\\\t\\\\t\\\\t\\\\t ((op==`special)&&funct==`div_funct&&instr[15:6]==0)?`md_div:\\\\n\\\\t\\\\t\\\\t\\\\t ((op==`special)&&funct==`multu_funct&&instr[15:6]==0)?`md_multu:\\\\n\\\\t\\\\t\\\\t\\\\t `md_mult;\\\\nassign usemd=(op==`special&&instr[20:6]==0&&(funct==`mthi_funct||funct==`mtlo_funct)\\\\n\\\\t\\\\t\\\\t\\\\t ||op==`special&&instr[25:16]==0&&instr[10:6]==0&&(funct==`mfhi_funct||funct==`mflo_funct)\\\\n\\\\t\\\\t\\\\t\\\\t ||(op==`special&&funct==`divu_funct&&instr[15:6]==0)\\\\n\\\\t\\\\t\\\\t\\\\t ||(op==`special&&funct==`div_funct&&instr[15:6]==0)\\\\n\\\\t\\\\t\\\\t\\\\t ||(op==`special&&funct==`multu_funct&&instr[15:6]==0)\\\\n\\\\t\\\\t\\\\t\\\\t ||(op==`special&&funct==`mult_funct&&instr[15:6]==0));\\\\nassign start=(op==`special&&funct==`divu_funct&&instr[15:6]==0)\\\\n\\\\t\\\\t\\\\t\\\\t ||(op==`special&&funct==`div_funct&&instr[15:6]==0)\\\\n\\\\t\\\\t\\\\t\\\\t ||(op==`special&&funct==`multu_funct&&instr[15:6]==0)\\\\n\\\\t\\\\t\\\\t\\\\t ||(op==`special&&funct==`mult_funct&&instr[15:6]==0);\\\\ninitial begin\\\\ndebug=0;\\\\n\\\\tbranch<=0; npcop<=0; extop<=0; regdst<=0; otherctrl<=0; aluop<=0; \\\\n\\\\talusrc<=0; memwrite<=0; memtoreg<=0; regwrite<=0;\\\\nend\\\\n\\\\n\\\\nalways @(*)\\\\n\\\\tbegin\\\\n\\\\t\\\\tif(op==`special &&shamt==0&&(funct==`addu_funct||funct==`add_funct||funct==`subu_funct||funct==`sub_funct\\\\n\\\\t\\\\t ||funct==`and_funct||funct==`or_funct||funct==`xor_funct||funct==`nor_funct))\\\\n\\\\t\\\\t\\\\tbegin//addu add subu sub and or xor nor\\\\n\\\\t\\\\t\\\\tdebug=1;\\\\n\\\\t\\\\t\\\\t\\\\tbranch<=0; npcop<=0; extop<=0; regdst<=`regdst_rd; otherctrl<=0; \\\\n\\\\t\\\\t\\\\t\\\\talusrc<=`alusrc_rd2; memwrite<=0; memtoreg<=`memtoreg_ao; regwrite<=1;\\\\n\\\\t\\\\t\\\\t\\\\tif (funct==`addu_funct||funct==`add_funct)\\\\n\\\\t\\\\t\\\\t\\\\t\\\\taluop<=`alu_add;\\\\n\\\\t\\\\t\\\\t\\\\telse if(funct==`subu_funct||funct==`sub_funct)\\\\n\\\\t\\\\t\\\\t\\\\t\\\\taluop<=`alu_sub;\\\\n\\\\t\\\\t\\\\t\\\\telse if(funct==`and_funct)\\\\n\\\\t\\\\t\\\\t\\\\t\\\\taluop<=`alu_and;\\\\n\\\\t\\\\t\\\\t\\\\telse if(funct==`or_funct)\\\\n\\\\t\\\\t\\\\t\\\\t\\\\taluop<=`alu_or;\\\\n\\\\t\\\\t\\\\t\\\\telse if(funct==`xor_funct)\\\\n\\\\t\\\\t\\\\t\\\\t\\\\taluop<=`alu_xor;\\\\n\\\\t\\\\t\\\\t\\\\telse if(funct==`nor_funct)\\\\n\\\\t\\\\t\\\\t\\\\t\\\\taluop<=`alu_nor;\\\\t\\\\n\\\\t\\\\t\\\\t\\\\telse \\\\n\\\\t\\\\t\\\\t\\\\t\\\\taluop<=`alu_debug;\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\telse if(op==`ori||op==`andi||op==`xori)\\\\n\\\\t\\\\t\\\\tbegin//ori andi xori\\\\n\\\\t\\\\t\\\\t\\\\tdebug=2;\\\\n\\\\t\\\\t\\\\t\\\\tbranch<=0; npcop<=0; extop<=`ext_unsign; regdst<=`regdst_rt; otherctrl<=`oth_ext;\\\\n\\\\t\\\\t\\\\t\\\\talusrc<=`alusrc_oth; memwrite<=0; memtoreg<=`memtoreg_ao; regwrite<=1;\\\\n\\\\t\\\\t\\\\t\\\\tif(op==`ori) \\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\taluop<=`alu_or;\\\\n\\\\t\\\\t\\\\t\\\\telse if(op==`andi)\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\taluop<=`alu_and;\\\\n\\\\t\\\\t\\\\t\\\\telse if(op==`xori)\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\taluop<=`alu_xor;\\\\n\\\\t\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\telse if(op==`special&&shamt==0&&funct==`jr_funct&&instr[20:6]==0)\\\\n\\\\t\\\\t\\\\tbegin//jr\\\\n\\\\t\\\\t\\\\t\\\\tbranch<=1; npcop<=`npc_reg; extop<=0; regdst<=0; otherctrl<=0; aluop<=0; \\\\n\\\\t\\\\t\\\\t\\\\talusrc=0; memwrite<=0; memtoreg<=0; regwrite<=0;\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\n\\\\t\\\\telse if(op==`addiu||op==`addi)\\\\n\\\\t\\\\t\\\\tbegin//addiu addi \\\\n\\\\t\\\\t\\\\t\\\\tbranch<=0; npcop<=0; extop<=`ext_sign; regdst<=`regdst_rt; otherctrl<=`oth_ext; aluop<=`alu_add; \\\\n\\\\t\\\\t\\\\t\\\\talusrc<=`alusrc_oth; memwrite<=0; memtoreg<=`memtoreg_ao; regwrite<=1;\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\telse if(op==`lw||op==`lh||op==`lhu||op==`lb||op==`lbu)\\\\n\\\\t\\\\t\\\\tbegin//lw lh lhu lb lbu\\\\n\\\\t\\\\t\\\\t\\\\tbranch<=0; npcop<=0; extop<=`ext_sign; regdst<=`regdst_rt; otherctrl<=`oth_ext; aluop<=`alu_add; \\\\n\\\\t\\\\t\\\\t\\\\talusrc<=`alusrc_oth; memwrite<=0; memtoreg<=`memtoreg_dr; regwrite<=1;\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\telse if(op==`sw||op==`sb||op==`sh)\\\\n\\\\t\\\\t\\\\tbegin//sw sb sh\\\\n\\\\t\\\\t\\\\t\\\\tbranch<=0; npcop<=0; extop<=`ext_sign; regdst<=0; otherctrl<=`oth_ext; aluop<=`alu_add; \\\\n\\\\t\\\\t\\\\t\\\\talusrc<=`alusrc_oth; memwrite<=1; memtoreg<=0; regwrite<=0;\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\telse if(op==`special&&rs==0&&(funct==`sll_funct||funct==`sra_funct||funct==`srl_funct))\\\\n\\\\t\\\\t\\\\tbegin//sll sra srl\\\\n\\\\t\\\\t\\\\t\\\\tbranch<=0; npcop<=0; extop<=0; regdst<=`regdst_rd; otherctrl<=0; \\\\n\\\\t\\\\t\\\\t\\\\talusrc<=`alusrc_rd2; memwrite<=0; memtoreg<=`memtoreg_ao; regwrite<=1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tif(funct==`sll_funct) aluop<=`alu_sll;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\telse if(funct==`srl_funct) aluop<=`alu_srl;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\telse if(funct==`sra_funct) aluop<=`alu_sra;\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\telse if(op==`special&&shamt==0&&(funct==`sllv_funct||funct==`srlv_funct||funct==`srav_funct))\\\\n\\\\t\\\\t\\\\tbegin//sllv srlv srav\\\\n\\\\t\\\\t\\\\t\\\\tbranch<=0; npcop<=0; extop<=0; regdst<=`regdst_rd; otherctrl<=0; \\\\n\\\\t\\\\t\\\\t\\\\talusrc<=`alusrc_rd2; memwrite<=0; memtoreg<=`memtoreg_ao; regwrite<=1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tif (funct==`sllv_funct) aluop<=`alu_sllv;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\telse if(funct==`srlv_funct) aluop<=`alu_srlv;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\telse if(funct==`srav_funct) aluop<=`alu_srav;\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\telse if(op==`special&&shamt==0&&(funct==`slt_funct||funct==`sltu_funct))\\\\n\\\\t\\\\t\\\\tbegin//slt sltu\\\\n\\\\t\\\\t\\\\t\\\\tbranch<=0; npcop<=0; extop<=0; regdst<=`regdst_rd; otherctrl<=0; \\\\n\\\\t\\\\t\\\\t\\\\talusrc<=`alusrc_rd2; memwrite<=0; memtoreg<=`memtoreg_ao; regwrite<=1;\\\\n\\\\t\\\\t\\\\t\\\\tif(funct==`slt_funct) aluop<=`alu_slt;\\\\n\\\\t\\\\t\\\\t\\\\telse if(funct==`sltu_funct) aluop<=`alu_sltu;\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\telse if(op==`slti||op==`sltiu)\\\\n\\\\t\\\\t\\\\tbegin//slti sltiu\\\\n\\\\t\\\\t\\\\t\\\\tbranch<=0; npcop<=0; extop<=`ext_sign; regdst<=`regdst_rt; otherctrl<=`oth_ext; \\\\n\\\\t\\\\t\\\\t\\\\talusrc<=`alusrc_oth; memwrite<=0; memtoreg<=`memtoreg_ao; regwrite<=1;\\\\n\\\\t\\\\t\\\\t\\\\tif(op==`slti) aluop<=`alu_slt;\\\\n\\\\t\\\\t\\\\t\\\\telse if(op==`sltiu) aluop<=`alu_sltu;\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\telse if(op==`beq||op==`bne\\\\n\\\\t\\\\t ||((op==`bgtz||op==`blez)&&rt==0)\\\\n\\\\t\\\\t ||op==`bgezbltz)\\\\n\\\\t\\\\t\\\\tbegin//beq bgtz blez bgez bltz bne\\\\n\\\\t\\\\t\\\\t\\\\tbranch<=1; npcop<=`npc_16; extop<=`ext_sign; regdst<=0; otherctrl<=0; aluop<=0; \\\\n\\\\t\\\\t\\\\t\\\\talusrc<=0; memwrite<=0; memtoreg<=0; regwrite<=0;\\\\n\\\\t\\\\t\\\\tend\\\\t\\\\n\\\\t\\\\telse if(op==`lui)\\\\n\\\\t\\\\t\\\\tbegin//lui\\\\n\\\\t\\\\t\\\\t\\\\tbranch<=0; npcop<=0; extop<=`ext_lui; regdst<=`regdst_rt; otherctrl<=`oth_ext; aluop<=`alu_oth; \\\\n\\\\t\\\\t\\\\t\\\\talusrc<=`alusrc_oth; memwrite<=0; memtoreg<=`memtoreg_ao; regwrite<=1;\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\telse if(op==`jal)\\\\n\\\\t\\\\t\\\\tbegin//jal\\\\n\\\\t\\\\t\\\\t\\\\tbranch<=1; npcop<=`npc_26; extop<=0; regdst<=`regdst_31; otherctrl<=0; aluop<=0; \\\\n\\\\t\\\\t\\\\t\\\\talusrc<=0; memwrite<=0; memtoreg<=`memtoreg_pc; regwrite<=1;\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\telse if (op==`j)\\\\n\\\\t\\\\t\\\\tbegin//j\\\\n\\\\t\\\\t\\\\t\\\\tbranch<=1; npcop<=`npc_26; extop<=0; regdst<=0; otherctrl<=0; aluop<=0; \\\\n\\\\t\\\\t\\\\t\\\\talusrc=0; memwrite<=0; memtoreg<=0; regwrite<=0;\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\telse if(op==`special&&funct==`jalr_funct&&shamt==0)\\\\n\\\\t\\\\t\\\\tbegin//jalr\\\\n\\\\t\\\\t\\\\t\\\\tbranch<=1; npcop<=`npc_reg; extop<=0; regdst<=`regdst_rd; otherctrl<=0; aluop<=0; \\\\n\\\\t\\\\t\\\\t\\\\talusrc<=0; memwrite<=0; memtoreg<=`memtoreg_pc; regwrite<=1;\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\telse if(instr==`eret)\\\\n\\\\t\\\\t\\\\tbegin//eret\\\\n\\\\t\\\\t\\\\t\\\\tbranch<=1; npcop<=`npc_epc; extop<=0; regdst<=0; otherctrl<=0; aluop<=0; \\\\n\\\\t\\\\t\\\\t\\\\talusrc<=0; memwrite<=0; memtoreg<=0; regwrite<=0;\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\telse if(op==`cop0&&rs==`mfc0_rs&&instr[10:0]==0)\\\\n\\\\t\\\\t\\\\tbegin//mfc0\\\\n\\\\t\\\\t\\\\t\\\\tbranch<=0; npcop<=0; extop<=0; regdst<=`regdst_rt; otherctrl<=0; aluop<=0; \\\\n\\\\t\\\\t\\\\t\\\\talusrc<=0; memwrite<=0; memtoreg<=`memtoreg_dr; regwrite<=1;\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\telse if(op==`cop0&&rs==`mtc0_rs&&instr[10:0]==0)\\\\n\\\\t\\\\t\\\\tbegin//mtc0\\\\n\\\\t\\\\t\\\\t\\\\tbranch<=0; npcop<=0; extop<=0; regdst<=0; otherctrl<=0; aluop<=0; \\\\n\\\\t\\\\t\\\\t\\\\talusrc<=0; memwrite<=0; memtoreg<=0; regwrite<=0;\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\telse if(op==`special&&instr[15:6]==0&&(funct==`mult_funct||funct==`multu_funct||funct==`div_funct||funct==`divu_funct))\\\\n\\\\t\\\\t\\\\tbegin//mult multu div divu\\\\n\\\\t\\\\t\\\\t\\\\tbranch<=0; npcop<=0; extop<=0; regdst<=0; otherctrl<=0; aluop<=0; \\\\n\\\\t\\\\t\\\\t\\\\talusrc<=`alusrc_rd2; memwrite<=0; memtoreg<=0; regwrite<=0;\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\telse if(op==`special &&(funct==`mfhi_funct||funct==`mflo_funct) )\\\\n\\\\t\\\\t\\\\tbegin//mfhi mflo\\\\n\\\\t\\\\t\\\\tdebug=15;\\\\n\\\\t\\\\t\\\\t\\\\tbranch<=0; npcop<=0; extop<=0; regdst<=`regdst_rd; otherctrl<=0; aluop<=0; \\\\n\\\\t\\\\t\\\\t\\\\talusrc<=`alusrc_rd2; memwrite<=0; memtoreg<=`memtoreg_ao; regwrite<=1;\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\telse if(op==`special &&(funct==`mthi_funct || funct ==`mtlo_funct))\\\\n\\\\t\\\\t\\\\tbegin//mtli mtlo\\\\n\\\\t\\\\t\\\\tdebug=16;\\\\n\\\\t\\\\t\\\\t\\\\tbranch<=0; npcop<=0; extop<=0; regdst<=0; otherctrl<=0; aluop<=0; \\\\n\\\\t\\\\t\\\\t\\\\talusrc<=0; memwrite<=0; memtoreg<=0; regwrite<=0;\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\telse \\\\n\\\\t\\\\t\\\\tbegin//default\\\\n\\\\t\\\\t\\\\t\\\\tbranch<=0; npcop<=0; extop<=0; regdst<=0; otherctrl<=0; aluop<=0; \\\\n\\\\t\\\\t\\\\t\\\\talusrc<=0; memwrite<=0; memtoreg<=0; regwrite<=0;\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\tend\\\\n\\\\n\\\\nendmodule']
["module Adder64b_mod (\\\\n input signed [63:0] A, B,\\\\n input SUB,\\\\n output COUT,\\\\n output signed [63:0] S\\\\n);\\\\n wire [63:0] C;\\\\n wire C1, C2, C3, C4, C5, C6, C7;\\\\n\\\\n /* XOR entre cada bit de B e o SUB, respons\\\\u00e1vel por complementar B caso SUB = 1*/\\\\n assign C = B ^ {64{SUB}};\\\\n\\\\n /* Sequencia de Carry Look-Ahead Adders de 8 bits, interligados de modo Ripple Carry */\\\\n CLAAdder8b U7_0 (.A(A[7:0]), .B(C[7:0]), .CIN(SUB), .S(S[7:0]), .COUT(C1)); // Sinal SUB ligado diretamente no CIN, para somar 1 do 2's complement caso SUB = 1 \\\\n CLAAdder8b U15_8 (.A(A[15:8]), .B(C[15:8]), .CIN(C1), .S(S[15:8]), .COUT(C2));\\\\n CLAAdder8b U23_16 (.A(A[23:16]), .B(C[23:16]), .CIN(C2), .S(S[23:16]), .COUT(C3));\\\\n CLAAdder8b U31_24 (.A(A[31:24]), .B(C[31:24]), .CIN(C3), .S(S[31:24]), .COUT(C4));\\\\n CLAAdder8b U39_32 (.A(A[39:32]), .B(C[39:32]), .CIN(C4), .S(S[39:32]), .COUT(C5));\\\\n CLAAdder8b U47_40 (.A(A[47:40]), .B(C[47:40]), .CIN(C5), .S(S[47:40]), .COUT(C6));\\\\n CLAAdder8b U55_48 (.A(A[55:48]), .B(C[55:48]), .CIN(C6), .S(S[55:48]), .COUT(C7));\\\\n CLAAdder8b U63_56 (.A(A[63:56]), .B(C[63:56]), .CIN(C7), .S(S[63:56]), .COUT(COUT));\\\\n \\\\nendmodule"]
['module top_seg7(rst, clk, seg1, seg2, seg3, seg4,seg5, seg6);\\\\n input rst, clk;\\\\n\\\\n output wire[6:0] seg1;\\\\n output wire[6:0] seg2;\\\\n output wire[6:0] seg3;\\\\n output wire[6:0] seg4;\\\\n output wire[6:0] seg5;\\\\n output wire[6:0] seg6;\\\\n reg[3:0] digit1;\\\\n reg[3:0] digit2;\\\\n wire[3:0] digit3;\\\\n wire[3:0] digit4;\\\\n wire[3:0] digit5;\\\\n wire[3:0] digit6;\\\\n \\\\n wire[7:0] long_digit1;\\\\n\\\\n wire[31:0] out_pc;\\\\n wire[31:0] writedata;\\\\n reg[6:0] pc;\\\\n \\\\n bcd v1(pc,long_digit1);\\\\n bcd_4digit v2(writedata[15:0],digit3, digit4, digit5, digit6);\\\\n \\\\n wire out_clk;\\\\n \\\\n // 50MHz -> 1Hz divide\\\\n clk_dll u0(rst, clk, out_clk); \\\\n \\\\n // counter \\\\n MIPS w1(clk, rst,out_pc, writedata);\\\\n counter u1(rst, out_clk, digit); \\\\n \\\\n // 7-segment decoder \\\\n seg7 u2(digit1, seg1);\\\\n seg7 u3(digit2, seg2);\\\\n seg7 u4(digit3, seg3);\\\\n seg7 u5(digit4, seg4);\\\\n seg7 u6(digit5, seg5);\\\\n seg7 u7(digit6, seg6);\\\\n \\\\n\\\\n \\\\n always@(*)\\\\n begin\\\\n\\\\tpc = out_pc[6:0];\\\\n\\\\tdigit1 = long_digit1[7:4];\\\\n\\\\tdigit2 = long_digit1[3:0];\\\\n\\\\n end\\\\n \\\\nendmodule']
["module optimizedSourceFIRfilter(aclk, s_axis_data_tvalid, s_axis_data_tdata, \\\\n s_axis_data_tready, m_axis_data_tvalid, m_axis_data_tdata);\\\\n \\\\n input aclk, s_axis_data_tvalid;\\\\n input [15:0] s_axis_data_tdata;\\\\n output s_axis_data_tready, m_axis_data_tvalid;\\\\n output [15:0] m_axis_data_tdata;\\\\n \\\\n \\\\n \\\\n reg signed [15:0] coefficient [18:0];\\\\n\\\\n\\\\t reg signed [15:0] b[17:0];\\\\n reg signed [15:0] result;\\\\n reg signed [31:0] temp_result;\\\\n reg valid;\\\\n\\\\n reg [4:0] i;\\\\n \\\\n\\\\t initial begin\\\\n\\\\t temp_result=0;\\\\n\\\\t coefficient [0]=16'd26;\\\\n\\\\t coefficient [1]=16'd270;\\\\n\\\\t coefficient [2]=16'd963;\\\\n\\\\t coefficient [3]=16'd2424;\\\\n\\\\t coefficient [4]=16'd4869;\\\\n\\\\t coefficient [5]=16'd8259;\\\\n\\\\t coefficient [6]=16'd12194;\\\\n\\\\t coefficient [7]=16'd15948;\\\\n\\\\t coefficient [8]=16'd18666;\\\\n\\\\t coefficient [9]=16'd19660;\\\\n\\\\t coefficient [10]=16'd18666;\\\\n\\\\t coefficient [11]=16'd15948;\\\\n\\\\t coefficient [12]=16'd12194;\\\\n\\\\t coefficient [13]=16'd8259;\\\\n\\\\t coefficient [14]=16'd4869;\\\\n\\\\t coefficient [15]=16'd2424;\\\\n\\\\t coefficient [16]=16'd963;\\\\n\\\\t coefficient [17]=16'd270;\\\\n\\\\t coefficient [18]=16'd26;\\\\n\\\\t b[0]=0;b[1]=0;b[2]=0;b[3]=0;b[4]=0;b[5]=0;b[6]=0;b[7]=0;b[8]=0;b[9]=0;\\\\n\\\\t b[10]=0;b[11]=0;b[12]=0;b[13]=0;b[14]=0;b[15]=0;b[16]=0;b[17]=0;\\\\n\\\\t end\\\\n\\\\t \\\\n\\\\t reg [31:0] mult_result[18:0];\\\\n \\\\n\\\\t wire temp;\\\\n\\\\t assign temp=aclk && s_axis_data_tvalid;\\\\n always @(posedge temp) begin\\\\n valid <= 0;\\\\n\\\\t\\\\t\\\\t#5;\\\\n // if (s_axis_data_tvalid) begin\\\\n //temp_result = s_axis_data_tdata * coefficient[0];\\\\n mult_result[0] = s_axis_data_tdata * coefficient[0];\\\\n \\\\n for ( i = 1; i <= 18; i = i + 1) begin\\\\n //temp_result = temp_result + b[i - 1] * coefficient[i];\\\\n mult_result[i] = b[i - 1] * coefficient[i];\\\\n \\\\n end\\\\n \\\\n for ( i = 17; i >= 1; i = i - 1) begin\\\\n b[i] <= b[i - 1];\\\\n end\\\\n \\\\n b[0] <= s_axis_data_tdata;\\\\n \\\\n //result <= temp_result[15:0];\\\\n \\\\n //valid <= 1;\\\\n // end\\\\n end\\\\n \\\\n \\\\n always @(posedge clk) begin\\\\n temp_result = 32'b0;\\\\n for (i = 0; i <= 18; i = i + 1) begin\\\\n temp_result = temp_result + mult_result[i];\\\\n end\\\\n \\\\n result <= temp_result[15:0];\\\\n valid <= 1;\\\\n end\\\\n\\\\t \\\\n \\\\n assign s_axis_data_tready = valid;\\\\n assign m_axis_data_tvalid = valid;\\\\n assign m_axis_data_tdata = result;\\\\nendmodule"]
["module ppc(y,x,rst,clk,a,b,c,d);\\\\n\\\\ninput [63:0][7:0]x;\\\\ninput [63:0] a,b;\\\\ninput rst,clk;\\\\n\\\\nwire [63:0][7:0]reg1,reg2,reg3,reg4,reg5,reg6;\\\\nwire [63:0] w_6,w_7,w_8,w_9,w_10,w_11,w_12,w_13,w_14,w_15,w_16,w_17; // WIRES FOR INPUTS A,B TO DFF\\\\nwire [63:0][7:0] w_1,w_2,w_3,w_4,w_5,w_18; //WIRES FOR K P G \\\\n\\\\noutput [63:0][7:0] y;\\\\noutput [63:0] c,d;\\\\n\\\\n\\\\ndff_lvl m_c1(x,rst,clk,reg1,w_6,w_7,a,b); //pipeline-11\\\\nlvl m_m1(w_1,reg1,3'd0);\\\\n\\\\ndff_lvl m_c2(w_1,rst,clk,reg2,w_8,w_9,w_6,w_7); //pipeline-12\\\\nlvl m_m2(w_2,reg2,3'd1);\\\\n\\\\ndff_lvl m_c3(w_2,rst,clk,reg3,w_10,w_11,w_8,w_9); //pipeline-13\\\\nlvl m_m3(w_3,reg3,3'd2);\\\\n\\\\ndff_lvl m_c4(w_3,rst,clk,reg4,w_12,w_13,w_10,w_11); //pipeline-14\\\\nlvl m_m4(w_4,reg4,3'd3);\\\\n\\\\ndff_lvl m_c5(w_4,rst,clk,reg5,w_14,w_15,w_12,w_13); //pipeline-15\\\\nlvl m_m5(w_5,reg5,3'd4);\\\\n\\\\ndff_lvl m_c6(w_5,rst,clk,reg6,w_16,w_17,w_14,w_15); //pipeline-16\\\\nlvl m_m6(w_18,reg6,3'd5);\\\\n\\\\ndff_lvl m_c7(w_18,rst,clk,y,c,d,w_16,w_17); //pipeline-17\\\\n\\\\nendmodule"]
["module Micro_Computer (\\\\n clk,sc,AC, DR,IR,ram,PC, AR,E\\\\n);\\\\ninput wire clk;\\\\n\\\\n// Signals for control unit\\\\nwire [7:0] T, D, B;\\\\nwire LDAC, CLRAC, INRAC, LDAR, INRAR, LDDR, INRDR, LDIR, INRPC, CLRSC,LDPC,read,write;\\\\nwire [2:0]s;\\\\nwire AND, ADD, LDA, STA, BUN, BSA, ISZ, CMA, CLA, CIL, CIR;\\\\n\\\\n// Signals for adder and logic unit and CB \\\\nwire [2:0] count;\\\\nwire [7:0]ACData,OUT;\\\\n\\\\n//ouptut\\\\noutput [7:0] AC, DR,IR,ram;\\\\noutput [3:0] PC, AR;\\\\nreg cin;\\\\noutput E;\\\\noutput [7:0] sc;\\\\n\\\\n\\\\n\\\\n//wires to link the modules\\\\nwire[7:0] ac_wire,dr_wire,ir_wire,ram_wire;\\\\nwire e_wire;\\\\nwire[3:0] pc_wire,ar_wire;\\\\n\\\\ninitial begin\\\\n cin=0;\\\\nend\\\\n\\\\n\\\\nassign AC=ac_wire;\\\\nassign DR=dr_wire;\\\\nassign IR=ir_wire;\\\\nassign ram=ram_wire;\\\\nassign PC=pc_wire;\\\\nassign AR=ar_wire;\\\\nassign E=e_wire;\\\\nassign sc=T;\\\\n\\\\n\\\\n\\\\n\\\\n// initial begin\\\\n// AC = 8'h00; // Initial value for ac\\\\n// DR = 8'h00; // Initial value for dr\\\\n// IR = 8'h00; // Initial value for ir\\\\n// PC = 4'h0; // Initial value for pc\\\\n// AR = 4'h0; // Initial value for ar\\\\n// cin=0;\\\\n// sc=0;\\\\n// ram=0;\\\\n// end\\\\n\\\\n\\\\n\\\\n// Output register assignments\\\\n // always @(*) begin\\\\n // AC <= ac_wire;\\\\n // DR <= dr_wire;\\\\n // IR <= ir_wire;\\\\n // ram <= ram_wire;\\\\n // PC <= pc_wire;\\\\n // AR <= ar_wire;\\\\n // E <= e_wire;\\\\n // sc<=T;\\\\n // end\\\\n\\\\n\\\\n\\\\n\\\\n\\\\n// sequence Counter\\\\nSequence_Counter3Bit2 counter (\\\\n .clk(clk),\\\\n .reset(CLRSC),\\\\n .count(count)\\\\n);\\\\n\\\\nDecoder3x8 decoder (\\\\n .A(count),\\\\n .Y(T)\\\\n);\\\\n\\\\n\\\\nIR_Reg ir (\\\\n .LD(LDIR),\\\\n .clk(clk),\\\\n .in(OUT),\\\\n .out(ir_wire)\\\\n);\\\\n\\\\n\\\\n// to get D\\\\n\\\\nDecoder3x8 d2(\\\\n.A(ir_wire[6:4]), \\\\n.Y(D)\\\\n\\\\n);\\\\n\\\\n\\\\n// CU\\\\nControlUnit CU (\\\\n .T(T),\\\\n .D(D),\\\\n .I(ir_wire[7]),\\\\n .B(ir_wire),\\\\n .LDAC(LDAC),\\\\n .CLRAC(CLRAC),\\\\n .INRAC(INRAC),\\\\n .LDAR(LDAR),\\\\n .INRAR(INRAR),\\\\n .ReadRam(read),\\\\n .WriteRam(write),\\\\n .LDDR(LDDR),\\\\n .INRDR(INRDR),\\\\n .LDIR(LDIR),\\\\n .INRPC(INRPC),\\\\n .CLRSC(CLRSC),\\\\n .LDPC(LDPC),\\\\n .s(s),\\\\n .AND(AND),\\\\n .ADD(ADD),\\\\n .LDA(LDA),\\\\n .STA(STA),\\\\n .BUN(BUN),\\\\n .BSA(BSA),\\\\n .ISZ(ISZ),\\\\n .CMA(CMA),\\\\n .CLA(CLA),\\\\n .CIL(CIL),\\\\n .CIR(CIR)\\\\n);\\\\n\\\\n\\\\n\\\\n// common bus\\\\nBUS_SEL CommonBus (\\\\n .AR(ar_wire),\\\\n .PC(pc_wire),\\\\n .DR(dr_wire),\\\\n .AC(ac_wire),\\\\n .IR(ir_wire),\\\\n .RAM(ram_wire),\\\\n .S(s),\\\\n .OUT(OUT)\\\\n);\\\\n\\\\n\\\\n// registers\\\\nAC_Reg ac (\\\\n .INR(INRAC),\\\\n .LD(LDAC),\\\\n .clk(clk),\\\\n .CLR(CLRAC),\\\\n .in(ACData),\\\\n .out(ac_wire)\\\\n);\\\\n\\\\nAR_Reg ar (\\\\n .INR(INRAR),\\\\n .LD(LDAR),\\\\n .clk(clk),\\\\n .in(OUT[3:0]),\\\\n .out(ar_wire)\\\\n);\\\\n\\\\n\\\\n// Adder&Logic\\\\nAdderAndLogic4 U1 (\\\\n .AND(AND), \\\\n .ADD(ADD), \\\\n .LDA(LDA), \\\\n .CMA(CMA), \\\\n .CIR(CIR), \\\\n .CIL(CIL), \\\\n .AC(ac_wire), \\\\n .DR(dr_wire), \\\\n .CIN(cin), \\\\n .E(e_wire), \\\\n .ACData(ACData) \\\\n);\\\\n \\\\n\\\\nDR_Reg dr (\\\\n .INR(INRDR),\\\\n .LD(LDDR),\\\\n .clk(clk),\\\\n // .CLR(CLRDR),\\\\n .in(OUT),\\\\n .out(dr_wire)\\\\n);\\\\n\\\\n\\\\n\\\\nPC_Reg pc (\\\\n .INR(INRPC),\\\\n .LD(LDPC),\\\\n .clk(clk),\\\\n .in(OUT[3:0]),\\\\n .out(pc_wire)\\\\n);\\\\n\\\\n// Memory\\\\nRAM_8x4bit RAM (\\\\n .clk(clk),\\\\n .read(read),\\\\n .write(write),\\\\n .addr(ar_wire),\\\\n .data_in(OUT)\\\\n ,.data_out(ram_wire)\\\\n);\\\\nendmodule"]
["module multi_cycle_cpu(clk,rst,rdata,pc,inst,alua,alub,alu,wmem,madr,wdata,state);\\\\n input [31:0] rdata;//\\\\u0221\\\\n input clk, rst;//\\\\u02b1\\\\ube34\\\\u03bb\\\\u017a\\\\n output [31:0] pc; //PC\\\\n output [31:0] inst; //\\\\u05b8\\\\n output [31:0] alua;//alu\\\\u04bb\\\\n output [31:0] alub;//alu\\\\n output [31:0] alu; //alu\\\\n output [31:0] madr; //\\\\u06b4\\\\u05b7\\\\n output [31:0] wdata;//\\\\u04aa\\\\u0434\\\\u06b4\\\\n output [2:0] state; //cpu\\\\u05f4\\\\u032c\\\\n output wmem; // \\\\u06b4\\\\u0434\\\\u02b9\\\\n// output reg [31:0] registers [0:31];\\\\n// output [31:0] regfile[31:0];\\\\n // \\\\u05b8\\\\u05b6\\\\n wire [5:0] op = inst[31:26];\\\\n wire [4:0] rs = inst[25:21];\\\\n wire [4:0] rt = inst[20:16];\\\\n wire [4:0] rd = inst[15:11];\\\\n wire [5:0] func = inst[5:0];\\\\n wire [15:0] imm = inst[15:0];\\\\n wire [25:0] addr = inst[25:0];\\\\n // \\\\u017a\\\\n wire [3:0] aluc;//ALU\\\\n wire [1:0] pcsrc;//PC\\\\u0534\\\\u0461\\\\n wire wreg;//\\\\u0134\\\\u0434\\\\u02b9\\\\n wire regrt;//\\\\u013f\\\\u0134\\\\n wire m2reg;//\\\\n wire [1:0] shift;//\\\\u03bb\\\\n wire [1:0] alusrcb;//alub\\\\n wire jal;\\\\n wire sext;//\\\\u0579\\\\n wire wpc;//pc\\\\u0434\\\\u02b9\\\\n wire wir;//ir\\\\u0434\\\\u02b9\\\\n wire iord;//\\\\u0461\\\\u06b4\\\\u05b7\\\\n wire selpc;//\\\\u0461PC\\\\n // \\\\u0368\\\\u00b7\\\\n wire [31:0] bpc;//\\\\u05a7\\\\u013f\\\\u05b7\\\\n wire [31:0] npc;//next PC\\\\n wire [31:0] qa;//\\\\u0134\\\\u02ff1\\\\n wire [31:0] qb;//\\\\u0134\\\\u02ff2\\\\n wire [31:0] alua;//ALUa\\\\n wire [31:0] alub;//ALUb\\\\n wire [15:0] alu_control;//alu\\\\u017a\\\\n wire [31:0] wd;//\\\\u0434\\\\u0134\\\\n wire [31:0] r; //ALU\\\\u06b4\\\\n wire [31:0] sa = {27'b0,inst[10:6]}; //\\\\u01ab\\\\n wire [15:0] s16 = {16{sext & inst[15]}};//16\\\\u03bb\\\\n wire [31:0] i32 = {s16,imm};//32\\\\u03bb\\\\n wire [31:0] dis = {s16[13:0],imm,2'b00}; //\\\\u05bc\\\\n wire [31:0] jpc = {pc[31:28],addr,2'b00};//\\\\u05ea\\\\u013f\\\\u05b7\\\\n wire [4:0] reg_dest; //\\\\u013f\\\\u0134RsRt\\\\n wire [4:0] wn = reg_dest | {5{jal}}; //\\\\u0434\\\\u0134\\\\n wire z; //0\\\\u05be\\\\n wire [31:0] rega; //\\\\u0134a\\\\n wire [31:0] regb; //\\\\u0134b\\\\n wire [31:0] regc; //\\\\u0134c\\\\n wire [31:0] data; //DR\\\\n wire [31:0] opa; //sa\\\\u0134a\\\\n// reg [31:0] registers [0:31];\\\\n// parameter [2:0] IDLE = 3'b000,\\\\n// IF = 3'b001,\\\\n// ID = 3'b010,\\\\n// EXE = 3'b011,\\\\n// MEM = 3'b100,\\\\n// WB = 3'b101;\\\\n // \\\\u07b8\\\\u013c\\\\u0134\\\\u05b5\\\\u07fc\\\\u04aa\\\\u06b2\\\\u036c\\\\u05f4\\\\u032c\\\\u07b8\\\\n// always @(posedge clk or negedge rst) begin\\\\n// case (state)\\\\n// // \\\\u06b2\\\\u036c\\\\u05f4\\\\u032c\\\\u00b8\\\\u00bc\\\\u0134\\\\u05b5\\\\n// // \\\\u78ec\\\\u0434\\\\u063d\\\\u05f6\\\\u03b8\\\\u00bc\\\\u0134\\\\u05b5\\\\n// WB: begin\\\\n// if (wreg) begin\\\\n// registers[wn] <= wd;\\\\n// end\\\\n// end\\\\n// // \\\\u05f4\\\\u032c\\\\u0138\\\\u07fc\\\\n// default: begin\\\\n// // \\\\u012c\\\\u00a3\\\\u03ba\\\\u07b8\\\\n// end\\\\n// endcase\\\\n// end\\\\n // \\\\u0123\\\\u02b5\\\\n //\\\\u01b5\\\\u052a\\\\n cu control_unit (op,func,z,clk,rst,wpc,wir,wmem,wreg,iord,\\\\n regrt,m2reg,aluc,shift,selpc,alusrcb,\\\\n pcsrc,jal,sext,state);\\\\n //PC\\\\u0134\\\\n rege32 ip (npc,clk,rst,wpc,pc);\\\\n //\\\\u05b8\\\\u0134\\\\n rege32 ir (rdata,clk,rst,wir,inst); \\\\n //\\\\u077c\\\\u0134\\\\n reg32 dr (rdata,clk,rst,data);\\\\n //\\\\u0134abc\\\\n reg32 reg_a (qa, clk,rst,rega);\\\\n reg32 reg_b (qb, clk,rst,regb);\\\\n reg32 reg_c (alu,clk,rst,regc);\\\\n //\\\\u0461sa\\\\u07fc\\\\u0134a\\\\n //\\\\u03bb\\\\u02b1\\\\u01ab\\\\n //shift[1]==1,\\\\u0221regfile\\\\u04e6\\\\u05b5\\\\u0175sa\\\\n// mux2x32 regsa();\\\\n //shift[1] sa<=qa\\\\n mux4x32 aorsa (rega,sa,rega,rega,shift,opa);\\\\n\\\\n //aluabalu\\\\n mux2x32 alu_a (opa,pc,selpc,alua);\\\\n mux4x32 alu_b (regb,32'h4,i32,dis,alusrcb,alub);\\\\n mux2x32 alu_m (regc,data,m2reg,r);\\\\n //\\\\u00f4\\\\u05b7\\\\n mux2x32 mem_a (pc,regc,iord,madr);\\\\n //\\\\u04e3rpc\\\\n mux2x32 link (r,pc,jal,wd);\\\\n //reg\\\\u0434\\\\u0461\\\\u0461\\\\u0434rdrt\\\\n mux2x5 reg_wn (rd,rt,regrt,reg_dest);\\\\n //PC\\\\u05b5\\\\n mux4x32 nextpc(alu,regc,qa,jpc,pcsrc,npc);\\\\n //\\\\u0134\\\\n regfile rf (rs,rt,wd,wn,wreg,clk,rst,qa,qb); \\\\n //ALU\\\\n alu alunit (alua,alub,aluc,alu,z);\\\\n //\\\\n decoder4x16 decoder(aluc,alu_control);\\\\n //\\\\u0434\\\\u06b4\\\\n assign wdata = regb;\\\\nendmodule"]
["module cpu_dataflow(\\\\ninput clk, rst,\\\\ninput [31:0]Inst, MemOut, RegWriteData,\\\\noutput [31:0]pc, Read2, ALUOut,\\\\noutput [1:0]MemWrite\\\\n);\\\\n\\\\nwire [1:0]RegDst, NPCOp, MemtoReg;\\\\nwire [2:0]RegWrite;\\\\nwire ALUsrc1, ALUsrc2, EXTOp;\\\\nwire [3:0]ALUOp;\\\\nwire Zero,Sign,BranchZ;\\\\nwire [4:0]WriteReg;\\\\nwire [31:0]ExtImm;\\\\nwire [31:0]Read1, Jraddr;\\\\nwire shamt;\\\\nwire [31:0]ALUa;\\\\nwire [31:0]nextpc;\\\\nwire [31:0]ALUbb;\\\\nwire [31:0]ALUb;\\\\ncontrol_unit cu( Inst[31:26], Inst[5:0], Inst[20:16], Zero, Sign,\\\\n RegDst, RegWrite, NPCOp, MemWrite, MemtoReg, ALUsrc1, ALUsrc2, BranchZ, EXTOp, ALUOp);\\\\n\\\\nEXT extension( Inst[15:0], EXTOp, ExtImm);\\\\n\\\\nRF RegFile( clk, rst, RegWrite, Inst[25:21], Inst[20:16], WriteReg, RegWriteData, Read1, Read2, Inst[25:21], Jraddr);\\\\n\\\\nmux4_5 RegD( Inst[20:16], Inst[15:11], 5'd31, 5'd31, RegDst, WriteReg);\\\\nmux2_32 ALU_a( Read1, {27'b0,Inst[10:6]}, ALUsrc1, ALUa);\\\\nmux2_32 ALU_bb( Read2, ExtImm, ALUsrc2, ALUbb);\\\\nmux2_32 ALU_b( ALUbb, 32'b0, BranchZ, ALUb);\\\\nmux4_32 Mem2Reg( ALUOut, MemOut, pc+4, 32'b0, MemtoReg, RegWriteData);\\\\n\\\\nalu ALU( ALUa, ALUb, ALUOp, ALUOut, Zero, Sign);\\\\nNPC NextPC( pc, NPCOp, Inst[25:0], nextpc, Jraddr);\\\\nPC PC_unit( clk, rst, nextpc, pc);\\\\n\\\\n\\\\nendmodule"]
["module not_tb();\\\\n\\\\nreg Clock, clear, tbIn;\\\\n// Bus input selection lines (device output -> bus input)\\\\nreg RFout, PCout, IRout, RYout, RZLOout, RZHIout, MARout, RHIout, RLOout;\\\\n// Register write enable lines\\\\nreg RFin, PCin, IRin, RYin, RZin, MARin, RHIin, RLOin;\\\\n// Register file selection line\\\\nreg [4:0]RFSelect;\\\\n\\\\nreg [31:0] BusMuxInTB;\\\\n\\\\n// ALU\\\\nreg start;\\\\nwire finished;\\\\nreg [5:0]opSelect;\\\\n// Memory\\\\nreg Read, MDRin, MDRout;\\\\nreg [31:0]Mdatain;\\\\n\\\\nreg IncPC; // Unused for now\\\\n\\\\nparameter Default = 4'b0000, Reg_load1a = 4'b0001, Reg_load1b = 4'b0010, Reg_load2a = 4'b0011,\\\\n Reg_load2b = 4'b0100, Reg_load3a = 4'b0101, Reg_load3b = 4'b0110, T0 = 4'b0111,\\\\n T1 = 4'b1000, T2 = 4'b1001, T3 = 4'b1010, T4 = 4'b1011, T5 = 4'b1100;\\\\n\\\\nreg [3:0] Present_state = Default;\\\\n\\\\nDataPath DP(\\\\n\\\\tClock, clear,\\\\n\\\\tRFout, PCout, IRout, RYout, RZLOout, RZHIout, MARout, RHIout, RLOout,\\\\n\\\\tRFin, PCin, IRin, RYin, RZin, MARin, RHIin, RLOin,\\\\t\\\\n\\\\tRFSelect,\\\\n // TODO: Remove these signals\\\\n\\\\ttbIn, BusMuxInTB,\\\\n\\\\n //alu signals\\\\n opSelect, start, finished,\\\\n // Data Signals\\\\n Read, MDRin, MDRout, Mdatain\\\\n);\\\\n\\\\n// Flag to pervent state transition while a waiting for a delay\\\\nreg holdState = 0;\\\\n\\\\n// Register holding expected value for comparison\\\\nreg [31:0]expectedValue = {32{1'dx}};\\\\n\\\\n// add test logic here\\\\ninitial\\\\nbegin\\\\n Clock = 0;\\\\n forever #10 Clock = ~ Clock;\\\\nend\\\\n\\\\nalways @(posedge Clock) // finite state machine; if clock rising-edge\\\\nbegin\\\\n\\\\t if(!holdState) begin\\\\n\\\\t\\\\t case (Present_state)\\\\n\\\\t\\\\t\\\\t Default : Present_state = Reg_load1a;\\\\n\\\\t\\\\t\\\\t Reg_load1a : Present_state = Reg_load1b;\\\\n\\\\t\\\\t\\\\t Reg_load1b : Present_state = Reg_load3a;\\\\n\\\\t\\\\t\\\\t Reg_load3a : Present_state = Reg_load3b;\\\\n\\\\t\\\\t\\\\t Reg_load3b : Present_state = T0;\\\\n\\\\t\\\\t\\\\t T0 : Present_state = T1;\\\\n\\\\t\\\\t\\\\t T1 : Present_state = T2;\\\\n\\\\t\\\\t\\\\t T2 : Present_state = T3;\\\\n\\\\t\\\\t\\\\t T3 : Present_state = T4;\\\\n\\\\t\\\\t endcase\\\\n\\\\t end\\\\nend\\\\n\\\\nalways @(Present_state) // do the required job in each state\\\\nbegin\\\\n\\\\t holdState = 1;\\\\n case (Present_state) // assert the required signals in each clock cycle\\\\n Default: begin\\\\n PCout <= 0; RZLOout <= 0; MDRout <= 0; // initialize the signals\\\\n RFout <= 0; MARin <= 0; RZin <= 0;\\\\n PCin <=0; MDRin <= 0; IRin <= 0; RYin <= 0;\\\\n IncPC <= 0; Read <= 0; opSelect <= 0;\\\\n RFin <= 0; Mdatain <= 32'h00000000;\\\\n end\\\\n Reg_load1a: begin\\\\n Mdatain <= 32'h00000012;\\\\n Read = 0; MDRin = 0; // the first zero is there for completeness\\\\n #10 Read <= 1; MDRin <= 1;\\\\n #15 Read <= 0; MDRin <= 0;\\\\n end\\\\n Reg_load1b: begin\\\\n #5 RFSelect <= 7;\\\\n #5 MDRout <= 1; RFin <= 1;\\\\n #15 MDRout <= 0; RFin <= 0; // initialize R7 with the value $12\\\\n end\\\\n Reg_load3a: begin\\\\n Mdatain <= 32'h00000018;\\\\n #10 Read <= 1; MDRin <= 1;\\\\n #15 Read <= 0; MDRin <= 0;\\\\n end\\\\n Reg_load3b: begin\\\\n #5 RFSelect <= 6;\\\\n #5 MDRout <= 1; RFin <= 1;\\\\n #15 MDRout <= 0; RFin <= 0; // initialize R6 with the value $18\\\\n end\\\\n T0: begin // see if you need to de-assert these signals\\\\n PCout <= 0; MARin <= 0; IncPC <= 0; RZin <= 0;\\\\n end\\\\n T1: begin\\\\n RZLOout <= 0; PCin <= 1; Read <= 1; MDRin <= 1;\\\\n Mdatain <= 32'h93B00000; // opcode for not R7, R6\\\\u201d\\\\n end\\\\n T2: begin\\\\n MDRout <= 1; IRin <= 1;\\\\n\\\\t\\\\t\\\\t#10 MDRout <= 0;\\\\n end\\\\n T3: begin\\\\n IRin <= 0;\\\\n RFSelect <= 7;\\\\n RFout <= 1; RYin <= 1;\\\\n opSelect <= 5'b00001; RZin <= 1;\\\\n end\\\\n T4: begin\\\\n #1 start <= 1; RYin <= 0; RFout <= 0;\\\\n #10 start <= 0;\\\\n\\\\t\\\\t\\\\tRFSelect <= 6;\\\\n RZLOout <= 1; RFin <= 1;\\\\n\\\\t\\\\t\\\\texpectedValue <= 32'hFFFFFFED;\\\\n end\\\\n endcase\\\\n\\\\tholdState = 0;\\\\n\\\\tend\\\\nendmodule"]
['module bit_counter (\\\\n data,\\\\n r\\\\n);\\\\n\\\\ninput [31:0] data;\\\\noutput [5:0] r;\\\\n\\\\n// the first layer is 16 half-adders, resulting in 16 2-bit results\\\\n// layer 2 is 8 2-bit adders, resulting in 8 3-bit results\\\\n// layer 3 is 4 3-bit adders, resulting in 4 4-bit results\\\\n// layer 4 is 2 4-bit adders, resulting in 2 5-bit results\\\\n// and then finally, we use a 5-bit adder, resulting in 6-bit result\\\\n\\\\nwire [15:0][1:0] layer1;\\\\nwire [7:0][2:0] layer2;\\\\nwire [3:0][3:0] layer3;\\\\nwire [2:0][4:0] layer4;\\\\n\\\\ngenvar i;\\\\nfor (i=0; i<16; i = i + 1) begin\\\\n half_adder t (.a(data[i*2]), .b(data[i*2+1]), .r(layer1[i][0]), .c(layer1[i][1]));\\\\nend\\\\nfor (i=0; i<8; i = i + 1) begin\\\\n assign layer2[i] = layer1[i*2] + layer1[i*2+1];\\\\nend\\\\nfor (i=0; i<4; i = i + 1) begin\\\\n assign layer3[i] = layer2[i*2] + layer2[i*2+1];\\\\nend\\\\nfor (i=0; i<2; i = i + 1) begin\\\\n assign layer4[i] = layer3[i*2] + layer3[i*2+1];\\\\nend\\\\nassign r = layer4[0] + layer4[1];\\\\n\\\\nendmodule']
["module topModule (Dados, clk, rst, Disp_RegA, Disp_RegB, Disp_Saida, Instrucao, fim, state, saida_regC);\\\\n\\\\ninput wire [3:0] Dados;\\\\ninput clk,rst,Instrucao;\\\\n\\\\noutput fim; \\\\noutput [6:0] Disp_RegA,Disp_RegB,Disp_Saida;\\\\noutput [3:0]state;\\\\noutput wire [4:0]saida_regC;\\\\n\\\\nwire [3:0] saidaA,saidaB;\\\\nwire [4:0]saidaSel;\\\\nwire Sel,EnB,EnA;\\\\nwire [1:0]Op, Op_Reg;\\\\nwire[4:0] saidaUla;\\\\n\\\\n\\\\n//module registrador (dados, clk, rst, hab, saida);\\\\nregistrador RA(Dados, clk, rst, EnA , saidaA);\\\\nregistrador RB(Dados, clk, rst, EnB , saidaB);\\\\n\\\\n//module mux (in0, in1, sel,saida);\\\\nmux M1({1'b0,saidaB}, saida_regC, Sel,saidaSel);\\\\n\\\\n//module display (Entrada, Hex);\\\\ndisplay D0 ({1'b0,saidaA}, Disp_RegA);\\\\ndisplay D1 ({1'b0,saidaB}, Disp_RegB);\\\\ndisplay D2 (saida_regC, Disp_Saida);\\\\n\\\\n//module regC (in,clk,rst,op_reg,saida);\\\\nregC rc (saidaUla,clk,rst,Op_Reg,saida_regC);\\\\n\\\\n//module ula (inA, inB, op, saida);\\\\nula U1({1'b0,saidaA}, saidaSel,Op,saidaUla);\\\\n\\\\n//module mealy (clk,instrucao,fim,enA,enB,op,op_Reg,sel,rst,state);\\\\nmealy Cn (clk,Instrucao,fim,EnA,EnB,Op,Op_Reg,Sel,rst,state);\\\\n\\\\n\\\\nendmodule"]
["module PC_Branch(clock, btns, btnu, btnd, btnr, btnl, new_count, a,b,c,d,e,ff,g,dp,an,led0,led1,led2,led3,led4,led5,led6,led7);\\\\n\\\\t input clock;\\\\n\\\\t input btns; // Synchronous reset; active low\\\\n\\\\t input btnu; // Only increment the counter when this signal is high\\\\n\\\\t input btnd;\\\\n\\\\t input btnr;\\\\n\\\\t input btnl; // When this signal is high, the counter loads new_count into the counter\\\\n\\\\t input [7:0] new_count; // New value to set the counter to\\\\n\\\\t \\\\n\\\\t\\\\n\\\\t output a;\\\\n\\\\t output b;\\\\n\\\\t output c;\\\\n\\\\t output d;\\\\n\\\\t output e;\\\\n\\\\t output ff;\\\\n\\\\t output g;\\\\n\\\\t output dp;\\\\n output [3:0] an;\\\\n\\\\t \\\\n\\\\t output reg led0;\\\\n\\\\t output reg led1;\\\\n\\\\t output reg led2;\\\\n\\\\t output reg led3;\\\\n\\\\t output reg led4;\\\\n\\\\t output reg led5;\\\\n\\\\t output reg led6;\\\\n\\\\t output reg led7;\\\\n\\\\t \\\\n\\\\t reg [15:0] count; // Output address of the program counter\\\\n\\\\t \\\\n\\\\t wire [3:0] first = count[3:0];\\\\n\\\\t wire [3:0] second = count[7:4];\\\\n\\\\t wire [3:0] third = count[11:8];\\\\n\\\\t wire [3:0] fourth = count[15:12];\\\\n\\\\t \\\\n\\\\t wire btns_o;\\\\n\\\\t wire btnl_o;\\\\n\\\\t wire btnr_o;\\\\n\\\\t wire btnd_o;\\\\n\\\\t wire btnu_o;\\\\n\\\\t \\\\n\\\\t debounce db1(clock, btns, btns_o);\\\\n\\\\t debounce db2(clock, btnl, btnl_o);\\\\n\\\\t debounce db3(clock, btnr, btnr_o);\\\\n\\\\t debounce db4(clock, btnd, btnd_o);\\\\n\\\\t debounce db5(clock, btnu, btnu_o);\\\\n\\\\t \\\\n\\\\t seven_segment_led ss(clock, 1'b0, first, second, third, fourth, a,b,c,d,e,ff,g,dp, an);\\\\n\\\\t\\\\n\\\\treg count_flag;\\\\n\\\\t \\\\n\\\\t reg [7:0] leftval=8'b00000000;\\\\n\\\\t\\\\treg [7:0] rightval = 8'b00000000;\\\\n\\\\t\\\\twire [15:0] finalval;\\\\n\\\\t\\\\treg kont = 1'b0;\\\\n\\\\t\\\\twire [15:0] countbef;\\\\n\\\\t\\\\tassign finalval = {leftval,rightval};\\\\n\\\\t\\\\t\\\\n\\\\t\\\\t\\\\n\\\\t\\\\twire clk_out;\\\\n\\\\t\\\\tclk_div clkk(clock, 1'b0, clk_out);\\\\n\\\\t\\\\t\\\\n\\\\t // Clocked operation\\\\n\\\\t always @(posedge clk_out) begin\\\\n\\\\t \\\\n\\\\t if(btns) begin // If the reset line is low, then zero the counter\\\\n\\\\t count <= 16'b0000000000000000;\\\\n\\\\t end\\\\n\\\\t \\\\n\\\\t else if(btnr_o) begin // If set is high, then load a new value into the counter\\\\n\\\\t rightval <= new_count;\\\\n\\\\t led0 <= new_count[0];\\\\n\\\\t led1 <= new_count[1];\\\\n\\\\t led2 <= new_count[2];\\\\n\\\\t led3 <= new_count[3];\\\\n\\\\t led4 <= new_count[4];\\\\n\\\\t led5 <= new_count[5];\\\\n\\\\t led6 <= new_count[6];\\\\n\\\\t led7 <= new_count[7];\\\\n\\\\t \\\\n\\\\t end\\\\n\\\\t \\\\n\\\\t else if(btnl_o) begin // If set is high, then load a new value into the counter\\\\n\\\\t leftval <= new_count;\\\\n\\\\t led0 <= new_count[0];\\\\n\\\\t led1 <= new_count[1];\\\\n\\\\t led2 <= new_count[2];\\\\n\\\\t led3 <= new_count[3];\\\\n\\\\t led4 <= new_count[4];\\\\n\\\\t led5 <= new_count[5];\\\\n\\\\t led6 <= new_count[6];\\\\n\\\\t led7 <= new_count[7];\\\\n\\\\t kont = 1;\\\\n\\\\t end\\\\n\\\\t else if(kont) begin\\\\n\\\\t \\\\n\\\\t count <= finalval;\\\\n\\\\t kont =0;\\\\n\\\\t end\\\\n\\\\t else if(btnu_o) begin // Otherwise, if increment is high, add one to the counter\\\\n\\\\t count_flag<=1;\\\\n\\\\t count <= count + 1;\\\\n\\\\t end\\\\n\\\\t \\\\n\\\\t else if(btnd_o) begin\\\\n\\\\t count_flag<=0;\\\\n\\\\t end\\\\n\\\\t \\\\n\\\\t else if(count_flag) begin\\\\n\\\\t count<=count+1;\\\\n\\\\t end\\\\n\\\\t \\\\n\\\\t end // END always\\\\n \\\\n\\\\t endmodule", "module seven_segment_led(clock,reset,in0,in1,in2,in3,a,b,c,d,e,f,g,dp,an);\\\\n input clock;\\\\n input reset;\\\\n input [3:0]in0;\\\\n\\\\t input [3:0]in1;\\\\n\\\\t input [3:0]in2;\\\\n\\\\t input [3:0]in3;\\\\n output a;\\\\n\\\\t output b;\\\\n\\\\t output c;\\\\n\\\\t output d;\\\\n\\\\t output e;\\\\n\\\\t output f;\\\\n\\\\t output g;\\\\n\\\\t output dp;\\\\n output [3:0] an;\\\\n \\\\n\\\\t \\\\n\\\\t \\\\n\\\\nlocalparam N1 = 18;\\\\n \\\\nreg [N1-1:0]count; //the 18 bit counter which allows us to multiplex at 1000Hz\\\\n \\\\nalways @ (posedge clock or posedge reset)\\\\n begin\\\\n if (reset)\\\\n count <= 0;\\\\n else\\\\n count <= count + 1;\\\\n end\\\\n \\\\nreg [6:0]sseg; //the 7 bit register to hold the data to output\\\\nreg [3:0]an_temp; //register for the 4 bit enable\\\\n \\\\nalways @ (*)\\\\n begin\\\\n case(count[N1-1:N1-2]) //using only the 2 MSB's of the counter \\\\n \\\\n 2'b00 : //When the 2 MSB's are 00 enable the fourth display\\\\n begin\\\\n sseg = in0;\\\\n an_temp = 4'b1110;\\\\n end\\\\n \\\\n 2'b01: //When the 2 MSB's are 01 enable the third display\\\\n begin\\\\n sseg = in1;\\\\n an_temp = 4'b1101;\\\\n end\\\\n \\\\n 2'b10: //When the 2 MSB's are 10 enable the second display\\\\n begin\\\\n sseg = in2;\\\\n an_temp = 4'b1011;\\\\n end\\\\n \\\\n 2'b11: //When the 2 MSB's are 11 enable the first display\\\\n begin\\\\n sseg = in3;\\\\n an_temp = 4'b0111;\\\\n end\\\\n endcase\\\\n end\\\\nassign an = an_temp;\\\\n \\\\n \\\\nreg [6:0] sseg_temp; // 7 bit register to hold the binary value of each input given\\\\n \\\\nalways @ (*)\\\\n begin\\\\n case(sseg)\\\\n 4'd0 : sseg_temp = 7'b1000000; //to display 0\\\\n 4'd1 : sseg_temp = 7'b1111001; //to display 1\\\\n 4'd2 : sseg_temp = 7'b0100100; //to display 2\\\\n 4'd3 : sseg_temp = 7'b0110000; //to display 3\\\\n 4'd4 : sseg_temp = 7'b0011001; //to display 4\\\\n 4'd5 : sseg_temp = 7'b0010010; //to display 5\\\\n 4'd6 : sseg_temp = 7'b0000010; //to display 6\\\\n 4'd7 : sseg_temp = 7'b1111000; //to display 7\\\\n 4'd8 : sseg_temp = 7'b0000000; //to display 8\\\\n 4'd9 : sseg_temp = 7'b0010000; //to display 9\\\\n\\\\t4'd10: sseg_temp = 7'b0001000;\\\\n\\\\t4'd11: sseg_temp = 7'b0000011;\\\\n\\\\t4'd12: sseg_temp = 7'b1000110;\\\\n\\\\t4'd13: sseg_temp = 7'b0100001;\\\\n\\\\t4'd14: sseg_temp = 7'b0000110;\\\\n\\\\t4'd15: sseg_temp = 7'b0001110;\\\\n default : sseg_temp = 7'b0111111; //dash\\\\n endcase\\\\n end\\\\nassign {g, f, e, d, c, b, a} = sseg_temp; //concatenate the outputs to the register, this is just a more neat way of doing this.\\\\n// I could have done in the case statement: 4'd0 : {g, f, e, d, c, b, a} = 7'b1000000; \\\\n// its the same thing.. write however you like it\\\\n \\\\nassign dp = 1'b1; //since the decimal point is not needed, all 4 of them are turned off\\\\n \\\\n \\\\nendmodule", "module debounce(clk,button_in,DB_out);\\\\n input clk;\\\\n //input n_reset,\\\\n input button_in;\\\\n output reg DB_out;\\\\n \\\\n\\\\t \\\\n\\\\t //// ---------------- internal constants --------------\\\\n\\\\tparameter N = 11 ;\\\\t\\\\t// (2^ (21-1) )/ 38 MHz = 32 ms debounce time\\\\n////---------------- internal variables ---------------\\\\n\\\\treg [N-1 : 0]\\\\tq_reg;\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t// timing regs\\\\n\\\\treg [N-1 : 0]\\\\tq_next;\\\\n\\\\treg DFF1, DFF2;\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t// input flip-flops\\\\n\\\\twire q_add;\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t// control flags\\\\n\\\\twire q_reset;\\\\n//// ------------------------------------------------------\\\\n\\\\n\\\\treg n_reset = 0;\\\\n////contenious assignment for counter control\\\\n\\\\tassign q_reset = (DFF1 ^ DFF2);\\\\t\\\\t// xor input flip flops to look for level chage to reset counter\\\\n\\\\tassign q_add = ~(q_reg[N-1]);\\\\t\\\\t\\\\t// add to counter when q_reg msb is equal to 0\\\\n\\\\t\\\\n//// combo counter to manage q_next\\\\t\\\\n\\\\talways @ ( q_reset, q_add, q_reg)\\\\n\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\tcase( {q_reset , q_add})\\\\n\\\\t\\\\t\\\\t\\\\t2'b00 :\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tq_next <= q_reg;\\\\n\\\\t\\\\t\\\\t\\\\t2'b01 :\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tq_next <= q_reg + 1;\\\\n\\\\t\\\\t\\\\t\\\\tdefault :\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tq_next <= { N {1'b0} };\\\\n\\\\t\\\\t\\\\tendcase \\\\t\\\\n\\\\t\\\\tend\\\\n\\\\t\\\\n//// Flip flop inputs and q_reg update\\\\n\\\\talways @ ( posedge clk )\\\\n\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\tif(n_reset == 1'b0)\\\\n\\\\t\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tDFF1 <= 1'b0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tDFF2 <= 1'b0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tq_reg <= { N {1'b0} };\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tn_reset <=1;\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\telse\\\\n\\\\t\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tDFF1 <= button_in;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tDFF2 <= DFF1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tq_reg <= q_next;\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\tend\\\\n\\\\t\\\\n//// counter control\\\\n\\\\talways @ ( posedge clk )\\\\n\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\tif(q_reg[N-1] == 1'b1)\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tDB_out <= DFF2;\\\\n\\\\t\\\\t\\\\telse\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tDB_out <= DB_out;\\\\n\\\\t\\\\tend\\\\n\\\\n\\\\tendmodule"]
["module alu(\\\\n input [31:0] aluin1,\\\\n input [31:0] aluin2,\\\\n output [31:0] aluout,\\\\n output [31:0] alu_addr_out,\\\\n input [3:0] aluCtrl\\\\n);\\\\n\\\\nwire [31:0] alu_add;\\\\nwire [31:0] alu_sub;\\\\nwire [31:0] alu_or;\\\\nwire [31:0] alu_and;\\\\nwire [31:0] alu_sll;\\\\nwire [31:0] alu_slt;\\\\nwire [31:0] alu_sltu;\\\\nwire [31:0] alu_xor;\\\\nwire [31:0] alu_srl;\\\\nwire [31:0] alu_sra;\\\\n\\\\nassign alu_add = ($signed(aluin1)) + ($signed(aluin2));\\\\nassign alu_sub = aluin1 - aluin2;\\\\nassign alu_or = aluin1 | aluin2;\\\\nassign alu_and = aluin1 & aluin2;\\\\nassign alu_sll = aluin1 << aluin2[4:0];\\\\nassign alu_sra = ($signed(aluin1)) >>> aluin2[4:0];//how?\\\\nassign alu_srl = aluin1 >> aluin2[4:0];\\\\nassign alu_xor = aluin1 ^ aluin2;\\\\nassign alu_sltu = (aluin1 < aluin2) ? 32'b1 : 32'b0;\\\\n\\\\nwire input_sign1 = aluin1[31];\\\\nwire input_sign2 = aluin2[31];\\\\n//wire [31:0] alu_sign1;\\\\n//wire [31:0] alu_sign2;\\\\n//assign alu_sign1 = (input_sign1 == 1) ? (32'hffffffff - aluin1) : aluin1;\\\\n//assign alu_sign2 = (input_sign2 == 1) ? (32'hffffffff - aluin2) : aluin2;\\\\nassign alu_slt = (input_sign1 == 1 && input_sign2 == 0) ? 32'b1 :\\\\n (input_sign1 == 0 && input_sign2 == 1) ? 32'b0 :\\\\n (input_sign1 == 1 && input_sign2 == 1 && aluin1 < aluin2) ? 32'b1 :\\\\n (input_sign1 == 1 && input_sign2 == 1 && aluin1 >= aluin2) ? 32'b0 :\\\\n (input_sign1 == 0 && input_sign2 == 0 && aluin1 >= aluin2) ? 32'b0 :\\\\n 32'b1;\\\\n\\\\nreg [31:0] aluout1;\\\\nreg [31:0] aluout2;\\\\n\\\\nalways @(*) begin\\\\n aluout1 = 32'b0;\\\\n case(aluCtrl)\\\\n `ALUCTRL_ADD: aluout1 = alu_add;\\\\n `ALUCTRL_OR: aluout1 = alu_or;\\\\n `ALUCTRL_SLL: aluout1 = alu_sll;\\\\n `ALUCTRL_SUB: aluout1 = alu_sub;\\\\n `ALUCTRL_SLT: aluout1 = alu_slt;\\\\n `ALUCTRL_SLTU: aluout1 = alu_sltu;\\\\n `ALUCTRL_XOR: aluout1 = alu_xor;\\\\n `ALUCTRL_AND: aluout1 = alu_and;\\\\n `ALUCTRL_SRL: aluout1 = alu_srl;\\\\n `ALUCTRL_SRA: aluout1 = alu_sra;\\\\n 4'b1111: aluout1 = aluin2;\\\\n default: aluout1 = 32'b0;\\\\n endcase\\\\nend\\\\n\\\\nalways @(*) begin\\\\n aluout2 <= alu_add;\\\\nend\\\\n\\\\nassign aluout = aluout1;\\\\nassign alu_addr_out = aluout2;\\\\n\\\\nendmodule"]
["module FPA(A,B,SUM,clk);\\\\n\\\\n\\\\tinput[31:0] A,B;\\\\n\\\\tinput clk;\\\\n\\\\n\\\\toutput[31:0] SUM;\\\\n\\\\n\\\\twire[31:0] OUT_EXPLARGE,OUT_EXPSMALL;\\\\n\\\\tcomparator_swap comp_swap(A,B,OUT_EXPLARGE,OUT_EXPSMALL,clk);\\\\n\\\\n\\\\t//4th clock cycle\\\\n\\\\twire[31:0] OUT_LARGE_FFOUT, OUT_SMALL_FFOUT;\\\\n\\\\tDFlipFlop32 OUT_LARGE_FF(OUT_EXPLARGE,clk,OUT_LARGE_FFOUT);\\\\n\\\\tDFlipFlop32 OUT_SMALL_FF(OUT_EXPSMALL,clk,OUT_SMALL_FFOUT);\\\\n\\\\n\\\\twire OUT_A_SIGN, OUT_B_SIGN;\\\\n\\\\twire[23:0] OUT_A_MANTISSA, OUT_B_MANTISSA;\\\\n\\\\twire[7:0] OUT_EXPONENT;\\\\n\\\\texponent_balance exp_balance(OUT_LARGE_FFOUT,OUT_SMALL_FFOUT,OUT_A_SIGN,OUT_A_MANTISSA,OUT_B_SIGN,OUT_B_MANTISSA,OUT_EXPONENT,clk);\\\\n\\\\n\\\\t//15th clock cycle\\\\n\\\\twire SIGNA_FFOUT,SIGNB_FFOUT;\\\\n\\\\twire[23:0] MANTISSA_FFOUT, MANTISSB_FFOUT;\\\\n\\\\twire[7:0] EXPONENT_FFOUT;\\\\n\\\\n\\\\tDFlipFlop2IN SIGN_FF(OUT_A_SIGN,OUT_B_SIGN,clk,SIGNA_FFOUT,SIGNB_FFOUT);\\\\n\\\\tDFlipFlop24 MANTISSA_FF(OUT_A_MANTISSA,clk,MANTISSA_FFOUT);\\\\n\\\\tDFlipFlop24 MANTISSB_FF(OUT_B_MANTISSA,clk,MANTISSB_FFOUT);\\\\n\\\\tDFlipFlop8 EXPONENT_FF(OUT_EXPONENT,clk,EXPONENT_FFOUT);\\\\n\\\\n\\\\n\\\\twire[31:0] SUM_SS;\\\\n\\\\tFP_SS_Adder FPSSAdder(SIGNA_FFOUT,MANTISSA_FFOUT,SIGNB_FFOUT,MANTISSB_FFOUT,EXPONENT_FFOUT,SUM_SS,clk);\\\\n\\\\n\\\\t//21st clock cycle\\\\n\\\\twire[31:0] SUM_SS_FFOUT;\\\\n\\\\tDFlipFlop32 SUM_SS_FF(SUM_SS,clk,SUM_SS_FFOUT);\\\\n\\\\n\\\\twire[31:0] SUM_DS;\\\\n\\\\tFF_DS_Adder FPDSAdder(SIGNA_FFOUT,MANTISSA_FFOUT,SIGNB_FFOUT,MANTISSB_FFOUT,EXPONENT_FFOUT,SUM_DS,clk);\\\\n\\\\n\\\\t//35 clock cycle\\\\n\\\\twire[31:0] SUM_DS_FFOUT;\\\\n\\\\tDFlipFlop32 SUM_DS_FF(SUM_DS,clk,SUM_DS_FFOUT);\\\\n\\\\n\\\\t/*PROPOGATE XOR OF SIGNS '16th to 35th' clock cycle -- start */\\\\n\\\\twire sign_xor = SIGNA_FFOUT^SIGNB_FFOUT;\\\\n\\\\n\\\\t//16th clock cycle\\\\n\\\\twire level16_signXOR;\\\\n\\\\tDFlipFlop level16_signXOR_FF(sign_xor,clk,level16_signXOR);\\\\n\\\\n\\\\t//17th clock cycle\\\\n\\\\twire level17_signXOR;\\\\n\\\\tDFlipFlop level17_signXOR_FF(level16_signXOR,clk,level17_signXOR);\\\\n\\\\n\\\\t//18th clock cycle\\\\n\\\\twire level18_signXOR;\\\\n\\\\tDFlipFlop level18_signXOR_FF(level17_signXOR,clk,level18_signXOR);\\\\n\\\\n\\\\t//19th clock cycle\\\\n\\\\twire level19_signXOR;\\\\n\\\\tDFlipFlop level19_signXOR_FF(level18_signXOR,clk,level19_signXOR);\\\\n\\\\n\\\\t//20th clock cycle\\\\n\\\\twire level20_signXOR;\\\\n\\\\tDFlipFlop level20_signXOR_FF(level19_signXOR,clk,level20_signXOR);\\\\n\\\\n\\\\t//21th clock cycle\\\\n\\\\twire level21_signXOR;\\\\n\\\\tDFlipFlop level21_signXOR_FF(level20_signXOR,clk,level21_signXOR);\\\\n\\\\n\\\\t//22th clock cycle\\\\n\\\\twire level22_signXOR;\\\\n\\\\tDFlipFlop level22_signXOR_FF(level21_signXOR,clk,level22_signXOR);\\\\n\\\\n\\\\t//23th clock cycle\\\\n\\\\twire level23_signXOR;\\\\n\\\\tDFlipFlop level23_signXOR_FF(level22_signXOR,clk,level23_signXOR);\\\\n\\\\n\\\\t//24th clock cycle\\\\n\\\\twire level24_signXOR;\\\\n\\\\tDFlipFlop level24_signXOR_FF(level23_signXOR,clk,level24_signXOR);\\\\n\\\\n\\\\t//25th clock cycle\\\\n\\\\twire level25_signXOR;\\\\n\\\\tDFlipFlop level25_signXOR_FF(level24_signXOR,clk,level25_signXOR);\\\\n\\\\n\\\\t//26th clock cycle\\\\n\\\\twire level26_signXOR;\\\\n\\\\tDFlipFlop level26_signXOR_FF(level25_signXOR,clk,level26_signXOR);\\\\n\\\\n\\\\t//27th clock cycle\\\\n\\\\twire level27_signXOR;\\\\n\\\\tDFlipFlop level27_signXOR_FF(level26_signXOR,clk,level27_signXOR);\\\\n\\\\n\\\\t//28th clock cycle\\\\n\\\\twire level28_signXOR;\\\\n\\\\tDFlipFlop level28_signXOR_FF(level27_signXOR,clk,level28_signXOR);\\\\n\\\\n\\\\t//29th clock cycle\\\\n\\\\twire level29_signXOR;\\\\n\\\\tDFlipFlop level29_signXOR_FF(level28_signXOR,clk,level29_signXOR);\\\\n\\\\n\\\\t//30th clock cycle\\\\n\\\\twire level30_signXOR;\\\\n\\\\tDFlipFlop level30_signXOR_FF(level29_signXOR,clk,level30_signXOR);\\\\n\\\\n\\\\t//31th clock cycle\\\\n\\\\twire level31_signXOR;\\\\n\\\\tDFlipFlop level31_signXOR_FF(level30_signXOR,clk,level31_signXOR);\\\\n\\\\n\\\\t//32th clock cycle\\\\n\\\\twire level32_signXOR;\\\\n\\\\tDFlipFlop level32_signXOR_FF(level31_signXOR,clk,level32_signXOR);\\\\n\\\\n\\\\t//33th clock cycle\\\\n\\\\twire level33_signXOR;\\\\n\\\\tDFlipFlop level33_signXOR_FF(level32_signXOR,clk,level33_signXOR);\\\\n\\\\n\\\\t//34th clock cycle\\\\n\\\\twire level34_signXOR;\\\\n\\\\tDFlipFlop level34_signXOR_FF(level33_signXOR,clk,level34_signXOR);\\\\n\\\\n\\\\t//35th clock cycle\\\\n\\\\twire level35_signXOR;\\\\n\\\\tDFlipFlop level35_signXOR_FF(level34_signXOR,clk,level35_signXOR);\\\\n\\\\t/*PROPOGATE XOR OF SIGNS '16th to 35th' clock cycle -- start */\\\\n\\\\n\\\\n\\\\t/*Propogate SUM_SS_FFOUT '22nd to 35th' clock cycle -- start */\\\\n\\\\t\\\\n\\\\t//22nd clock cycle\\\\n\\\\twire[31:0] level22_SUM_SS;\\\\n\\\\tDFlipFlop32 level22_SUMSS_FF(SUM_SS_FFOUT,clk,level22_SUM_SS);\\\\n\\\\n\\\\t//23 clock cycle\\\\n\\\\twire[31:0] level23_SUM_SS;\\\\n\\\\tDFlipFlop32 level23_SUMSS_FF(level22_SUM_SS,clk,level23_SUM_SS);\\\\n\\\\n\\\\t//24 clock cycle\\\\n\\\\twire[31:0] level24_SUM_SS;\\\\n\\\\tDFlipFlop32 level24_SUMSS_FF(level23_SUM_SS,clk,level24_SUM_SS);\\\\n\\\\n\\\\t//25 clock cycle\\\\n\\\\twire[31:0] level25_SUM_SS;\\\\n\\\\tDFlipFlop32 level25_SUMSS_FF(level24_SUM_SS,clk,level25_SUM_SS);\\\\n\\\\n\\\\t//26 clock cycle\\\\n\\\\twire[31:0] level26_SUM_SS;\\\\n\\\\tDFlipFlop32 level26_SUMSS_FF(level25_SUM_SS,clk,level26_SUM_SS);\\\\n\\\\n\\\\t//27 clock cycle\\\\n\\\\twire[31:0] level27_SUM_SS;\\\\n\\\\tDFlipFlop32 level27_SUMSS_FF(level26_SUM_SS,clk,level27_SUM_SS);\\\\n\\\\n\\\\t//28 clock cycle\\\\n\\\\twire[31:0] level28_SUM_SS;\\\\n\\\\tDFlipFlop32 level28_SUMSS_FF(level27_SUM_SS,clk,level28_SUM_SS);\\\\n\\\\n\\\\t//29 clock cycle\\\\n\\\\twire[31:0] level29_SUM_SS;\\\\n\\\\tDFlipFlop32 level29_SUMSS_FF(level28_SUM_SS,clk,level29_SUM_SS);\\\\n\\\\n\\\\t//30 clock cycle\\\\n\\\\twire[31:0] level30_SUM_SS;\\\\n\\\\tDFlipFlop32 level30_SUMSS_FF(level29_SUM_SS,clk,level30_SUM_SS);\\\\n\\\\n\\\\t//31 clock cycle\\\\n\\\\twire[31:0] level31_SUM_SS;\\\\n\\\\tDFlipFlop32 level31_SUMSS_FF(level30_SUM_SS,clk,level31_SUM_SS);\\\\n\\\\n\\\\t//32 clock cycle\\\\n\\\\twire[31:0] level32_SUM_SS;\\\\n\\\\tDFlipFlop32 level32_SUMSS_FF(level31_SUM_SS,clk,level32_SUM_SS);\\\\n\\\\n\\\\t//33 clock cycle\\\\n\\\\twire[31:0] level33_SUM_SS;\\\\n\\\\tDFlipFlop32 level33_SUMSS_FF(level32_SUM_SS,clk,level33_SUM_SS);\\\\n\\\\n\\\\t//34 clock cycle\\\\n\\\\twire[31:0] level34_SUM_SS;\\\\n\\\\tDFlipFlop32 level34_SUMSS_FF(level33_SUM_SS,clk,level34_SUM_SS);\\\\n\\\\n\\\\t//35 clock cycle\\\\n\\\\twire[31:0] level35_SUM_SS;\\\\n\\\\tDFlipFlop32 level35_SUMSS_FF(level34_SUM_SS,clk,level35_SUM_SS);\\\\n\\\\n\\\\t/*Propogate SUM_SS_FFOUT '22nd to 35th' clock cycle -- end */\\\\n\\\\n\\\\t//generating output\\\\n\\\\tMUX32bit_2x1 MUX_SUM(level35_SUM_SS,SUM_DS_FFOUT,level35_signXOR,SUM);\\\\n\\\\t\\\\nendmodule"]
["module branchCtrl (IR_Stage3,nEQ,LT,shouldBranch,newPC,branchIsn,Stage3PC,signExtended);\\\\n\\\\ninput [31:0] IR_Stage3,Stage3PC,signExtended;\\\\ninput nEQ, LT;\\\\noutput shouldBranch,branchIsn;\\\\noutput [31:0] newPC;\\\\nwire junk,realLT;\\\\nwire [31:0] PCGens, PCProps;\\\\nassign branchIsn = (!IR_Stage3[31] && !IR_Stage3[30] && !IR_Stage3[29] && IR_Stage3[28] && !IR_Stage3[27]) || (!IR_Stage3[31] && !IR_Stage3[30] && IR_Stage3[29] && IR_Stage3[28] && !IR_Stage3[27]);\\\\nassign shouldBranch = (nEQ && !IR_Stage3[31] && !IR_Stage3[30] && !IR_Stage3[29] && IR_Stage3[28] && !IR_Stage3[27]) || (realLT && !IR_Stage3[31] && !IR_Stage3[30] && IR_Stage3[29] && IR_Stage3[28] && !IR_Stage3[27]);\\\\nassign realLT = !LT && nEQ;\\\\n bitwise_And PCgen(.in1(Stage3PC),.in2(signExtended),.out(PCGens));\\\\n bitwise_Or PCProp(.in1(Stage3PC),.in2(signExtended),.out(PCProps));\\\\n fullAdder PCCounter(.dataA(Stage3PC),.dataB(signExtended),.props(PCProps),.gens(PCGens),.carryIn(1'b0),.sum(newPC),.carryOut(junk));\\\\n \\\\nendmodule"]
["module layer_mid_1(/*autoport*/\\\\n//output\\\\n\\\\t\\\\t\\\\tRqFlag1,\\\\n\\\\t\\\\t\\\\tRed1,\\\\n\\\\t\\\\t\\\\tBlue1,\\\\n\\\\t\\\\t\\\\tGreen1,\\\\n//input\\\\n\\\\t\\\\t\\\\tclk,\\\\n\\\\t\\\\t\\\\tman,\\\\n\\\\t\\\\t\\\\tbox,\\\\n\\\\t\\\\t\\\\tway,\\\\n\\\\t\\\\t\\\\twall,\\\\n\\\\t\\\\t\\\\tdestination,\\\\n\\\\t\\\\t\\\\tx_pos,\\\\n\\\\t\\\\t\\\\ty_pos);\\\\n\\\\tinput clk;\\\\n\\\\tinput[5:0] man;\\\\n\\\\tinput[63:0] box,way,wall,destination; \\\\n\\\\tinput[9:0] x_pos,y_pos;\\\\n\\\\toutput RqFlag1;\\\\n\\\\toutput[7:0] Red1,Blue1,Green1;\\\\n\\\\treg[7:0] Red1,Blue1,Green1;\\\\n\\\\treg flag=0,mask=0;\\\\n\\\\twire[11:0] addr;\\\\n\\\\twire[9:0] x_offset,y_offset;\\\\n\\\\twire[5:0] cursor;\\\\n\\\\tparameter TOP=10'd100,LEFT=10'd200,WIDTH=10'd64*8,HEIGHT=10'd64*8;\\\\n\\\\tassign x_offset=x_pos-LEFT;\\\\n\\\\tassign y_offset=y_pos-TOP;\\\\n\\\\t// assume 64*64 block\\\\n\\\\tassign addr={y_offset[5:0],x_offset[5:0]};\\\\n\\\\tassign cursor={y_offset[8:6],x_offset[8:6]};\\\\n\\\\tassign RqFlag1=mask&flag;\\\\n\\\\twire rom_en;\\\\n\\\\tassign rom_en=(x_pos>=LEFT)&&(x_pos<LEFT+WIDTH)&&(y_pos>=TOP)&&(y_pos<TOP+HEIGHT);\\\\n\\\\twire[7:0] box_dst_red,box_dst_blue,box_dst_green;\\\\n\\\\twire[7:0] box_red,box_blue,box_green;\\\\n\\\\twire[7:0] dst_red,dst_blue,dst_green;\\\\n\\\\twire[7:0] way_red,way_blue,way_green;\\\\n\\\\twire[7:0] wall_red,wall_blue,wall_green;\\\\n\\\\talways @(*) begin\\\\n\\\\t\\\\tif(x_pos<LEFT||y_pos<TOP||x_pos>=LEFT+WIDTH||y_pos>=TOP+HEIGHT) begin\\\\n\\\\t\\\\t\\\\tmask<=0;\\\\n\\\\t\\\\tend\\\\n\\\\t\\\\telse begin\\\\n\\\\t\\\\t\\\\tmask<=1;\\\\n\\\\t\\\\tend\\\\n\\\\t\\\\tif(box[cursor]==1&&destination[cursor]==1) begin\\\\n\\\\t\\\\t\\\\tRed1<=box_dst_red;\\\\n\\\\t\\\\t\\\\tBlue1<=box_dst_blue;\\\\n\\\\t\\\\t\\\\tGreen1<=box_dst_green;\\\\n\\\\t\\\\t\\\\tflag<=1;\\\\n\\\\t\\\\tend\\\\n\\\\t\\\\telse if(box[cursor]==1) begin\\\\n\\\\t\\\\t\\\\tRed1<=box_red;\\\\n\\\\t\\\\t\\\\tBlue1<=box_blue;\\\\n\\\\t\\\\t\\\\tGreen1<=box_green;\\\\n\\\\t\\\\t\\\\tflag<=1;\\\\n\\\\t\\\\tend\\\\n\\\\t\\\\telse if(destination[cursor]==1) begin\\\\n\\\\t\\\\t\\\\tRed1<=dst_red;\\\\n\\\\t\\\\t\\\\tBlue1<=dst_blue;\\\\n\\\\t\\\\t\\\\tGreen1<=dst_green;\\\\n\\\\t\\\\t\\\\tflag<=1;\\\\n\\\\t\\\\tend\\\\n\\\\t\\\\telse if(way[cursor]==1) begin\\\\n\\\\t\\\\t\\\\tRed1<=way_red;\\\\n\\\\t\\\\t\\\\tBlue1<=way_blue;\\\\n\\\\t\\\\t\\\\tGreen1<=way_green;\\\\n\\\\t\\\\t\\\\tflag<=1;\\\\n\\\\t\\\\tend\\\\n\\\\t\\\\telse if(wall[cursor]==1) begin\\\\n\\\\t\\\\t\\\\tRed1<=wall_red;\\\\n\\\\t\\\\t\\\\tBlue1<=wall_blue;\\\\n\\\\t\\\\t\\\\tGreen1<=wall_green;\\\\n\\\\t\\\\t\\\\tflag<=1;\\\\n\\\\t\\\\tend\\\\n\\\\t\\\\telse begin\\\\n\\\\t\\\\t\\\\tRed1<=0;\\\\n\\\\t\\\\t\\\\tBlue1<=0;\\\\n\\\\t\\\\t\\\\tGreen1<=0;\\\\n\\\\t\\\\t\\\\tflag<=0;\\\\n\\\\t\\\\tend\\\\n\\\\tend\\\\n\\\\tboxRom box_inst(\\\\n\\\\t\\\\t.addr(addr),\\\\n\\\\t\\\\t.clk(clk),\\\\n\\\\t\\\\t.dout({box_red,box_blue,box_green}),\\\\n\\\\t\\\\t.en(rom_en));\\\\n\\\\tdstRom dst_inst(\\\\n\\\\t\\\\t.addr(addr),\\\\n\\\\t\\\\t.clk(clk),\\\\n\\\\t\\\\t.dout({dst_red,dst_blue,dst_green}),\\\\n\\\\t\\\\t.en(rom_en));\\\\n\\\\tboxDstRom box_dst_inst(\\\\n\\\\t\\\\t.addr(addr),\\\\n\\\\t\\\\t.clk(clk),\\\\n\\\\t\\\\t.dout({box_dst_red,box_dst_blue,box_dst_green}),\\\\n\\\\t\\\\t.en(rom_en));\\\\n\\\\twayRom way_inst(\\\\n\\\\t\\\\t.addr(addr),\\\\n\\\\t\\\\t.clk(clk),\\\\n\\\\t\\\\t.dout({way_red,way_blue,way_green}),\\\\n\\\\t\\\\t.en(rom_en));\\\\n\\\\twallRom wall_inst(\\\\n\\\\t\\\\t.addr(addr),\\\\n\\\\t\\\\t.clk(clk),\\\\n\\\\t\\\\t.dout({wall_red,wall_blue,wall_green}),\\\\n\\\\t\\\\t.en(rom_en));\\\\nendmodule"]
["module controller_layer4(L,z,k_Reg,y_Reg,BRAM1_addr,BRAM2_addr,weight_addr,load,clk,rst,temp_zero_new,temp_zero);\\\\ninput wire clk,rst;\\\\noutput wire L;\\\\noutput wire [1:0] k_Reg;\\\\noutput wire [4:0] y_Reg;\\\\noutput wire [9:0] BRAM1_addr,BRAM2_addr;\\\\noutput wire [3:0] weight_addr;\\\\noutput wire \\\\t\\\\tload,z,temp_zero_new,temp_zero;\\\\n wire [1:0] k;\\\\nwire [4:0] row,col,x,y,x_Reg;\\\\nwire L_zero,y_zero,x_zero,temp_count,z_zero,K_zero;\\\\n\\\\nL_counter_L4 L_counter_layer_4 \\\\t\\\\t(L,L_zero,clk,rst,temp_zero);\\\\nk_counter_L4 k_counter_layer_4\\\\t\\\\t(k,K_zero,clk,rst,L_zero,temp_zero);\\\\nz_counter_L4 Z_counter_layer_4 \\\\t\\\\t(z,z_zero,clk,rst,K_zero,temp_zero);\\\\ny_counter_L4 y_counter_layer_4 \\\\t\\\\t(y,y_zero,clk,rst,z_zero,temp_count,temp_zero);\\\\nx_counter_L4 x_counter_layer_4 \\\\t\\\\t(x,x_zero,clk,rst,y_zero,temp_count,temp_zero);\\\\n\\\\nReg_y_L4 Reg_y\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t(y_Reg,clk,rst,y);\\\\nReg_k_L4\\\\tReg_k\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t(k_Reg,clk,rst,k);\\\\ntemp_counter_L4 temp_counter_layer_4(temp_count,temp_zero,clk,rst,x_zero,temp_zero_new);\\\\nR_counter_L4 R_counter_layer_4\\\\t\\\\t(R_zero,clk,rst,K_zero,temp_zero);\\\\nBRAM2_out_L4 BRAM2_out\\\\t\\\\t\\\\t\\\\t\\\\t(BRAM2_addr,clk,rst,K_zero,x,y);\\\\nassign load=R_zero;\\\\nassign weight_addr={z,k,L};\\\\nassign row=x;\\\\nassign col=y+k-1'b1;\\\\nassign BRAM1_addr = {row,col};\\\\nendmodule"]
["module CF(gyroData_x,gyroData_y,gyroData_z,\\\\n\\\\t\\\\t\\\\t x_accel_data,y_accel_data,z_accel_data,\\\\n\\\\t\\\\t\\\\t clk,\\\\n\\\\t\\\\t\\\\t RST,\\\\n\\\\t\\\\t\\\\t x_final,y_final,z_final\\\\n );\\\\n\\\\t \\\\ninput signed [19:0] gyroData_x,gyroData_y,gyroData_z;//read from gyro\\\\ninput [9:0] x_accel_data,y_accel_data,z_accel_data;//read from accelerometer\\\\ninput RST;\\\\n\\\\noutput [15:0] x_final,y_final,z_final; //x_final=final degree of x axis\\\\n\\\\nwire signed [19:0] gyroData_x,gyroData_y,gyroData_z;//gyro\\\\nwire [9:0] x_accel_data,y_accel_data,z_accel_data;//acc, 10th bit sign, rest is magnitude\\\\nwire [15:0] x_out,y_out,z_out;//arctan results, internal\\\\nreg rdy_acc;\\\\n\\\\nwire rdy_x,rdy_y,rdy_z;\\\\nreg signed [19:0] x_gyro1;\\\\nreg signed [19:0] x_gyro,y_gyro,z_gyro;//DEGREE from gyro,internal\\\\nreg [23:0] x_acc,y_acc,z_acc;//DEGREE from acc, internal\\\\nreg [15:0] x_final,y_final,z_final;\\\\n\\\\nwire slow_clk;\\\\n\\\\n\\\\nCF_slowclk slowclk (\\\\n\\\\t\\\\t\\\\t.clk(clk),\\\\n\\\\t\\\\t\\\\t.RST(RST),\\\\n\\\\t\\\\t\\\\t.slow_clk(slow_clk)\\\\n);\\\\n\\\\n\\\\n\\\\nalways @ (posedge slow_clk ) begin\\\\n\\\\n\\\\tif (gyroData_x[19]==1'b1) begin\\\\n\\\\t\\\\tif (x_gyro >= (x_gyro - gyroData_x[9:0])) begin\\\\n\\\\t\\\\t\\\\tx_gyro <= x_gyro - gyroData_x[9:0];\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\telse begin\\\\n\\\\t\\\\t\\\\tx_gyro <= 20'd360 - (gyroData_x[9:0] - x_gyro);\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\n\\\\tend else begin\\\\n\\\\tif (x_gyro <= 20'd360) begin\\\\n\\\\tx_gyro <= x_gyro + gyroData_x[9:0];\\\\n\\\\tend else begin\\\\n\\\\tx_gyro <= x_gyro - 20'd360;\\\\n\\\\tend\\\\n\\\\tend\\\\n\\\\nend\\\\n\\\\narctan x_cc (\\\\n\\\\t.x_in(({{y_accel_data[7:2],2'b00}*8'b10100100})>>1),//164 == 10100100\\\\n\\\\t.y_in(({{z_accel_data[7:2],2'b00}*8'b10100100})>>1),//x and y format 1QN =>XX.XXXXXXXXXXXXXX\\\\n\\\\t.phase_out(x_out),//out format 2QN =>XXX.XXXXXXXXXXXXX\\\\n\\\\t.rdy(rdy_x),\\\\n\\\\t.clk(slow_clk)\\\\n);\\\\n\\\\narctan y_cc (\\\\n\\\\t.x_in(({{z_accel_data[7:2],2'b00}*8'b10100100})>>1),//x and y format 1QN =>XX.XXXXXXXXXXXXXX\\\\n\\\\t.y_in(({{x_accel_data[7:2],2'b00}*8'b10100100})>>1),//\\\\n\\\\t.phase_out(y_out),//out format 2QN =>XXX.XXXXXXXXXXXXX\\\\n\\\\t.rdy(rdy_y),\\\\n\\\\t.clk(slow_clk)\\\\n);\\\\n\\\\narctan z_cc (\\\\n\\\\t.x_in(({{x_accel_data[7:2],2'b00}*8'b10100100})>>1),//x and y format 1QN =>XX.XXXXXXXXXXXXXX\\\\n\\\\t.y_in(({{y_accel_data[7:2],2'b00}*8'b10100100})>>1),//\\\\n\\\\t.phase_out(z_out),//out format 2QN =>XXX.XXXXXXXXXXXXX\\\\n\\\\t.rdy(rdy_z),\\\\n\\\\t.clk(slow_clk)\\\\n);\\\\n\\\\nfunction reg inbetween(input [7:0] low, value, high); \\\\nbegin\\\\n inbetween = value >= low && value <= high;\\\\nend\\\\nendfunction\\\\n\\\\n\\\\nalways @ (posedge slow_clk) begin\\\\n\\\\t//Convert to 360 degree\\\\n//\\\\tif (rdy_x==1'b1 && rdy_y==1'b1 && rdy_z==1'b1) begin\\\\n\\\\tcase (1)\\\\n\\\\t\\\\t\\\\t\\\\tinbetween(0,x_out,11): x_acc<=16'd5;\\\\n\\\\t\\\\t\\\\t\\\\tinbetween(12,x_out,22): x_acc<=16'd10;\\\\n\\\\t\\\\t\\\\t\\\\tinbetween(22,x_out,33): x_acc<=16'd15;\\\\n\\\\t\\\\t\\\\t\\\\tinbetween(33,x_out,44): x_acc<=16'd20;\\\\n\\\\t\\\\t\\\\t\\\\tinbetween(44,x_out,55): x_acc<=16'd25;\\\\n\\\\t\\\\t\\\\t\\\\tinbetween(55,x_out,66): x_acc<=16'd30;\\\\n\\\\t\\\\t\\\\t\\\\tinbetween(66,x_out,44): x_acc<=16'd35;\\\\n\\\\t\\\\t\\\\t\\\\tinbetween(77,x_out,88): x_acc<=16'd40;\\\\n\\\\t\\\\t\\\\t\\\\tinbetween(88,x_out,99): x_acc<=16'd45;\\\\n\\\\t\\\\t\\\\t\\\\tinbetween(99,x_out,111): x_acc<=16'd50;\\\\n\\\\t\\\\t\\\\t\\\\tinbetween(111,x_out,122): x_acc<=16'd55;\\\\n\\\\t\\\\t\\\\t\\\\tinbetween(122,x_out,133): x_acc<=16'd60;\\\\n\\\\t\\\\t\\\\t\\\\tinbetween(133,x_out,144): x_acc<=16'd65;\\\\n\\\\t\\\\t\\\\t\\\\tinbetween(144,x_out,155): x_acc<=16'd70;\\\\n\\\\t\\\\t\\\\t\\\\tinbetween(155,x_out,166): x_acc<=16'd75;\\\\n\\\\t\\\\t\\\\t\\\\tinbetween(166,x_out,177): x_acc<=16'd80;\\\\n\\\\t\\\\t\\\\t\\\\tinbetween(177,x_out,188): x_acc<=16'd85;\\\\n\\\\t\\\\t\\\\t\\\\tinbetween(188,x_out,201): x_acc<=16'd90;\\\\n\\\\t\\\\t\\\\t\\\\tdefault:x_acc<=16'd0;\\\\nendcase\\\\nend\\\\n\\\\t\\\\n\\\\talways @ (posedge slow_clk) begin\\\\n\\\\t//Convert to 360 degree\\\\n//\\\\tif (rdy_x==1'b1 && rdy_y==1'b1 && rdy_z==1'b1) begin\\\\n\\\\tcase (1)\\\\n\\\\t\\\\t\\\\t\\\\tinbetween(0,y_out,11): y_acc<=16'd5;\\\\n\\\\t\\\\t\\\\t\\\\tinbetween(12,y_out,22): y_acc<=16'd10;\\\\n\\\\t\\\\t\\\\t\\\\tinbetween(22,y_out,33): y_acc<=16'd15;\\\\n\\\\t\\\\t\\\\t\\\\tinbetween(33,y_out,44): y_acc<=16'd20;\\\\n\\\\t\\\\t\\\\t\\\\tinbetween(44,y_out,55): y_acc<=16'd25;\\\\n\\\\t\\\\t\\\\t\\\\tinbetween(55,y_out,66): y_acc<=16'd30;\\\\n\\\\t\\\\t\\\\t\\\\tinbetween(66,y_out,44): y_acc<=16'd35;\\\\n\\\\t\\\\t\\\\t\\\\tinbetween(77,y_out,88): y_acc<=16'd40;\\\\n\\\\t\\\\t\\\\t\\\\tinbetween(88,y_out,99): y_acc<=16'd45;\\\\n\\\\t\\\\t\\\\t\\\\tinbetween(99,y_out,111): y_acc<=16'd50;\\\\n\\\\t\\\\t\\\\t\\\\tinbetween(111,y_out,122): y_acc<=16'd55;\\\\n\\\\t\\\\t\\\\t\\\\tinbetween(122,y_out,133): y_acc<=16'd60;\\\\n\\\\t\\\\t\\\\t\\\\tinbetween(133,y_out,144): y_acc<=16'd65;\\\\n\\\\t\\\\t\\\\t\\\\tinbetween(144,y_out,155): y_acc<=16'd70;\\\\n\\\\t\\\\t\\\\t\\\\tinbetween(155,y_out,166): y_acc<=16'd75;\\\\n\\\\t\\\\t\\\\t\\\\tinbetween(166,y_out,177): y_acc<=16'd80;\\\\n\\\\t\\\\t\\\\t\\\\tinbetween(177,y_out,188): y_acc<=16'd85;\\\\n\\\\t\\\\t\\\\t\\\\tinbetween(188,y_out,201): y_acc<=16'd90;\\\\n\\\\t\\\\t\\\\t\\\\tdefault:y_acc<=16'd0;\\\\nendcase\\\\nend\\\\n\\\\nalways @ (posedge slow_clk) begin\\\\n\\\\t//Convert to 360 degree\\\\n//\\\\tif (rdy_x==1'b1 && rdy_y==1'b1 && rdy_z==1'b1) begin\\\\n\\\\tcase (1)\\\\n\\\\t\\\\t\\\\t\\\\tinbetween(0,z_out,11): z_acc<=16'd5;\\\\n\\\\t\\\\t\\\\t\\\\tinbetween(12,z_out,22): z_acc<=16'd10;\\\\n\\\\t\\\\t\\\\t\\\\tinbetween(22,z_out,33): z_acc<=16'd15;\\\\n\\\\t\\\\t\\\\t\\\\tinbetween(33,z_out,44): z_acc<=16'd20;\\\\n\\\\t\\\\t\\\\t\\\\tinbetween(44,z_out,55): z_acc<=16'd25;\\\\n\\\\t\\\\t\\\\t\\\\tinbetween(55,z_out,66): z_acc<=16'd30;\\\\n\\\\t\\\\t\\\\t\\\\tinbetween(66,z_out,44): z_acc<=16'd35;\\\\n\\\\t\\\\t\\\\t\\\\tinbetween(77,z_out,88): z_acc<=16'd40;\\\\n\\\\t\\\\t\\\\t\\\\tinbetween(88,z_out,99): z_acc<=16'd45;\\\\n\\\\t\\\\t\\\\t\\\\tinbetween(99,z_out,111): z_acc<=16'd50;\\\\n\\\\t\\\\t\\\\t\\\\tinbetween(111,z_out,122): z_acc<=16'd55;\\\\n\\\\t\\\\t\\\\t\\\\tinbetween(122,z_out,133): z_acc<=16'd60;\\\\n\\\\t\\\\t\\\\t\\\\tinbetween(133,z_out,144): z_acc<=16'd65;\\\\n\\\\t\\\\t\\\\t\\\\tinbetween(144,z_out,155): z_acc<=16'd70;\\\\n\\\\t\\\\t\\\\t\\\\tinbetween(155,z_out,166): z_acc<=16'd75;\\\\n\\\\t\\\\t\\\\t\\\\tinbetween(166,z_out,177): z_acc<=16'd80;\\\\n\\\\t\\\\t\\\\t\\\\tinbetween(177,z_out,188): z_acc<=16'd85;\\\\n\\\\t\\\\t\\\\t\\\\tinbetween(188,z_out,201): z_acc<=16'd90;\\\\n\\\\t\\\\t\\\\t\\\\tdefault:z_acc<=16'd0;\\\\nendcase\\\\nend\\\\n\\\\t\\\\n\\\\talways @ (posedge clk) begin\\\\n\\\\n\\\\tx_final <= x_accel_data[8:0];//\\\\n\\\\ty_final <= y_accel_data[8:0];// x/y/z_final=0.96875*gyro+0.03125*acc\\\\n\\\\tz_final <= z_accel_data[8:0];//\\\\n\\\\n\\\\nend\\\\n\\\\n\\\\nendmodule"]
['module r_type(input clk , input reset, input [32:0]instruction, input [4:0]write_reg, input [63:0]write_data, input reg_write, output [63:0] result);\\\\n\\\\n\\\\twire [63:0] result;\\\\n\\\\treg [4:0] read_reg1, read_reg2;\\\\n\\\\twire [4:0] write_reg;\\\\n\\\\treg [63:0] write_data;\\\\n\\\\twire reg_write;\\\\n\\\\twire [63:0] read_data1, read_data2;\\\\n\\\\treg less;\\\\n\\\\treg [5:0] in;\\\\n\\\\twire G, P, set, overflow, zero;\\\\n\\\\tinteger i;\\\\t\\\\n\\\\t\\\\n\\\\treg_file r(read_reg1, read_reg2, write_reg, write_data, reg_write, clk, reset, read_data1, read_data2);\\\\n\\\\t\\\\n\\\\talu64_withcu alu(read_data1, read_data1, less, in[5:0], result[63:0], G, P, set, overflow, zero);\\\\n\\\\t\\\\n\\\\talways @(posedge clk) begin\\\\n\\\\t\\\\tread_reg1[4:0] = instruction[19:15];\\\\n\\\\t\\\\tread_reg2[4:0] = instruction[24:20];\\\\n \\\\n\\\\t\\\\tless = 0;\\\\n\\\\t\\\\tin[2:0] = instruction[14:12];\\\\n\\\\t\\\\tin[3] = instruction[30];\\\\n\\\\t\\\\tin[4] = instruction[6] & instruction[4] & (~instruction[4]);\\\\n\\\\t\\\\tin[5] = (~instruction[6]) & instruction[4] & instruction[4];\\\\t\\\\t\\\\n\\\\t\\\\n\\\\t\\\\twrite_data = result;\\\\n\\\\t\\\\n\\\\tend\\\\n\\\\t\\\\nendmodule']
['module muxer_3_5_1(A, B, C, D, E, Selectors, LEDs);\\\\n\\\\n\\\\t// Define inputs and outputs\\\\n\\\\tinput [2:0] A;\\\\n\\\\tinput [2:0] B;\\\\n\\\\tinput [2:0] C;\\\\n\\\\tinput [2:0] D;\\\\n\\\\tinput [2:0] E;\\\\n\\\\tinput [2:0] Selectors;\\\\n\\\\toutput [2:0] LEDs;\\\\n\\\\t\\\\n\\\\t// Create 3 5-1 Muxes\\\\n\\\\tmuxer_5_1 muxA(\\\\n\\\\t\\\\t.lineA(A[0]),\\\\n\\\\t\\\\t.lineB(B[0]),\\\\n\\\\t\\\\t.lineC(C[0]),\\\\n\\\\t\\\\t.lineD(D[0]),\\\\n\\\\t\\\\t.lineE(E[0]),\\\\n\\\\t\\\\t.Selectors(Selectors),\\\\n\\\\t\\\\t.lineout(LEDs[0])\\\\n\\\\t);\\\\n\\\\t\\\\n\\\\tmuxer_5_1 muxB(\\\\n\\\\t\\\\t.lineA(A[1]),\\\\n\\\\t\\\\t.lineB(B[1]),\\\\n\\\\t\\\\t.lineC(C[1]),\\\\n\\\\t\\\\t.lineD(D[1]),\\\\n\\\\t\\\\t.lineE(E[1]),\\\\n\\\\t\\\\t.Selectors(Selectors),\\\\n\\\\t\\\\t.lineout(LEDs[1])\\\\n\\\\t);\\\\n\\\\t\\\\n\\\\tmuxer_5_1 muxC(\\\\n\\\\t\\\\t.lineA(A[2]),\\\\n\\\\t\\\\t.lineB(B[2]),\\\\n\\\\t\\\\t.lineC(C[2]),\\\\n\\\\t\\\\t.lineD(D[2]),\\\\n\\\\t\\\\t.lineE(E[2]),\\\\n\\\\t\\\\t.Selectors(Selectors),\\\\n\\\\t\\\\t.lineout(LEDs[2])\\\\n\\\\t);\\\\n\\\\nendmodule']
['module HA(output C, S, input A, B);\\\\n\\\\tXOR g0(S, A, B);\\\\n\\\\tAND g1(C, A, B);\\\\nendmodule', 'module FA(output C, S, input A, B, CI);\\\\n\\\\twire c0, s0, c1, s1;\\\\n\\\\tHA ha0(c0, s0, A, B);\\\\n\\\\tHA ha1(c1, s1, s0, CI);\\\\n\\\\tassign S = s1;\\\\n\\\\tOR or0(C, c0, c1);\\\\nendmodule', 'module adder_rtl(\\\\n\\\\toutput C3, // carry output\\\\n\\\\toutput[2:0] S, // sum\\\\n\\\\tinput[2:0] A, B, // operands\\\\n\\\\tinput C0 // carry input\\\\n\\\\t);\\\\n\\\\t\\\\n// Implement your code here.\\\\n// Hint: should be done in 1 line.\\\\n// You can use this adder to debug the gate-level implemented adder.\\\\n/*B06902100*/\\\\n\\\\tassign {C3, S} = A+B+C0;\\\\n\\\\t\\\\nendmodule', 'module rca_gl(\\\\n\\\\toutput C3, // carry output\\\\n\\\\toutput[2:0] S, // sum\\\\n\\\\tinput[2:0] A, B, // operands\\\\n\\\\tinput C0 // carry input\\\\n\\\\t);\\\\n\\\\twire[3:0] c;\\\\n\\\\tassign c[0] = C0;\\\\n\\\\tassign C3 = c[3];\\\\n\\\\tFA fa0(c[1], S[0], A[0], B[0], c[0]);\\\\n\\\\tFA fa1(c[2], S[1], A[1], B[1], c[1]);\\\\n\\\\tFA fa2(c[3], S[2], A[2], B[2], c[2]);\\\\nendmodule', 'module cla_gl(\\\\n\\\\toutput C3, // carry output\\\\n\\\\toutput[2:0] S, // sum\\\\n\\\\tinput[2:0] A, B, // operands\\\\n\\\\tinput C0 // carry input\\\\n\\\\t);\\\\n\\\\t\\\\n\\\\t// Implement your code here.\\\\n\\\\t/*B06902100*/\\\\n\\\\twire[2:0] G, P, C; \\\\n\\\\tAND and1(G[0], A[0], B[0]); //generate\\\\n\\\\tAND and2(G[1], A[1], B[1]);\\\\n\\\\tAND and3(G[2], A[2], B[2]);\\\\n\\\\tXOR xor1(P[0], A[0], B[0]); //propagate\\\\n\\\\tXOR xor2(P[1], A[1], B[1]);\\\\n\\\\tXOR xor3(P[2], A[2], B[2]);\\\\n\\\\n\\\\tassign C[0] = C0;\\\\n\\\\twire[6:0] TR; //temp. result\\\\n\\\\tAND and4(TR[0], P[0], C[0]); //TR[0] = P[0] & C[0]\\\\n\\\\tAND and5(TR[1], P[1], G[0]); //TR[1] = P[1] & G[0]\\\\n\\\\tAND and6(TR[2], P[1], TR[0]); //TR[2] = P[1] & P[0] & C[0]\\\\n\\\\tAND and7(TR[3], P[2], G[1]); //TR[3] = P[2] & G[1]\\\\n\\\\tAND and8(TR[4], P[2], TR[1]); //TR[4] = P[2] & P[1] & G[0]\\\\n\\\\tAND and9(TR[5], P[2], TR[2]); //TR[5] = P[2] & P[1] & P[0] & C[0]\\\\n\\\\tOR or1(TR[6], G[1], TR[1]); //TR[6] = G[1] | (P[1] & G[0])\\\\n\\\\tOR or2(C[1], G[0], TR[0]); //C[1] = G[0] | (P[0] & C[0])\\\\n\\\\tOR or3(C[2], TR[6], TR[2]); //C[2] = G[1] | (P[1] & G[0]) | (P[1] & P[0] & C[0])\\\\n\\\\tOR4 or4(C3, G[2], TR[3], TR[4], TR[5]);\\\\n\\\\tXOR xor4(S[0], P[0], C[0]);\\\\n\\\\tXOR xor5(S[1], P[1], C[1]);\\\\n\\\\tXOR xor6(S[2], P[2], C[2]);\\\\nendmodule']
["module fifo_16 (clk, reset_n, rd_en, wr_en, d_in, d_out, full, empty, wr_ack, wr_err, rd_ack, rd_err, data_count);\\\\n\\\\tinput clk, reset_n, rd_en, wr_en;\\\\n\\\\tinput[31:0] d_in;\\\\n\\\\toutput[31:0] d_out;\\\\n\\\\toutput full, empty, wr_ack, wr_err, rd_ack, rd_err;\\\\n\\\\toutput reg[4:0] data_count;\\\\n\\\\t\\\\n\\\\twire we, re;\\\\n\\\\twire[2:0] next_state;\\\\n\\\\twire[3:0] next_head, next_tail;\\\\n\\\\treg[2:0] state;\\\\n\\\\treg[3:0] head, tail;\\\\n\\\\twire[4:0] next_data_count;\\\\n\\\\twire[31:0] rData, next_d_out;\\\\n\\\\n\\\\tfifo_ns_16 fifo_ns_1 (wr_en, rd_en, state, data_count, next_state);\\\\n\\\\tfifo_cal_addr_16 fifo_cal_addr_1(next_state, head, tail, data_count, we, re, next_head, next_tail, next_data_count);\\\\n\\\\t//next state logic is contain 2 logics\\\\n\\\\t\\\\n\\\\tfifo_out_16 fifo_out_1(state, data_count, full, empty, wr_ack, wr_err, rd_ack, rd_err);\\\\n\\\\t//Register_file Register_file_1(clk, reset_n, tail[3:0], d_in, we, head[3:0], rData);\\\\n\\\\tALU_registerfile Register_file_1(clk, reset_n, tail, d_in, we, head, d_out);\\\\n\\\\t//output logic is contain 2 logics\\\\n\\\\t\\\\n\\\\tmx2 mx2_1(32'b0000_0000_0000_0000_0000_0000_0000_0000, d_out, re, next_d_out); //mux for d_out\\\\n\\\\t\\\\n\\\\talways @ (posedge clk, negedge reset_n)\\\\n\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\tif (reset_n == 1'b0) //reset has 1st priority (asynchronous)\\\\n\\\\t\\\\t\\\\t\\\\t{state, data_count, head, tail} = 16'b000_00000_0000_0000;\\\\n\\\\t\\\\t\\\\telse //clock has 2nd priority\\\\n\\\\t\\\\t\\\\t\\\\t{state, data_count, head, tail} = {next_state, next_data_count, next_head, next_tail};\\\\n\\\\t\\\\tend\\\\n\\\\t//register logic\\\\nendmodule"]
["module adaptive_fir \\\\n#(parameter \\\\tW1 = 12,\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tW2 = 32,\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tL=16 )\\\\n(input clk,\\\\ninput reset,\\\\ninput signed [11:0] x_in,\\\\ninput signed [13:0] d_in,\\\\ninput [7:0] mu_in,\\\\noutput reg signed [42:0] y_out,\\\\noutput reg signed [32:0] e_out,\\\\noutput reg signed [15:0] f_0,\\\\noutput reg signed [15:0] f_1,\\\\noutput reg signed [15:0] f_2,\\\\noutput reg signed [15:0] f_3,\\\\noutput reg signed [15:0] f_4,\\\\noutput reg signed [15:0] f_5,\\\\noutput reg signed [15:0] f_6,\\\\noutput reg signed [15:0] f_7,\\\\noutput reg signed [15:0] f_8,\\\\noutput reg signed [15:0] f_9,\\\\noutput reg signed [15:0] f_10,\\\\noutput reg signed [15:0] f_11,\\\\noutput reg signed [15:0] f_12,\\\\noutput reg signed [15:0] f_13,\\\\noutput reg signed [15:0] f_14,\\\\noutput reg signed [15:0] f_15\\\\n);\\\\n\\\\n//regs and wire declarations:\\\\nreg signed [11:0] x [0:L-1];\\\\nreg signed [15:0] f [0:L-1];\\\\nreg signed [13:0] d ;\\\\nreg signed [27:0] p [0:L-1];\\\\nwire signed [32:0] emu;\\\\nreg signed [44:0] xemu [0:L-1];\\\\nwire signed [42:0] y;\\\\nwire signed [32:0] e;\\\\n\\\\ninitial begin\\\\n\\\\td <= 14'd0;\\\\n\\\\tx[0] <= 12'd0;\\\\n\\\\tx[1] <= 12'd0;\\\\n\\\\tx[2] <= 12'd0;\\\\n\\\\tx[3] <= 12'd0;\\\\n\\\\tx[4] <= 12'd0;\\\\n\\\\tx[5] <= 12'd0;\\\\n\\\\tx[6] <= 12'd0;\\\\n\\\\tx[7] <= 12'd0;\\\\n\\\\tx[8] <= 12'd0;\\\\n\\\\tx[9] <= 12'd0;\\\\n\\\\tx[10] <= 12'd0;\\\\n\\\\tx[11] <= 12'd0;\\\\n\\\\tx[12] <= 12'd0;\\\\n\\\\tx[13] <= 12'd0;\\\\n\\\\tx[14] <= 12'd0;\\\\n\\\\tx[15] <= 12'd0;\\\\n\\\\n\\\\tf[0] <= 16'd0;\\\\n\\\\tf[1] <= 16'd0;\\\\n\\\\tf[2] <= 16'd0;\\\\n\\\\tf[3] <= 16'd0;\\\\n\\\\tf[4] <= 16'd0;\\\\n\\\\tf[5] <= 16'd0;\\\\n\\\\tf[6] <= 16'd0;\\\\n\\\\tf[7] <= 16'd0;\\\\n\\\\tf[8] <= 16'd0;\\\\n\\\\tf[9] <= 16'd0;\\\\n\\\\tf[10] <= 16'd0;\\\\n\\\\tf[11] <= 16'd0;\\\\n\\\\tf[12] <= 16'd0;\\\\n\\\\tf[13] <= 16'd0;\\\\n\\\\tf[14] <= 16'd0;\\\\n\\\\tf[15] <= 16'd0;\\\\n\\\\t\\\\n\\\\t f_0 <= 16'd0;\\\\n\\\\t f_1 <= 16'd0;\\\\n\\\\t f_2 <= 16'd0;\\\\n\\\\t f_3 <= 16'd0;\\\\n\\\\t f_4 <= 16'd0;\\\\n\\\\t f_5 <= 16'd0;\\\\n\\\\t f_6 <= 16'd0;\\\\n\\\\t f_7 <= 16'd0;\\\\n\\\\t f_8 <= 16'd0;\\\\n\\\\t f_9 <= 16'd0;\\\\n\\\\t f_10 <= 16'd0;\\\\n\\\\t f_11 <= 16'd0;\\\\n\\\\t f_12 <= 16'd0;\\\\n\\\\t f_13 <= 16'd0;\\\\n\\\\t f_14 <= 16'd0;\\\\n\\\\t f_15 <= 16'd0;\\\\n\\\\t\\\\nend\\\\n\\\\nalways @(posedge clk or negedge reset)\\\\nif (!reset)\\\\nbegin\\\\n\\\\td <= 14'd0;\\\\n\\\\tx[0] <= 12'd0;\\\\n\\\\tx[1] <= 12'd0;\\\\n\\\\tx[2] <= 12'd0;\\\\n\\\\tx[3] <= 12'd0;\\\\n\\\\tx[4] <= 12'd0;\\\\n\\\\tx[5] <= 12'd0;\\\\n\\\\tx[6] <= 12'd0;\\\\n\\\\tx[7] <= 12'd0;\\\\n\\\\tx[8] <= 12'd0;\\\\n\\\\tx[9] <= 12'd0;\\\\n\\\\tx[10] <= 12'd0;\\\\n\\\\tx[11] <= 12'd0;\\\\n\\\\tx[12] <= 12'd0;\\\\n\\\\tx[13] <= 12'd0;\\\\n\\\\tx[14] <= 12'd0;\\\\n\\\\tx[15] <= 12'd0;\\\\n\\\\n\\\\tf[0] <= 16'd0;\\\\n\\\\tf[1] <= 16'd0;\\\\n\\\\tf[2] <= 16'd0;\\\\n\\\\tf[3] <= 16'd0;\\\\n\\\\tf[4] <= 16'd0;\\\\n\\\\tf[5] <= 16'd0;\\\\n\\\\tf[6] <= 16'd0;\\\\n\\\\tf[7] <= 16'd0;\\\\n\\\\tf[8] <= 16'd0;\\\\n\\\\tf[9] <= 16'd0;\\\\n\\\\tf[10] <= 16'd0;\\\\n\\\\tf[11] <= 16'd0;\\\\n\\\\tf[12] <= 16'd0;\\\\n\\\\tf[13] <= 16'd0;\\\\n\\\\tf[14] <= 16'd0;\\\\n\\\\tf[15] <= 16'd0;\\\\n\\\\t\\\\n\\\\t f_0 <= 16'd0;\\\\n\\\\t f_1 <= 16'd0;\\\\n\\\\t f_2 <= 16'd0;\\\\n\\\\t f_3 <= 16'd0;\\\\n\\\\t f_4 <= 16'd0;\\\\n\\\\t f_5 <= 16'd0;\\\\n\\\\t f_6 <= 16'd0;\\\\n\\\\t f_7 <= 16'd0;\\\\n\\\\t f_8 <= 16'd0;\\\\n\\\\t f_9 <= 16'd0;\\\\n\\\\t f_10 <= 16'd0;\\\\n\\\\t f_11 <= 16'd0;\\\\n\\\\t f_12 <= 16'd0;\\\\n\\\\t f_13 <= 16'd0;\\\\n\\\\t f_14 <= 16'd0;\\\\n\\\\t f_15 <= 16'd0;\\\\n\\\\t\\\\nend\\\\nelse\\\\tbegin\\\\n\\\\td <= d_in;\\\\n\\\\t\\\\n\\\\tx[0] <= x_in;\\\\n\\\\tx[1] <= x[0];\\\\n\\\\tx[2] <= x[1];\\\\n\\\\tx[3] <= x[2];\\\\n\\\\tx[4] <= x[3];\\\\n\\\\tx[5] <= x[4];\\\\n\\\\tx[6] <= x[5];\\\\n\\\\tx[7] <= x[6];\\\\n\\\\tx[8] <= x[7];\\\\n\\\\tx[9] <= x[8];\\\\n\\\\tx[10] <= x[9];\\\\n\\\\tx[11] <= x[10];\\\\n\\\\tx[12] <= x[11];\\\\n\\\\tx[13] <= x[12];\\\\n\\\\tx[14] <= x[13];\\\\n\\\\tx[15] <= x[14];\\\\n\\\\nf[0] <= f[0] + {xemu [0][42],xemu [0][26:12]};\\\\nf[1] <= f[1] + {xemu [1][42],xemu [1][26:12]};\\\\nf[2] <= f[2] + {xemu [2][42],xemu [2][26:12]};\\\\nf[3] <= f[3] + {xemu [3][42],xemu [3][26:12]};\\\\nf[4] <= f[4] + {xemu [4][42],xemu [4][26:12]};\\\\nf[5] <= f[5] + {xemu [5][42],xemu [5][26:12]};\\\\nf[6] <= f[6] + {xemu [6][42],xemu [6][26:12]};\\\\nf[7] <= f[7] + {xemu [7][42],xemu [7][26:12]};\\\\nf[8] <= f[8] + {xemu [8][42],xemu [8][26:12]};\\\\nf[9] <= f[9] + {xemu [9][42],xemu [9][26:12]};\\\\nf[10] <= f[10] + {xemu [10][42],xemu [10][26:12]};\\\\nf[11] <= f[11] + {xemu [11][42],xemu [11][26:12]};\\\\nf[12] <= f[12] + {xemu [12][42],xemu [12][26:12]};\\\\nf[13] <= f[13] + {xemu [13][42],xemu [13][26:12]};\\\\nf[14] <= f[14] + {xemu [14][42],xemu [14][26:12]};\\\\nf[15] <= f[15] + {xemu [15][42],xemu [15][26:12]};\\\\n\\\\n f_0 <= f[0];\\\\n f_1 <= f[1];\\\\n f_2 <= f[2];\\\\n f_3 <= f[3];\\\\n f_4 <= f[4];\\\\n f_5 <= f[5];\\\\n f_6 <= f[6];\\\\n f_7 <= f[7];\\\\n f_8 <= f[8];\\\\n f_9 <= f[9];\\\\n f_10 <= f[10];\\\\n f_11 <= f[11];\\\\n f_12 <= f[12];\\\\n f_13 <= f[13];\\\\n f_14 <= f[14];\\\\n f_15 <= f[15];\\\\n\\\\ny_out <= y;\\\\ne_out <= e;\\\\n\\\\nend\\\\n\\\\nalways @(*) begin\\\\ninteger i;\\\\nfor (i=0; i<L; i=i+1) p[i] <= x[i] * f[i];\\\\nend\\\\n\\\\nassign y = p[0] + p[1]+ p[2] + p[3] +p[4]+ p[5] + p[6] + p[7] + p[8] + p[9] + p[10] + p[11] + p[12] + p[13] + p[14] + p[15] ;\\\\n\\\\nassign e = (d-(y>>>10));\\\\n\\\\nassign emu = (e>>>mu_in); //Delta control\\\\n\\\\nalways @(*) begin\\\\ninteger i;\\\\nfor (i=0; i<L ; i = i+1) xemu[i] <= emu * x[i];\\\\nend\\\\n\\\\nendmodule"]
["module ex8_top (\\\\nCLOCK_50,\\\\nKEY,\\\\nHEX0,\\\\nHEX1,\\\\nHEX2,\\\\nHEX3,\\\\nHEX4,\\\\nLEDR\\\\n);\\\\n\\\\n\\\\n\\\\ninput CLOCK_50;\\\\ninput [3:0] KEY;\\\\noutput [6:0] HEX0, HEX1, HEX2, HEX3, HEX4;\\\\noutput [9:0] LEDR;\\\\n\\\\nreg [15:0] k1 = 16'd49999;\\\\nreg [15:0] k2 = 16'd2499;\\\\n\\\\nwire tick_ms,tick_hs,time_out,en_fsr,start_delay;\\\\nwire [15:0] prbs;\\\\nwire [3:0]\\\\tBCD_0, BCD_1, BCD_2, BCD_3, BCD_4;\\\\n\\\\nclktick a1 (CLOCK_50,k1,tick_ms,1'b1);\\\\nclktick a2 (CLOCK_50,k2,tick_hs,tick_ms);\\\\n\\\\nfsm F1 (tick_ms,tick_hs,~KEY[3],time_out,en_fsr,start_delay,LEDR);\\\\n\\\\nlfsr16 LFSR (en_fsr,prbs, tick_ms);\\\\n\\\\ndelay D1 ({3'b0, prbs[12:0]},tick_ms,start_delay,time_out);\\\\n\\\\nbin2bcd_16 BCDC ({3'b0, prbs[12:0]}, BCD_0, BCD_1, BCD_2, BCD_3, BCD_4);\\\\n\\\\nhex_to_7seg H0 (HEX0, BCD_0);\\\\nhex_to_7seg H1 (HEX1, BCD_1);\\\\nhex_to_7seg H2 (HEX2, BCD_2);\\\\nhex_to_7seg H3 (HEX3, BCD_3);\\\\nhex_to_7seg H4 (HEX4, BCD_4);\\\\n\\\\nendmodule"]
["module gpu_testbench(iGPU_DATA, oGPU_DATA, oMEM_ADDR, oMEM_READ, oMEM_WRITE, \\\\n\\\\tiVIDEO_ON, iCLK, iRST_N, iVGA_BLANK, oFPS);\\\\n\\\\n// GPU SRAM interface\\\\ninput \\\\t\\\\t [15:0]\\\\tiGPU_DATA;\\\\noutput\\\\treg [15:0]\\\\toGPU_DATA;\\\\noutput\\\\treg [17:0]\\\\toMEM_ADDR;\\\\noutput reg [15:0] oFPS;\\\\noutput\\\\treg \\\\t\\\\t\\\\toMEM_WRITE;\\\\noutput\\\\treg\\\\t\\\\t\\\\toMEM_READ;\\\\n\\\\ninput\\\\tiVIDEO_ON;\\\\ninput\\\\tiCLK;\\\\ninput iRST_N;\\\\ninput iVGA_BLANK;\\\\n//assign reset = iRST_N;\\\\n\\\\n\\\\twire reset, draw, StartPrim, EndPrim, loop, stall;\\\\n\\\\treg NewVertex_delayed;//, NewVertex;\\\\n\\\\treg [9:0] rowInd, colInd;\\\\n\\\\twire [31:0]instruction, vertex;\\\\n\\\\twire [3:0]PrimType;\\\\n\\\\twire NewVertex;\\\\n\\\\twire [15:0] v0x,v0y,v0z,v0w;\\\\n\\\\twire [15:0] v1x,v1y,v1z,v1w;\\\\n\\\\twire [15:0] v2x,v2y,v2z,v2w;\\\\n\\\\t//reg [63:0] vert0Vector;\\\\n\\\\twire [63:0] vert0Vector;\\\\n\\\\t\\\\n\\\\treg rastCycle1;\\\\n\\\\treg rastCycle2, rastCycle3, rastCycle4, rastContinue;\\\\n\\\\twire [1:0] v0depth, v1depth, v2depth, pixelDepth;\\\\n\\\\twire [15:0] triangleColor, loop_PC, PC;\\\\n\\\\twire writePixel, rastDone;\\\\n\\\\twire [15:0] pixelXout, pixelYout, pixelColor;\\\\n\\\\treg rast_v1_select;\\\\n\\\\treg rast_v2_select;\\\\n\\\\t\\\\n\\\\treg [31:0] v_bufferStage1;\\\\n\\\\treg [31:0] v_bufferStage2;\\\\n\\\\treg [31:0] primitive1_v0_buffer;\\\\n\\\\treg [31:0] primitive1_v1_buffer;\\\\n\\\\treg [31:0] primitive1_v2_buffer;\\\\n reg [31:0] primitive1_v3_buffer;\\\\n \\\\treg [31:0] primitive1_min;\\\\n reg [31:0] primitive1_max;\\\\n reg [3:0] primitive1_type;\\\\n reg primitive1_valid;\\\\n \\\\treg primitive1_drawn;\\\\n\\\\treg resetBlank;\\\\n\\\\treg blanked1;\\\\n \\\\n \\\\treg [31:0] primitive2_v0_buffer;\\\\n\\\\treg [31:0] primitive2_v1_buffer;\\\\n\\\\treg [31:0] primitive2_v2_buffer;\\\\n reg [31:0] primitive2_v3_buffer;\\\\n \\\\treg [31:0] primitive2_min;\\\\n reg [31:0] primitive2_max;\\\\n reg [3:0] primitive2_type;\\\\n reg primitive2_valid;\\\\n \\\\treg primitive2_drawn;\\\\n\\\\treg primitive2_drawn_half;\\\\n \\\\t\\\\n \\\\treg draw_reg;\\\\n reg current_prim;\\\\n\\\\twire [31:0] v0_in;\\\\n\\\\twire [31:0] v1_in;\\\\n\\\\twire [31:0] v2_in;\\\\n\\\\treg primType_delayed;\\\\n\\\\t\\\\n\\\\t\\\\n\\\\twire [31:0] v0t_buffer;\\\\n\\\\twire [31:0] v1t_buffer;\\\\n\\\\twire [31:0] v2t_buffer;\\\\n\\\\t\\\\n\\\\twire [3:0] sevenSegOut1;\\\\n\\\\twire [3:0] sevenSegOut2;\\\\n\\\\t\\\\n\\\\treg [31:0] counter;\\\\n\\\\treg [2:0] vertexCount;\\\\n\\\\treg [17:0] i;\\\\n\\\\t\\\\n\\\\treg latch, primRead, blankDone, prim_count;\\\\n\\\\n\\\\n\\\\tassign triangleColor = current_prim ? 16'h00F0 : 16'h0F0F;\\\\n\\\\tassign v0depth = 0;\\\\n\\\\tassign v1depth = 0;\\\\n\\\\tassign v2depth = 0;\\\\n\\\\tassign reset = !iRST_N;\\\\n\\\\t\\\\n\\\\twire rast1, rast2, rast3, rast4, rastCont;\\\\n\\\\twire [63:0] id_to_vops_vector;\\\\n\\\\twire [3:0] vertexOp;\\\\n\\\\t\\\\n\\\\t/*assign rast1 = iVGA_BLANK ? rastCycle1 : 1'b0;\\\\n\\\\tassign rast2 = iVGA_BLANK ? rastCycle2 : 1'b0;\\\\n\\\\tassign rast3 = iVGA_BLANK ? rastCycle3 : 1'b0;\\\\n\\\\tassign rast4 = iVGA_BLANK ? rastCycle4 : 1'b0;\\\\n\\\\tassign rastCont = iVGA_BLANK ? rastContinue : 1'b0;*/\\\\n\\\\t\\\\n\\\\tassign rast1 = rastCycle1;\\\\n\\\\tassign rast2 = rastCycle2;\\\\n\\\\tassign rast3 = rastCycle3;\\\\n\\\\tassign rast4 = rastCycle4;\\\\n\\\\tassign rastCont = rastContinue;\\\\n\\\\t\\\\n\\\\t\\\\n\\\\tinitial primitive1_v0_buffer = 32'd0;\\\\n\\\\tinitial primitive1_v1_buffer = 32'd0;\\\\n\\\\tinitial primitive1_v2_buffer = 32'd0;\\\\n initial primitive1_v3_buffer = 32'd0;\\\\n \\\\n \\\\tinitial primitive2_v0_buffer = 32'd0;\\\\n\\\\tinitial primitive2_v1_buffer = 32'd0;\\\\n\\\\tinitial primitive2_v2_buffer = 32'd0;\\\\n initial primitive2_v3_buffer = 32'd0;\\\\n \\\\n initial primitive1_drawn = 0;\\\\n initial primitive2_drawn = 0;\\\\n initial primitive1_valid = 0;\\\\n initial primitive2_valid = 0;\\\\n initial primitive1_type = 4'd0;\\\\n initial primitive2_type = 4'd0;\\\\n initial primitive2_drawn_half = 0;\\\\n initial rast_v1_select = 0;\\\\n initial rast_v2_select = 0;\\\\n initial rowInd = 0;\\\\n initial colInd = 0;\\\\n initial blankDone = 1;\\\\n initial prim_count = 1'b0;\\\\n initial current_prim = 1'b0;\\\\n \\\\n\\\\t\\\\n\\\\tinitial vertexCount = 3'b000;\\\\n\\\\n\\\\t\\\\n\\\\tFE fetch(.reset(reset),.CLOCK_50(iCLK),\\\\n\\\\t\\\\t\\\\t\\\\t.Stall(stall),\\\\n\\\\t\\\\t\\\\t\\\\t.id_instr(instruction),\\\\n\\\\t\\\\t\\\\t\\\\t.Loop(loop),\\\\n\\\\t\\\\t\\\\t\\\\t.PC_in(loop_PC),\\\\n\\\\t\\\\t\\\\t\\\\t.PC_out(PC));\\\\n\\\\t\\\\t\\\\t\\\\t\\\\n\\\\t\\\\t\\\\t\\\\t\\\\n\\\\t/*ID decode(.RESET(reset),.CLK(iCLK),\\\\n\\\\t\\\\t\\\\t\\\\t .Stall(stall),\\\\n\\\\t\\\\t\\\\t\\\\t .Instruction(instruction),\\\\n\\\\t\\\\t\\\\t\\\\t .Vertex(vert0Vector),\\\\n\\\\t\\\\t\\\\t\\\\t .StartPrimitive(StartPrim),\\\\n\\\\t\\\\t\\\\t\\\\t .EndPrimitive(EndPrim),\\\\n\\\\t\\\\t\\\\t\\\\t .PrimitiveType(PrimType),\\\\n\\\\t\\\\t\\\\t\\\\t .Draw(draw),.Loop(loop),\\\\n\\\\t\\\\t\\\\t\\\\t .PC(PC),.PC_Out(loop_PC),\\\\n\\\\t\\\\t\\\\t\\\\t .NewVertex(NewVertex));*/\\\\n\\\\t\\\\t\\\\t\\\\t \\\\n\\\\tID decode(.RESET(reset),.CLK(iCLK),\\\\n\\\\t\\\\t\\\\t\\\\t .Stall(stall),\\\\n\\\\t\\\\t\\\\t\\\\t .Instruction(instruction),\\\\n\\\\t\\\\t\\\\t\\\\t .Vertex(id_to_vops_vector),\\\\n\\\\t\\\\t\\\\t\\\\t .StartPrimitive(StartPrim),\\\\n\\\\t\\\\t\\\\t\\\\t .EndPrimitive(EndPrim),\\\\n\\\\t\\\\t\\\\t\\\\t .PrimitiveType(PrimType),\\\\n\\\\t\\\\t\\\\t\\\\t .Draw(draw),.Loop(loop),\\\\n\\\\t\\\\t\\\\t\\\\t .PC(PC),.PC_Out(loop_PC),\\\\n\\\\t\\\\t\\\\t\\\\t .VertexOp(vertexOp));\\\\n\\\\t\\\\t\\\\t\\\\t \\\\n\\\\tvertexops vertops(.CLK(iCLK), .vectorIn(id_to_vops_vector), .Vertex(vert0Vector), .NewVertex(NewVertex),.op(vertexOp),.stall(stall));\\\\n\\\\t\\\\t\\\\t\\\\t \\\\n\\\\t\\\\t\\\\t\\\\t \\\\t//Single cycle unit\\\\t\\\\t\\\\t\\\\t\\\\t\\\\n\\\\tVectorComponentExtractor vect0Extract(.in_vector_val(vert0Vector), .clock(iCLK),\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t.out_component0(v0w),\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t.out_component1(v0z),\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t.out_component2(v0y),\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t.out_component3(v0x));\\\\n\\\\t\\\\t\\\\t\\\\t \\\\n\\\\tinitial rastCycle1 = 1'b0;\\\\n\\\\tinitial rastCycle2 = 1'b0;\\\\n\\\\tinitial rastCycle3 = 1'b0;\\\\n\\\\tinitial rastCycle4 = 1'b0;\\\\n\\\\tinitial rastContinue = 1'b0;\\\\n\\\\tinitial counter = 32'd0;\\\\n\\\\tinitial NewVertex_delayed = 1'b0;\\\\n\\\\tinitial draw_reg = 1'b0;\\\\n\\\\tinitial blanked1 = 1'b0;\\\\n\\\\tinitial primitive2_max = 32'd0;\\\\n\\\\tinitial primitive2_min = 32'd0;\\\\n\\\\t\\\\n\\\\tassign stall = /*!iVGA_BLANK |*/ !blankDone | rastCycle1 | rastCycle2 | rastCycle3 | rastCycle4 | rastContinue;\\\\n /*assign current_prim = ((rastDone & primitive1_drawn & !primitive2_drawn) & \\\\n !(rastDone & primitive2_drawn & primitive1_drawn)) ? 1'b1 : 1'b0;*/\\\\n \\\\n\\\\t\\\\t\\\\t\\\\t \\\\n\\\\talways @ (posedge iCLK or posedge reset) begin\\\\n\\\\t\\\\n\\\\t\\\\n\\\\t//resets frame buffer to all 0's when KEY[0] is pressed\\\\n\\\\tif(reset)\\\\n\\\\tbegin\\\\n\\\\t\\\\toMEM_ADDR <= 16'h0000;\\\\n\\\\t\\\\toMEM_WRITE <= 1'b1;\\\\n\\\\t\\\\toMEM_READ <= 1'b0;\\\\n\\\\t\\\\toGPU_DATA <= {4'h0, 4'hF, 4'h0, 4'h0};\\\\t\\\\t\\\\n\\\\tend else begin\\\\n\\\\t\\\\n\\\\t\\\\tif (!iVIDEO_ON /*&& iVGA_BLANK*/) begin \\\\n\\\\t\\\\t \\\\t\\\\t\\\\n\\\\t\\\\tif(StartPrim) begin\\\\n\\\\t\\\\t prim_count <= prim_count + 1'b1;\\\\n\\\\t\\\\t if(prim_count==1'b0) primitive1_type <= PrimType;\\\\n\\\\t\\\\t else primitive2_type <= PrimType;\\\\n\\\\t\\\\tend\\\\n\\\\n\\\\t\\\\tif(blankDone==1'b0) begin\\\\n\\\\t\\\\t\\\\toMEM_ADDR <= rowInd*18'd640 + colInd;\\\\n\\\\t\\\\t\\\\toMEM_WRITE <= 1'b1;\\\\n\\\\t\\\\t\\\\toMEM_READ <= 1'b0;\\\\n\\\\t\\\\t\\\\toGPU_DATA <= {4'h0, 4'h0, 4'h0, 4'h0};\\\\n\\\\t\\\\t\\\\t//if(draw==1'b1) draw_reg <= 1'b1;\\\\n\\\\t\\\\tend else if(blankDone==1'b1) begin\\\\n\\\\t\\\\t\\\\toMEM_ADDR <= pixelYout*18'd640 + pixelXout;\\\\n\\\\t\\\\t\\\\toMEM_WRITE <= writePixel;\\\\n\\\\t\\\\t\\\\toGPU_DATA <= pixelColor;//16'hFFFF;\\\\n\\\\t\\\\t\\\\toMEM_READ <= 1'b0;\\\\n\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\n\\\\t\\\\tif(resetBlank==1'b1) resetBlank <= 1'b0;\\\\n\\\\t\\\\n\\\\t\\\\tif(draw==1'b1) begin \\\\n\\\\t\\\\t\\\\tdraw_reg <=1'b1;\\\\n\\\\t\\\\t\\\\t//blankDone <= 1'b0;\\\\n\\\\t\\\\t\\\\tresetBlank <= 1'b1;\\\\n\\\\t\\\\t\\\\tblanked1 <= 1'b0;\\\\n\\\\t\\\\t\\\\trast_v1_select <= 1'b0;\\\\n\\\\t\\\\t\\\\tcurrent_prim <= 1'b0;\\\\n\\\\t\\\\tend\\\\n\\\\t\\\\telse if (primitive2_drawn & primitive1_drawn) begin\\\\n\\\\t\\\\t\\\\t draw_reg<=1'b0;\\\\n\\\\t\\\\t\\\\t primitive2_drawn <= 1'b0;\\\\n\\\\t\\\\t\\\\t primitive2_drawn_half <= 1'b0;\\\\n\\\\t\\\\t\\\\t primitive2_valid <= 1'b0;\\\\n\\\\t\\\\t\\\\t primitive1_drawn <= 1'b0;\\\\n\\\\t\\\\t\\\\t primitive1_valid <= 1'b0;\\\\n\\\\t\\\\tend\\\\n\\\\t\\\\tcounter <= counter+1;\\\\n\\\\t\\\\t\\\\n\\\\t\\\\t//delay signal for 1 cycle to allow Converter to do its thing\\\\n\\\\t\\\\tNewVertex_delayed <= NewVertex;\\\\n\\\\t\\\\n\\\\t\\\\t\\\\n\\\\t\\\\tif(!blanked1) begin\\\\n\\\\t\\\\t\\\\tif(rowInd==primitive1_max[15:0] && colInd==primitive1_max[31:16]) begin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tblanked1 <=1'b1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t//blankDone <=1'b1;\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\telse blanked1 <= 1'b0;\\\\n\\\\t\\\\tend else\\\\n\\\\t\\\\tif((rowInd==primitive2_max[15:0] && colInd==primitive2_max[31:16]) || primitive2_valid==1'b0) blankDone <=1'b1;\\\\n\\\\t\\\\t//else// blankDone <= 1'b0;\\\\n\\\\t\\\\t\\\\n\\\\t\\\\t//oFPS <= {blanked1, 5'd0, rowInd};\\\\n\\\\t\\\\toFPS <= {primitive1_type, primitive2_type};\\\\n\\\\t\\\\t\\\\t\\\\n\\\\t\\\\t\\\\t\\\\n\\\\t\\\\tif(NewVertex_delayed) begin\\\\n\\\\t\\\\t \\\\n\\\\t\\\\t if(primitive1_valid==0) begin\\\\n\\\\t\\\\t\\\\t\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tif(vertexCount==0) begin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tprimitive1_min <= {v0x, v0y};\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tprimitive1_max <= {v0x, v0y};\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tprimitive1_v1_buffer <= {v0x,v0y};\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tvertexCount <= vertexCount + 1'b1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tend else\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tif(vertexCount==1) begin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tif(v0x<primitive1_min[31:16]) primitive1_min[31:16] <= v0x;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\telse if(v0x>primitive1_max[31:16]) primitive1_max[31:16] <= v0x;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tif(v0y<primitive1_min[15:0]) primitive1_min[15:0] <= v0y;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\telse if(v0y>primitive1_max[15:0]) primitive1_max[15:0] <= v0y;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tprimitive1_v2_buffer[31:16] <= v0x;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tprimitive1_v2_buffer[15:0] <= v0y;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tvertexCount <= vertexCount + 1'b1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tend else\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tif(vertexCount==2) begin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tif(v0x<primitive1_min[31:16]) primitive1_min[31:16] <= v0x;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\telse if(v0x>primitive1_max[31:16]) primitive1_max[31:16] <= v0x;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tif(v0y<primitive1_min[15:0]) primitive1_min[15:0] <= v0y;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\telse if(v0y>primitive1_max[15:0]) primitive1_max[15:0] <= v0y;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tprimitive1_v0_buffer[31:16]<=v0x;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tprimitive1_v0_buffer[15:0]<=v0y;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tif(primitive1_type!=`RECTANGLE) begin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tvertexCount <= 3'd0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tprimitive1_valid <= 1'b1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tend else vertexCount <= vertexCount + 1'b1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tend else if(vertexCount==3)begin\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t if(primitive1_type == `RECTANGLE) begin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t if(v0x<primitive1_min[31:16]) primitive1_min[31:16] <= v0x;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t else if(v0x>primitive1_max[31:16]) primitive1_max[31:16] <= v0x;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t if(v0y<primitive1_min[15:0]) primitive1_min[15:0] <= v0y;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t else if(v0y>primitive1_max[15:0]) primitive1_max[15:0] <= v0y;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t primitive1_v3_buffer[31:16]<=v0x;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t primitive1_v3_buffer[15:0]<=v0y;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t vertexCount <= 3'd0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t primitive1_valid <= 1'b1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t end\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t\\\\t\\\\n\\\\t\\\\t\\\\t\\\\tend else if (primitive2_valid==0) begin\\\\n\\\\n\\\\t\\\\t\\\\t\\\\t \\\\n\\\\t\\\\t\\\\t\\\\t\\\\tif(vertexCount==0) begin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tprimitive2_min <= {v0x, v0y};\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tprimitive2_max <= {v0x, v0y};\\\\t\\\\t\\\\t\\\\t\\\\t\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tprimitive2_v1_buffer[31:16]<=v0x;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tprimitive2_v1_buffer[15:0]<=v0y;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tvertexCount <= vertexCount + 1'b1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tend else\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tif(vertexCount==1) begin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tif(v0x<primitive2_min[31:16]) primitive2_min[31:16] <= v0x;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\telse if(v0x>primitive2_max[31:16]) primitive2_max[31:16] <= v0x;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tif(v0y<primitive2_min[15:0]) primitive2_min[15:0] <= v0y;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\telse if(v0y>primitive2_max[15:0]) primitive2_max[15:0] <= v0y;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tprimitive2_v2_buffer[31:16]<=v0x;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tprimitive2_v2_buffer[15:0]<=v0y;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tvertexCount <= vertexCount + 1'b1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tend else\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tif(vertexCount==2) begin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tif(v0x<primitive2_min[31:16]) primitive2_min[31:16] <= v0x;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\telse if(v0x>primitive2_max[31:16]) primitive2_max[31:16] <= v0x;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tif(v0y<primitive2_min[15:0]) primitive2_min[15:0] <= v0y;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\telse if(v0y>primitive2_max[15:0]) primitive2_max[15:0] <= v0y;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tprimitive2_v0_buffer[31:16]<=v0x;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tprimitive2_v0_buffer[15:0]<=v0y;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tif(primitive2_type!=`RECTANGLE) begin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t vertexCount <= 3'b0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t primitive2_valid <= 1'b1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tend else vertexCount <= vertexCount + 1'b1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tend else\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tif(vertexCount==3)begin \\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t if(primitive2_type == `RECTANGLE) begin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t \\\\t\\\\tif(v0x<primitive2_min[31:16]) primitive2_min[31:16] <= v0x;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\telse if(v0x>primitive2_max[31:16]) primitive2_max[31:16] <= v0x;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tif(v0y<primitive2_min[15:0]) primitive2_min[15:0] <= v0y;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\telse if(v0y>primitive2_max[15:0]) primitive2_max[15:0] <= v0y;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t primitive2_v3_buffer[31:16]<=v0x;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t primitive2_v3_buffer[15:0]<=v0y;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t end\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t vertexCount <= 3'd0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t primitive2_valid <= 1'b1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\n\\\\n\\\\t\\\\t\\\\n\\\\t\\\\t\\\\n\\\\t\\\\t\\\\n\\\\t\\\\t//if(counter==2) vert0Vector[63:32] <= 32'h00800080;\\\\n\\\\t\\\\t//if(counter==1) vert0Vector[63:32] <= 32'h01000080;\\\\n\\\\t\\\\t//if(counter==0) vert0Vector[63:32] <= 32'h00800100;\\\\n\\\\t\\\\t//if(counter>2) NewVertex <= 1'b0;\\\\n\\\\t\\\\t//else NewVertex <=1'b1;\\\\n\\\\t\\\\t//if(counter==1)rastCycle1<=1'b1;\\\\n\\\\t\\\\t//else \\\\n\\\\t //if(counter==16'd6)rastCycle1<=1'b1;\\\\n\\\\t\\\\t//else rastCycle1<=1'b0;\\\\n\\\\t\\\\trastCycle1 <= (~stall) & draw_reg;\\\\n\\\\t\\\\trastCycle2 <= rastCycle1;\\\\n\\\\t\\\\trastCycle3 <= rastCycle2;\\\\n\\\\t\\\\trastCycle4 <= rastCycle3;\\\\n\\\\t\\\\tif(rastCycle4==1'b1) rastContinue <= 1'b1;\\\\n\\\\t\\\\telse if(rastContinue==1'b1 && rastDone==1'b0) rastContinue <= 1'b1;\\\\n\\\\t\\\\telse rastContinue <=1'b0;\\\\n\\\\t\\\\t \\\\n\\\\t\\\\t//control signals for muxes. v0 is hardwired into v0 of the rasterizer\\\\n\\\\t\\\\t//A value of 1 selects the alternate vertex for drawing the other half of\\\\n\\\\t\\\\t// a restangle (v0,v2,v3). 0 selects (v0,v1,v2).\\\\n\\\\t\\\\tif(rastDone==1'b1 && primitive1_drawn==1'b1 && primitive2_drawn==1'b0) begin\\\\n\\\\t\\\\t\\\\tcurrent_prim <= 1'b1;\\\\n\\\\t end else if(rastDone==1'b1 && primitive1_drawn==1'b0) current_prim <= 1'b0;\\\\n \\\\n\\\\t\\\\t//rastDone will be asserted after initial 1/2 of prim1 is drawn.\\\\n\\\\t\\\\tif(rastDone==1'b1 && primitive1_drawn==1'b0 && primitive1_valid==1'b1) begin\\\\n\\\\t\\\\t\\\\t if(primitive1_type==`RECTANGLE) begin\\\\n\\\\t\\\\t\\\\t\\\\t //select alternate set of vertices\\\\n\\\\t\\\\t\\\\t\\\\t rast_v1_select <= 1'b1;\\\\n\\\\t\\\\t\\\\t end else begin\\\\n\\\\t\\\\t\\\\t rast_v1_select <= 1'b0;\\\\n\\\\t\\\\t\\\\t\\\\t primitive1_drawn <= 1'b1;\\\\n\\\\t\\\\t\\\\t\\\\t primitive1_valid <= 1'b0;\\\\n\\\\t\\\\t\\\\t end\\\\t\\\\n\\\\t //This will not automatically draw the 1st half of the triangle, as it happens after primitive 1.\\\\n\\\\t\\\\tend else if(rastDone==1'b1 && primitive2_drawn==1'b0 && primitive2_valid==1'b1)\\\\n\\\\t\\\\t if(primitive2_type==`RECTANGLE && primitive2_drawn_half==1'b0) begin\\\\n\\\\t\\\\t //select alternate set of vertices\\\\n\\\\t\\\\t rast_v1_select <= 1'b1;\\\\n\\\\t\\\\t //rast_v2_select <= 1'b1;\\\\n\\\\t\\\\t\\\\t primitive2_drawn_half <= 1'b1;\\\\n\\\\t\\\\t end else begin\\\\n\\\\t\\\\t\\\\t //If not a rectangle, or 1st half of rectangle is drawn, draw using first 3 vertices.\\\\n\\\\t\\\\t rast_v1_select <= 1'b0;\\\\n\\\\t\\\\t primitive2_drawn <= 1'b1;\\\\n\\\\t\\\\t primitive2_valid <= 1'b0;\\\\n\\\\t\\\\t end\\\\t\\\\n\\\\t\\\\tend\\\\n\\\\t\\\\tend\\\\n\\\\tend\\\\n\\\\t\\\\n\\\\tassign v0_in = (current_prim==1'b0) ? primitive1_v0_buffer\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t: ((rast_v1_select==1'b0) ? primitive2_v0_buffer : primitive2_v1_buffer );\\\\n\\\\t\\\\n\\\\tassign v1_in = (current_prim==1'b0) ? ( (rast_v1_select==1'b0) ? primitive1_v1_buffer : primitive1_v2_buffer )\\\\n\\\\t : ( (rast_v1_select==1'b0) ? primitive2_v1_buffer : primitive2_v0_buffer );\\\\n\\\\t \\\\n\\\\tassign v2_in = (current_prim==1'b0) ? ( (rast_v1_select==1'b0) ? primitive1_v2_buffer : primitive1_v3_buffer )\\\\n\\\\t : ( (rast_v1_select==1'b0) ? primitive2_v2_buffer : primitive2_v3_buffer );\\\\n\\\\t\\\\n\\\\tassign v0t_buffer = 32'h00640019;\\\\n\\\\tassign v1t_buffer = 32'h0067001d;\\\\n\\\\tassign v2t_buffer = 32'h0061001d;\\\\n\\\\t\\\\n\\\\t\\\\t\\\\t\\\\t \\\\n\\\\t\\\\t\\\\t\\\\t\\\\n\\\\t//Multi-cycle unit\\\\t\\\\t\\\\t\\\\t\\\\n\\\\tEdgeRasterizer rasterizer(.clock(iCLK),\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t// clock - logic here takes multiple cycles\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t.in_sig_start_new_triangle(rast1), \\\\t\\\\t\\\\t// control signal to indicate starting new triangle\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t.in_sig_get_boundary_coords(rast2), \\\\t\\\\t\\\\t// control signal to indicate should get bounding box coordinates of triangle\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t.in_sig_form_edges(rast3), \\\\t\\\\t\\\\t\\\\t\\\\t\\\\t// control signal to indicate should form initial edge function values\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t.in_sig_pixel_loop_setup(rast4),\\\\t\\\\t\\\\t\\\\t// control signal to indicate should setup for rasterization loop over pixels\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t.in_sig_rasterize_pixels(rastCont), \\\\t\\\\t\\\\t// control signal to indicate actual rasterization computation should occur\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t.in_v0_screen_x(v0_in[31:16]),\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t.in_v0_screen_y(v0_in[15:0]),\\\\t // x, y coordinates of vertex 0\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t.in_v1_screen_x(v1_in[31:16]), \\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t.in_v1_screen_y(v1_in[15:0]),\\\\t\\\\t// x, y coordinates of vertex 1\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t.in_v2_screen_x(v2_in[31:16]), \\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t.in_v2_screen_y(v2_in[15:0]),\\\\t\\\\t// x, y coordinates of vertex 2\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t.in_v0_depth(v0depth),\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t.in_v1_depth(v1depth),\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t.in_v2_depth(v2depth),\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t// depth (z-value) for 3 vertices\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t.in_color(triangleColor),\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t// color to use for triangle pixels\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t.out_sig_rasterize_write_pixel(writePixel),\\\\t\\\\t// signal to indicate that current output pixel data is a pixel inside triangle that can be written to framebuffer\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t.out_sig_rasterize_done(rastDone), \\\\t\\\\t\\\\t\\\\t\\\\t// signal to indicate rasterization of current triangle is complete\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t.out_pixel_x(pixelXout), .out_pixel_y(pixelYout),// x, y coordinates of any output pixels (only pixels inside triangle)\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t.out_pixel_depth(pixelDepth),\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t// depth (z-value) of any output pixels (only pixels inside triangle) - NOT YET IMPLEMENTED\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t.out_pixel_color(pixelColor));\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t// color of any output pixels (only pixels inside triangle));\\\\n\\\\t\\\\n/*always@(posedge iCLK or posedge reset)\\\\nbegin\\\\n\\\\tif(reset)\\\\n\\\\tbegin\\\\n\\\\t\\\\tcolInd\\\\t\\\\t<=\\\\t0;\\\\n\\\\tend\\\\n\\\\telse if (!iVIDEO_ON && blankDone==1'b0)\\\\n\\\\tbegin\\\\n\\\\t\\\\tif( colInd < 639 )\\\\n\\\\t\\\\tcolInd\\\\t<=\\\\tcolInd+1;\\\\n\\\\t\\\\telse\\\\n\\\\t\\\\tcolInd\\\\t<=\\\\t0;\\\\n\\\\tend\\\\nend\\\\n\\\\nalways@(posedge iCLK or posedge reset)\\\\nbegin\\\\n\\\\tif(reset)\\\\n\\\\tbegin\\\\n\\\\t\\\\trowInd\\\\t\\\\t<=\\\\t0;\\\\n\\\\tend\\\\n\\\\telse if (!iVIDEO_ON && blankDone==1'b0)\\\\n\\\\tbegin\\\\n\\\\t\\\\tif(colInd==0)\\\\n\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\tif( rowInd < 399 )\\\\n\\\\t\\\\t\\\\trowInd\\\\t<=\\\\trowInd+1;\\\\n\\\\t\\\\t\\\\telse\\\\n\\\\t\\\\t\\\\trowInd\\\\t<=\\\\t0;\\\\n\\\\t\\\\tend\\\\n\\\\tend\\\\nend*/\\\\n\\\\nalways@(posedge iCLK)\\\\nbegin\\\\n\\\\tif(resetBlank)\\\\n\\\\tbegin\\\\n\\\\t\\\\tcolInd\\\\t\\\\t<=\\\\tblanked1 ? primitive2_min[31:16] : primitive1_min[31:16];\\\\n\\\\tend\\\\n\\\\telse if (!iVIDEO_ON && blankDone==1'b0)\\\\n\\\\tbegin\\\\n\\\\t\\\\tif( colInd < ( blanked1 ? primitive2_max[31:16] : primitive1_max[31:16] ) )\\\\n\\\\t\\\\tcolInd\\\\t<=\\\\tcolInd+1'b1;\\\\n\\\\t\\\\telse\\\\n\\\\t\\\\tcolInd\\\\t<=\\\\tblanked1 ? primitive2_min[31:16] : primitive1_min[31:16];\\\\n\\\\tend\\\\nend\\\\n\\\\nalways@(posedge iCLK)\\\\nbegin\\\\n\\\\tif(resetBlank)\\\\n\\\\tbegin\\\\n\\\\t\\\\trowInd\\\\t\\\\t<=\\\\tblanked1 ? primitive2_min[15:0] : primitive1_min[15:0];\\\\n\\\\tend\\\\n\\\\telse if (!iVIDEO_ON && blankDone==1'b0)\\\\n\\\\tbegin\\\\n\\\\t\\\\tif(colInd==( blanked1 ? primitive2_min[15:0] : primitive1_min[31:16]))\\\\n\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\tif( rowInd < ( blanked1 ? primitive2_max[15:0] : primitive1_max[15:0] ))\\\\n\\\\t\\\\t\\\\trowInd\\\\t<=\\\\trowInd+1'b1;\\\\n\\\\t\\\\t\\\\telse\\\\n\\\\t\\\\t\\\\trowInd\\\\t<=\\\\tblanked1 ? primitive2_min[15:0] : primitive1_min[15:0];\\\\n\\\\t\\\\tend\\\\n\\\\tend\\\\nend\\\\n\\\\n\\\\n\\\\n\\\\n\\\\nendmodule"]
["module scb_cla32(x,y,cin,s,cout);\\\\n\\\\n\\\\toutput [31:0] s;\\\\n\\\\tinput [31:0] x,y;\\\\n\\\\toutput cout;\\\\n\\\\tinput cin;\\\\n\\\\twire [5:0] sel;\\\\n\\\\t\\\\n\\\\twire [2:0] sum0;\\\\n\\\\twire [3:0] temp0,temp0_1;\\\\n\\\\twire [3:0] sum1;\\\\n\\\\twire [4:0] temp1,temp1_1;\\\\n\\\\twire [4:0] sum2;\\\\n\\\\twire [5:0] temp2,temp2_1;\\\\n\\\\twire [4:0] sum3;\\\\n\\\\twire [5:0] temp3,temp3_1;\\\\n\\\\twire [5:0] sum4;\\\\n\\\\twire [6:0] temp4,temp4_1;\\\\n\\\\twire [6:0] sum5;\\\\n\\\\twire [7:0] temp5,temp5_1;\\\\n\\\\t\\\\n\\\\twire carry0, carry1, carry2, carry3, carry4, carry5;\\\\n\\\\n\\\\t//sum[0:1] (2)\\\\n\\\\tcla_2 r2(x[1:0],y[1:0],cin,s[1:0],sel[0]);\\\\n\\\\n\\\\t//sum[2:4] (3)\\\\n\\\\tcla_3 r3(x[4:2],y[4:2],1'b0,sum0,carry0);\\\\n\\\\tassign temp0 = {carry0,sum0[2:0]};\\\\n\\\\tbec_4 b4(temp0,temp0_1);\\\\n\\\\n\\\\tmux_2x1 m1(s[2],temp0[0],temp0_1[0],sel[0]);\\\\n\\\\tmux_2x1 m2(s[3],temp0[1],temp0_1[1],sel[0]);\\\\n\\\\tmux_2x1 m3(s[4],temp0[2],temp0_1[2],sel[0]);\\\\n\\\\tmux_2x1 m4(sel[1],temp0[3],temp0_1[3],sel[0]);\\\\n\\\\t\\\\n\\\\t//sum[5:8] (4)\\\\n\\\\tcla_4 r4(x[8:5],y[8:5],1'b0,sum1,carry1);\\\\n\\\\tassign temp1 = {carry1,sum1[3:0]};\\\\n\\\\tbec_5 b5(temp1,temp1_1);\\\\n\\\\n\\\\tmux_2x1 m5(s[5],temp1[0],temp1_1[0],sel[1]);\\\\n\\\\tmux_2x1 m6(s[6],temp1[1],temp1_1[1],sel[1]);\\\\n\\\\tmux_2x1 m7(s[7],temp1[2],temp1_1[2],sel[1]);\\\\n\\\\tmux_2x1 m8(s[8],temp1[3],temp1_1[3],sel[1]);\\\\n\\\\tmux_2x1 m9(sel[2],temp1[4],temp1_1[4],sel[1]);\\\\n\\\\n\\\\t//sum[9:13] (5)\\\\n\\\\tcla_5 r5(x[13:9],y[13:9],1'b0,sum2,carry2);\\\\n\\\\tassign temp2 = {carry2,sum2[4:0]};\\\\n\\\\tbec_6 b6(temp2,temp2_1);\\\\n\\\\n\\\\tmux_2x1 m10(s[9],temp2[0],temp2_1[0],sel[2]);\\\\n\\\\tmux_2x1 m11(s[10],temp2[1],temp2_1[1],sel[2]);\\\\n\\\\tmux_2x1 m12(s[11],temp2[2],temp2_1[2],sel[2]);\\\\n\\\\tmux_2x1 m13(s[12],temp2[3],temp2_1[3],sel[2]);\\\\n\\\\tmux_2x1 m14(s[13],temp2[4],temp2_1[4],sel[2]);\\\\n\\\\tmux_2x1 m15(sel[3],temp2[5],temp2_1[5],sel[2]);\\\\n\\\\t\\\\n\\\\t//sum[14:18] (5)\\\\n\\\\tcla_5 r5_1(x[18:14],y[18:14],1'b0,sum3,carry3);\\\\n\\\\tassign temp3 = {carry3,sum3[4:0]};\\\\n\\\\tbec_6 b6_1(temp3,temp3_1);\\\\n\\\\n\\\\tmux_2x1 m16(s[14],temp3[0],temp3_1[0],sel[3]);\\\\n\\\\tmux_2x1 m17(s[15],temp3[1],temp3_1[1],sel[3]);\\\\n\\\\tmux_2x1 m18(s[16],temp3[2],temp3_1[2],sel[3]);\\\\n\\\\tmux_2x1 m19(s[17],temp3[3],temp3_1[3],sel[3]);\\\\n\\\\tmux_2x1 m20(s[18],temp3[4],temp3_1[4],sel[3]);\\\\n\\\\tmux_2x1 m21(sel[4],temp3[5],temp3_1[5],sel[3]);\\\\n\\\\t\\\\n\\\\t//sum[19:24] (6)\\\\n\\\\tcla_6 r6(x[24:19],y[24:19],1'b0,sum4,carry4);\\\\n\\\\tassign temp4 = {carry4,sum4[5:0]};\\\\n\\\\tbec_7 b7(temp4,temp4_1);\\\\n\\\\n\\\\tmux_2x1 m22(s[19],temp4[0],temp4_1[0],sel[4]);\\\\n\\\\tmux_2x1 m23(s[20],temp4[1],temp4_1[1],sel[4]);\\\\n\\\\tmux_2x1 m24(s[21],temp4[2],temp4_1[2],sel[4]);\\\\n\\\\tmux_2x1 m25(s[22],temp4[3],temp4_1[3],sel[4]);\\\\n\\\\tmux_2x1 m26(s[23],temp4[4],temp4_1[4],sel[4]);\\\\n\\\\tmux_2x1 m27(s[24],temp4[5],temp4_1[5],sel[4]);\\\\n\\\\tmux_2x1 m28(sel[5],temp4[6],temp4_1[6],sel[4]);\\\\n\\\\t\\\\n\\\\t//sum[25:31] (7)\\\\n\\\\tcla_7 r7(x[31:25],y[31:25],1'b0,sum5,carry5);\\\\n\\\\tassign temp5 = {carry5,sum5[6:0]};\\\\n\\\\tbec_8 b8(temp5,temp5_1);\\\\n\\\\n\\\\tmux_2x1 m29(s[25],temp5[0],temp5_1[0],sel[5]);\\\\n\\\\tmux_2x1 m30(s[26],temp5[1],temp5_1[1],sel[5]);\\\\n\\\\tmux_2x1 m31(s[27],temp5[2],temp5_1[2],sel[5]);\\\\n\\\\tmux_2x1 m32(s[28],temp5[3],temp5_1[3],sel[5]);\\\\n\\\\tmux_2x1 m33(s[29],temp5[4],temp5_1[4],sel[5]);\\\\n\\\\tmux_2x1 m34(s[30],temp5[5],temp5_1[5],sel[5]);\\\\n\\\\tmux_2x1 m35(s[31],temp5[6],temp5_1[6],sel[5]);\\\\n\\\\tmux_2x1 m36(cout,temp5[7],temp5_1[7],sel[5]);\\\\n\\\\nendmodule"]
["module d_ff(q, d, clock, reset);\\\\n input d, clock, reset;\\\\n output q;\\\\n reg q;\\\\n always @ (posedge clock or negedge reset)\\\\n if(~reset)\\\\n q = 1'b0;\\\\n else\\\\n q = d;\\\\nendmodule", 'module reg_32bit(q, d, clock, reset);\\\\n input [31:0] d;\\\\n input clock, reset;\\\\n output [31:0] q;\\\\n genvar j;\\\\n generate\\\\n for(j = 0; j < 32; j = j + 1) begin: d_loop\\\\n d_ff ff(q[j], d[j], clock, reset);\\\\n end\\\\n endgenerate\\\\nendmodule', "module mux32_1(Out, Data00, Data01, Data02, Data03, Data04, Data05, Data06, Data07, Data08, Data09, Data10, Data11, Data12, Data13, Data14, Data15, Data16, Data17, Data18, Data19, Data20, Data21, Data22, Data23, Data24, Data25, Data26, Data27, Data28, Data29, Data30, Data31, Select);\\\\n input [31:0] Data00, Data01, Data02, Data03, Data04, Data05, Data06, Data07, Data08, Data09, Data10, Data11, Data12, Data13, Data14, Data15, Data16, Data17, Data18, Data19, Data20, Data21, Data22, Data23, Data24, Data25, Data26, Data27, Data28, Data29, Data30, Data31;\\\\n input [4:0] Select;\\\\n output [31:0] Out;\\\\n reg [31:0] Out;\\\\n always @ (Data00 or Data01 or Data02 or Data03 or Data04 or Data05 or Data06 or Data07 or Data08 or Data09 or Data10 or Data11 or Data12 or Data13 or Data14 or Data15 or Data16 or Data17 or Data18 or Data19 or Data20 or Data21 or Data22 or Data23 or Data24 or Data25 or Data26 or Data27 or Data28 or Data29 or Data30 or Data31 or Select)\\\\n case (Select)\\\\n 5'b00000: Out = Data00;\\\\n 5'b00001: Out = Data01;\\\\n 5'b00010: Out = Data02;\\\\n 5'b00011: Out = Data03;\\\\n 5'b00100: Out = Data04;\\\\n 5'b00101: Out = Data05;\\\\n 5'b00110: Out = Data06;\\\\n 5'b00111: Out = Data07;\\\\n 5'b01000: Out = Data08;\\\\n 5'b01001: Out = Data09;\\\\n 5'b01010: Out = Data10;\\\\n 5'b01011: Out = Data11;\\\\n 5'b01100: Out = Data12;\\\\n 5'b01101: Out = Data13;\\\\n 5'b01110: Out = Data14;\\\\n 5'b01111: Out = Data15;\\\\n 5'b10000: Out = Data16;\\\\n 5'b10001: Out = Data17;\\\\n 5'b10010: Out = Data18;\\\\n 5'b10011: Out = Data19;\\\\n 5'b10100: Out = Data20;\\\\n 5'b10101: Out = Data21;\\\\n 5'b10110: Out = Data22;\\\\n 5'b10111: Out = Data23;\\\\n 5'b11000: Out = Data24;\\\\n 5'b11001: Out = Data25;\\\\n 5'b11010: Out = Data26;\\\\n 5'b11011: Out = Data27;\\\\n 5'b11100: Out = Data28;\\\\n 5'b11101: Out = Data29;\\\\n 5'b11110: Out = Data30;\\\\n 5'b11111: Out = Data31;\\\\n endcase\\\\nendmodule", 'module RegFile_32(ReadData1, ReadData2, Clock, Reset, RegWrite, ReadReg1, ReadReg2, WriteRegNo, WriteData);\\\\n input Clock, Reset, RegWrite;\\\\n input [4:0] ReadReg1, ReadReg2, WriteRegNo;\\\\n input [31:0] WriteData;\\\\n output [31:0] ReadData1, ReadData2;\\\\n wire [31:0] Data0, Data1, Data2, Data3, Data4, Data5, Data6, Data7, Data8, Data9, Data10, Data11, Data12, Data13, Data14, Data15, Data16, Data17, Data18, Data19, Data20, Data21, Data22, Data23, Data24, Data25, Data26, Data27, Data28, Data29, Data30, Data31;\\\\n wire [31:0] Decode;\\\\n wire [31:0]c;\\\\n genvar j;\\\\n decoder5_32 dec(Decode, WriteRegNo);\\\\n generate\\\\n for(j = 0; j < 32; j = j + 1) begin: and_loop\\\\n and g(c[j], RegWrite, Decode[j], Clock);\\\\n end\\\\n endgenerate\\\\n reg_32bit r0(Data0, WriteData, c[0], Reset);\\\\n reg_32bit r1(Data1, WriteData, c[1], Reset);\\\\n reg_32bit r2(Data2, WriteData, c[2], Reset);\\\\n reg_32bit r3(Data3, WriteData, c[3], Reset);\\\\n reg_32bit r4(Data4, WriteData, c[4], Reset);\\\\n reg_32bit r5(Data5, WriteData, c[5], Reset);\\\\n reg_32bit r6(Data6, WriteData, c[6], Reset);\\\\n reg_32bit r7(Data7, WriteData, c[7], Reset);\\\\n reg_32bit r8(Data8, WriteData, c[8], Reset);\\\\n reg_32bit r9(Data9, WriteData, c[9], Reset);\\\\n reg_32bit r10(Data10, WriteData, c[10], Reset);\\\\n reg_32bit r11(Data11, WriteData, c[11], Reset);\\\\n reg_32bit r12(Data12, WriteData, c[12], Reset);\\\\n reg_32bit r13(Data13, WriteData, c[13], Reset);\\\\n reg_32bit r14(Data14, WriteData, c[14], Reset);\\\\n reg_32bit r15(Data15, WriteData, c[15], Reset);\\\\n reg_32bit r16(Data16, WriteData, c[16], Reset);\\\\n reg_32bit r17(Data17, WriteData, c[17], Reset);\\\\n reg_32bit r18(Data18, WriteData, c[18], Reset);\\\\n reg_32bit r19(Data19, WriteData, c[19], Reset);\\\\n reg_32bit r20(Data20, WriteData, c[20], Reset);\\\\n reg_32bit r21(Data21, WriteData, c[21], Reset);\\\\n reg_32bit r22(Data22, WriteData, c[22], Reset);\\\\n reg_32bit r23(Data23, WriteData, c[23], Reset);\\\\n reg_32bit r24(Data24, WriteData, c[24], Reset);\\\\n reg_32bit r25(Data25, WriteData, c[25], Reset);\\\\n reg_32bit r26(Data26, WriteData, c[26], Reset);\\\\n reg_32bit r27(Data27, WriteData, c[27], Reset);\\\\n reg_32bit r28(Data28, WriteData, c[28], Reset);\\\\n reg_32bit r29(Data29, WriteData, c[29], Reset);\\\\n reg_32bit r30(Data30, WriteData, c[30], Reset);\\\\n reg_32bit r31(Data31, WriteData, c[31], Reset);\\\\n mux32_1 m0(ReadData1, Data00, Data01, Data02, Data03, Data04, Data05, Data06, Data07, Data08, Data09, Data10, Data11, Data12, Data13, Data14, Data15, Data16, Data17, Data18, Data19, Data20, Data21, Data22, Data23, Data24, Data25, Data26, Data27, Data28, Data29, Data30, Data31, ReadReg1);\\\\n mux32_1 m1(ReadData2, Data00, Data01, Data02, Data03, Data04, Data05, Data06, Data07, Data08, Data09, Data10, Data11, Data12, Data13, Data14, Data15, Data16, Data17, Data18, Data19, Data20, Data21, Data22, Data23, Data24, Data25, Data26, Data27, Data28, Data29, Data30, Data31, ReadReg2);\\\\nendmodule']
["module hamming_decoder_serial(\\\\n\\\\tinput [20:0] e,\\\\n\\\\tinput clk,\\\\n\\\\toutput reg [15:0] op,\\\\n output reg [4:0] p\\\\n\\\\t);\\\\nreg [4:0] i;\\\\ninitial p=0;\\\\ninitial i=1;\\\\nalways @ (clk) begin\\\\n\\\\tif(i==22) begin\\\\t\\\\n\\\\tcase(p) \\\\n\\\\t\\\\n\\\\t5'd3: begin \\\\n\\\\top[0]=~e[2];\\\\n\\\\top[1]=e[4];\\\\n\\\\top[2]=e[5];\\\\n\\\\top[3]=e[6];\\\\n\\\\top[4]=e[8];\\\\n\\\\top[5]=e[9];\\\\n\\\\top[6]=e[10];\\\\n\\\\top[7]=e[11];\\\\n\\\\top[8]=e[12];\\\\n\\\\top[9]=e[13];\\\\n\\\\top[10]=e[14];\\\\n\\\\top[11]=e[16];\\\\n\\\\top[12]=e[17];\\\\n\\\\top[13]=e[18];\\\\n\\\\top[14]=e[19];\\\\n\\\\top[15]=e[20];\\\\n\\\\tend\\\\n\\\\t5'd5: begin\\\\n\\\\top[0]=e[2];\\\\n\\\\top[1]=~e[4];\\\\n\\\\top[2]=e[5];\\\\n\\\\top[3]=e[6];\\\\n\\\\top[4]=e[8];\\\\n\\\\top[5]=e[9];\\\\n\\\\top[6]=e[10];\\\\n\\\\top[7]=e[11];\\\\n\\\\top[8]=e[12];\\\\n\\\\top[9]=e[13];\\\\n\\\\top[10]=e[14];\\\\n\\\\top[11]=e[16];\\\\n\\\\top[12]=e[17];\\\\n\\\\top[13]=e[18];\\\\n\\\\top[14]=e[19];\\\\n\\\\top[15]=e[20];\\\\n\\\\tend\\\\n\\\\t5'd6: begin\\\\n\\\\top[0]=e[2];\\\\n\\\\top[1]=e[4];\\\\n\\\\top[2]=~e[5];\\\\n\\\\top[3]=e[6];\\\\n\\\\top[4]=e[8];\\\\n\\\\top[5]=e[9];\\\\n\\\\top[6]=e[10];\\\\n\\\\top[7]=e[11];\\\\n\\\\top[8]=e[12];\\\\n\\\\top[9]=e[13];\\\\n\\\\top[10]=e[14];\\\\n\\\\top[11]=e[16];\\\\n\\\\top[12]=e[17];\\\\n\\\\top[13]=e[18];\\\\n\\\\top[14]=e[19];\\\\n\\\\top[15]=e[20];code word \\\\n\\\\tend\\\\n\\\\n\\\\t5'd7: begin\\\\n\\\\t\\\\t\\\\n\\\\top[0]=e[2];\\\\n\\\\top[1]=e[4];\\\\n\\\\top[2]=e[5];\\\\n\\\\top[3]=~e[6];\\\\n\\\\top[4]=e[8];\\\\n\\\\top[5]=e[9];\\\\n\\\\top[6]=e[10];\\\\n\\\\top[7]=e[11];\\\\n\\\\top[8]=e[12];\\\\n\\\\top[9]=e[13];\\\\n\\\\top[10]=e[14];\\\\n\\\\top[11]=e[16];\\\\n\\\\top[12]=e[17];\\\\n\\\\top[13]=e[18];\\\\n\\\\top[14]=e[19];\\\\n\\\\top[15]=e[20];\\\\n\\\\tend\\\\n\\\\n\\\\t5'd9: begin\\\\n\\\\t\\\\t\\\\n\\\\top[0]=e[2];\\\\n\\\\top[1]=e[4];\\\\n\\\\top[2]=e[5];\\\\n\\\\top[3]=e[6];\\\\n\\\\top[4]=~e[8];\\\\n\\\\top[5]=e[9];\\\\n\\\\top[6]=e[10];\\\\n\\\\top[7]=e[11];\\\\n\\\\top[8]=e[12];\\\\n\\\\top[9]=e[13];\\\\n\\\\top[10]=e[14];\\\\n\\\\top[11]=e[16];\\\\n\\\\top[12]=e[17];\\\\n\\\\top[13]=e[18];\\\\n\\\\top[14]=e[19];\\\\n\\\\top[15]=e[20];\\\\n\\\\tend\\\\n\\\\n\\\\t5'd10: begin\\\\n\\\\t\\\\t\\\\n\\\\top[0]=e[2];\\\\n\\\\top[1]=e[4];\\\\n\\\\top[2]=e[5];\\\\n\\\\top[3]=e[6];\\\\n\\\\top[4]=e[8];\\\\n\\\\top[5]=~e[9];\\\\n\\\\top[6]=e[10];\\\\n\\\\top[7]=e[11];\\\\n\\\\top[8]=e[12];\\\\n\\\\top[9]=e[13];\\\\n\\\\top[10]=e[14];\\\\n\\\\top[11]=e[16];\\\\n\\\\top[12]=e[17];\\\\n\\\\top[13]=e[18];\\\\n\\\\top[14]=e[19];\\\\n\\\\top[15]=e[20];\\\\n\\\\tend\\\\n\\\\n\\\\t5'd11: begin\\\\n\\\\t\\\\t\\\\n\\\\top[0]=e[2];\\\\n\\\\top[1]=e[4];\\\\n\\\\top[2]=e[5];\\\\n\\\\top[3]=e[6];\\\\n\\\\top[4]=e[8];\\\\n\\\\top[5]=e[9];\\\\n\\\\top[6]=~e[10];\\\\n\\\\top[7]=e[11];\\\\n\\\\top[8]=e[12];\\\\n\\\\top[9]=e[13];\\\\n\\\\top[10]=e[14];\\\\n\\\\top[11]=e[16];\\\\n\\\\top[12]=e[17];\\\\n\\\\top[13]=e[18];\\\\n\\\\top[14]=e[19];\\\\n\\\\top[15]=e[20];\\\\n\\\\tend\\\\n\\\\n\\\\t5'd12: begin\\\\n\\\\t\\\\t\\\\n\\\\top[0]=e[2];\\\\n\\\\top[1]=e[4];\\\\n\\\\top[2]=e[5];\\\\n\\\\top[3]=e[6];\\\\n\\\\top[4]=e[8];\\\\n\\\\top[5]=e[9];\\\\n\\\\top[6]=e[10];\\\\n\\\\top[7]=~e[11];\\\\n\\\\top[8]=e[12];\\\\n\\\\top[9]=e[13];\\\\n\\\\top[10]=e[14];\\\\n\\\\top[11]=e[16];\\\\n\\\\top[12]=e[17];\\\\n\\\\top[13]=e[18];\\\\n\\\\top[14]=e[19];\\\\n\\\\top[15]=e[20];\\\\n\\\\tend\\\\n\\\\n\\\\t5'd13: begin\\\\n\\\\t\\\\t\\\\n\\\\top[0]=e[2];\\\\n\\\\top[1]=e[4];\\\\n\\\\top[2]=e[5];\\\\n\\\\top[3]=e[6];\\\\n\\\\top[4]=e[8];\\\\n\\\\top[5]=e[9];\\\\n\\\\top[6]=e[10];\\\\n\\\\top[7]=e[11];\\\\n\\\\top[8]=~e[12];\\\\n\\\\top[9]=e[13];\\\\n\\\\top[10]=e[14];\\\\n\\\\top[11]=e[16];\\\\n\\\\top[12]=e[17];\\\\n\\\\top[13]=e[18];\\\\n\\\\top[14]=e[19];\\\\n\\\\top[15]=e[20];\\\\n\\\\tend\\\\n\\\\n\\\\t5'd14: begin\\\\n\\\\t\\\\t\\\\n\\\\top[0]=e[2];\\\\n\\\\top[1]=e[4];\\\\n\\\\top[2]=e[5];\\\\n\\\\top[3]=e[6];\\\\n\\\\top[4]=e[8];\\\\n\\\\top[5]=e[9];\\\\n\\\\top[6]=e[10];\\\\n\\\\top[7]=e[11];\\\\n\\\\top[8]=e[12];\\\\n\\\\top[9]=e[13];\\\\n\\\\top[10]=~e[14];\\\\n\\\\top[11]=e[16];\\\\n\\\\top[12]=e[17];\\\\n\\\\top[13]=e[18];\\\\n\\\\top[14]=e[19];\\\\n\\\\top[15]=e[20];\\\\n\\\\tend\\\\n\\\\n\\\\t5'd15: begin\\\\n\\\\t\\\\t\\\\n\\\\top[0]=e[2];\\\\n\\\\top[1]=e[4];\\\\n\\\\top[2]=e[5];\\\\n\\\\top[3]=e[6];\\\\n\\\\top[4]=e[8];\\\\n\\\\top[5]=e[9];\\\\n\\\\top[6]=e[10];\\\\n\\\\top[7]=e[11];\\\\n\\\\top[8]=e[12];\\\\n\\\\top[9]=e[13];\\\\n\\\\top[10]=~e[14];\\\\n\\\\top[11]=e[16];\\\\n\\\\top[12]=e[17];\\\\n\\\\top[13]=e[18];\\\\n\\\\top[14]=e[19];\\\\n\\\\top[15]=e[20];\\\\n\\\\tend\\\\n\\\\t5'd17: begin\\\\n\\\\t\\\\t\\\\n\\\\top[0]=e[2];\\\\n\\\\top[1]=e[4];\\\\n\\\\top[2]=e[5];\\\\n\\\\top[3]=e[6];\\\\n\\\\top[4]=e[8];\\\\n\\\\top[5]=e[9];\\\\n\\\\top[6]=e[10];\\\\n\\\\top[7]=e[11];\\\\n\\\\top[8]=e[12];\\\\n\\\\top[9]=e[13];\\\\n\\\\top[10]=e[14];\\\\n\\\\top[11]=~e[16];\\\\n\\\\top[12]=e[17];\\\\n\\\\top[13]=e[18];\\\\n\\\\top[14]=e[19];\\\\n\\\\top[15]=e[20];\\\\n\\\\tend\\\\n\\\\n\\\\t5'd18: begin\\\\n\\\\t\\\\t\\\\n\\\\top[0]=e[2];\\\\n\\\\top[1]=e[4];\\\\n\\\\top[2]=e[5];\\\\n\\\\top[3]=e[6];\\\\n\\\\top[4]=e[8];\\\\n\\\\top[5]=e[9];\\\\n\\\\top[6]=e[10];\\\\n\\\\top[7]=e[11];\\\\n\\\\top[8]=e[12];\\\\n\\\\top[9]=e[13];\\\\n\\\\top[10]=e[14];\\\\n\\\\top[11]=e[16];\\\\n\\\\top[12]=~e[17];\\\\n\\\\top[13]=e[18];\\\\n\\\\top[14]=e[19];\\\\n\\\\top[15]=e[20];\\\\n\\\\tend\\\\n\\\\n\\\\t5'd19: begin\\\\n\\\\t\\\\t\\\\n\\\\top[0]=e[2];\\\\n\\\\top[1]=e[4];\\\\n\\\\top[2]=e[5];\\\\n\\\\top[3]=e[6];\\\\n\\\\top[4]=e[8];\\\\n\\\\top[5]=e[9];\\\\n\\\\top[6]=e[10];\\\\n\\\\top[7]=e[11];\\\\n\\\\top[8]=e[12];\\\\n\\\\top[9]=e[13];\\\\n\\\\top[10]=e[14];\\\\n\\\\top[11]=e[16];\\\\n\\\\top[12]=e[17];\\\\n\\\\top[13]=~e[18];\\\\n\\\\top[14]=e[19];\\\\n\\\\top[15]=e[20];\\\\n\\\\tend\\\\n\\\\n\\\\t5'd20: begin\\\\n\\\\t\\\\t\\\\n\\\\top[0]=e[2];\\\\n\\\\top[1]=e[4];\\\\n\\\\top[2]=e[5];\\\\n\\\\top[3]=e[6];\\\\n\\\\top[4]=e[8];\\\\n\\\\top[5]=e[9];\\\\n\\\\top[6]=e[10];\\\\n\\\\top[7]=e[11];\\\\n\\\\top[8]=e[12];\\\\n\\\\top[9]=e[13];\\\\n\\\\top[10]=e[14];\\\\n\\\\top[11]=e[16];\\\\n\\\\top[12]=e[17];\\\\n\\\\top[13]=e[18];\\\\n\\\\top[14]=~e[19];\\\\n\\\\top[15]=e[20];\\\\n\\\\tend\\\\n\\\\n\\\\t5'd21: begin\\\\t\\\\n\\\\top[0]=e[2];\\\\n\\\\top[1]=e[4];\\\\n\\\\top[2]=e[5];\\\\n\\\\top[3]=e[6];\\\\n\\\\top[4]=e[8];\\\\n\\\\top[5]=e[9];\\\\n\\\\top[6]=e[10];\\\\n\\\\top[7]=e[11];\\\\n\\\\top[8]=e[12];\\\\n\\\\top[9]=e[13];\\\\n\\\\top[10]=e[14];\\\\n\\\\top[11]=e[16];\\\\n\\\\top[12]=e[17];\\\\n\\\\top[13]=e[18];\\\\n\\\\top[14]=e[19];\\\\n\\\\top[15]=~e[20];\\\\n\\\\tend\\\\n\\\\n\\\\t5'd0: begin\\\\n\\\\top[0]=e[2];\\\\n\\\\top[1]=e[4];\\\\n\\\\top[2]=e[5];\\\\n\\\\top[3]=e[6];\\\\n\\\\top[4]=e[8];\\\\n\\\\top[5]=e[9];\\\\n\\\\top[6]=e[10];\\\\n\\\\top[7]=e[11];\\\\n\\\\top[8]=e[12];\\\\n\\\\top[9]=e[13];\\\\n\\\\top[10]=e[14];\\\\n\\\\top[11]=e[16];\\\\n\\\\top[12]=e[17];\\\\n\\\\top[13]=e[18];\\\\n\\\\top[14]=e[19];\\\\n\\\\top[15]=e[20];\\\\n\\\\tend\\\\n\\\\n\\\\tendcase\\\\n\\\\t\\\\n\\\\tend\\\\n\\\\n\\\\telse begin\\\\n\\\\t\\\\tif(i[0]==1) p[0]=p[0]^e[i-1];\\\\n\\\\t\\\\tif(i[1]==1) p[1]=p[1]^e[i-1];\\\\n\\\\t\\\\tif(i[2]==1) p[2]=p[2]^e[i-1];\\\\n\\\\t\\\\tif(i[3]==1) p[3]=p[3]^e[i-1];\\\\n\\\\t\\\\tif(i[4]==1) p[4]=p[4]^e[i-1];\\\\n\\\\t\\\\ti=i+1;\\\\n\\\\tend\\\\nend\\\\nendmodule"]
["module paddsb (input [15:0] A, input [15:0] B, output [15:0] out);\\\\n\\\\n\\\\twire AE_of, BF_of, CG_of, DH_of;\\\\n\\\\twire AE_cout, BF_cout, CG_cout, DH_cout;\\\\n\\\\t\\\\n\\\\twire [3:0] AE_out, BF_out, CG_out, DH_out;\\\\n\\\\twire [3:0] AE_sat, BF_sat, CG_sat, DH_sat;\\\\n\\\\n\\\\tcla_4bit AE(.A(A[15:12]), .B(B[15:12]), .Cin(1'b0), .S(AE_out), .Cout(AE_cout), .ovfl(AE_of));\\\\n\\\\tcla_4bit BF(.A(A[11:8]), .B(B[11:8]), .Cin(1'b0), .S(BF_out), .Cout(BF_cout), .ovfl(BF_of));\\\\n\\\\tcla_4bit CG(.A(A[7:4]), .B(B[7:4]), .Cin(1'b0), .S(CG_out), .Cout(CG_cout), .ovfl(CG_of));\\\\n\\\\tcla_4bit DH(.A(A[3:0]), .B(B[3:0]), .Cin(1'b0), .S(DH_out), .Cout(DH_cout), .ovfl(DH_of));\\\\n\\\\t\\\\n\\\\tassign AE_sat = AE_of ? (AE_cout ? 4'b1000 : 4'b0111) : AE_out;\\\\n\\\\tassign BF_sat = BF_of ? (BF_cout ? 4'b1000 : 4'b0111) : BF_out;\\\\n\\\\tassign CG_sat = CG_of ? (CG_cout ? 4'b1000 : 4'b0111) : CG_out;\\\\n\\\\tassign DH_sat = DH_of ? (DH_cout ? 4'b1000 : 4'b0111) : DH_out;\\\\n\\\\t\\\\n\\\\tassign out = {AE_sat, BF_sat, CG_sat, DH_sat};\\\\nendmodule"]
["module alu(output wire [3:0] R, output wire zero, carry, sign, input wire [3:0] A, B, input wire [1:0] ALUOp, input wire L);\\\\n\\\\n//Celda aritmetico logica de 1 bit:\\\\tcal(output wire out, c_out, input wire a, b, l, c_in, input wire [1:0] s);\\\\n//Mux 2 a 1 de 4 bits\\\\t\\\\t\\\\tmux2_4(output wire [3:0] out, input wire [3:0] a, b, input wire s);\\\\n//Complementador a 1\\\\t\\\\t\\\\tcompl1(output wire [3:0] Sal, input wire [3:0] Ent, input wire cpl);\\\\n//\\\\n\\\\nwire [3:0] OP1, OP2, cpl_in;\\\\nwire Cin1, Cin2, Cin3, cpl, op1_A, op1_B;\\\\n\\\\n//CABLEADO DE LOS MULTIPLEXORES\\\\nassign op1_A = L | (~ALUOp[1]);\\\\nassign op1_B = L | (~ALUOp[1]) | ALUOp[0];\\\\nassign cpl = ( (~L) & ALUOp[1] ) | ( (~L) & ALUOp[0]);\\\\n\\\\n\\\\n//INSTANCIAS DE LOS MULTIPLEXORES Y EL COMPLEMENTADOR\\\\nmux2_4 mux0(OP1, 4'b0000, A, op1_A);\\\\nmux2_4 mux1(cpl_in, A, B, op1_B);\\\\n\\\\ncompl1 complementador(OP2, cpl_in, cpl);\\\\n\\\\n//INSTACIAS DE LAS CELDAS ARITM\\\\u00c9TICO-L\\\\u00d3GICAS\\\\ncal cal0(R[0], Cin1, OP1[0], OP2[0], L, cpl, ALUOp);\\\\ncal cal1(R[1], Cin2, OP1[1], OP2[1], L, Cin1, ALUOp);\\\\ncal cal2(R[2], Cin3, OP1[2], OP2[2], L, Cin2, ALUOp);\\\\ncal cal3(R[3], carry, OP1[3], OP2[3], L, Cin3, ALUOp);\\\\n\\\\n//ASIGNACI\\\\u00d3N DE LA SALIDA ZERO\\\\nassign zero = ( R == 4'b0000 )? 1'b1: 1'b0;\\\\n\\\\n//ASIGNACI\\\\u00d3N DE LA SALIDA SIGN\\\\nassign sign = R[3];\\\\n\\\\n\\\\nendmodule"]
["module MicrodePruebas(clk, rst, REF, POT, PWM, InstruccionIn_IR, WrtAddrs, WTReady, WrtEna, PC, InstruccionOut_IR, OperaA, OperaBBancos,OperaBALU, WrDat);\\\\n\\\\n//Entradas\\\\ninput clk, rst;\\\\ninput [17:0]REF, POT;\\\\ninput [31:0]InstruccionIn_IR;\\\\ninput [3:0]WrtAddrs;\\\\ninput WrtEna;\\\\ninput WTReady;\\\\noutput [17:0]PWM;\\\\noutput [3:0]PC;\\\\noutput [31:0]InstruccionOut_IR;\\\\noutput [17:0]WrDat;\\\\noutput [17:0]OperaA, OperaBBancos,OperaBALU;\\\\n\\\\n\\\\n//Salidas\\\\n\\\\n\\\\n//Formato de la Instruccion\\\\nwire [3:0]AddrsRt;\\\\nwire [3:0]AddrsRs;\\\\nwire [3:0]AddrsRd;\\\\nwire [15:0]Inmediate;\\\\nwire [4:0]Shamt;\\\\nwire [5:0]funct;\\\\nwire [5:0]opcode;\\\\n//Fetch\\\\n\\\\n\\\\n//Decodificacion de la Instruccion\\\\n\\\\nwire RST_PC;\\\\n\\\\n//Ejecucion\\\\n\\\\nwire [17:0]ExtSign;\\\\n\\\\n//CONTROL\\\\nwire [5:0]CONTROL;\\\\nwire CE_MEM,SEL_OPERAB,REG_WR,SEL_DEST;\\\\nwire [1:0]LU_OPCODE;\\\\n//Escritura de Programa\\\\n\\\\nwire [3:0]AddDestino;\\\\n\\\\nRAM32bits InstructionRegister(clk, InstruccionIn_IR, InstruccionOut_IR, WrtAddrs,PC,WrtEna);\\\\n\\\\nassign opcode = InstruccionOut_IR[31:26];\\\\nassign AddrsRs = InstruccionOut_IR[24:21];\\\\nassign AddrsRt = InstruccionOut_IR[19:16];\\\\nassign AddrsRd = InstruccionOut_IR[14:11];\\\\nassign Shamt = InstruccionOut_IR[10:6];\\\\nassign funct = InstruccionOut_IR[5:0];\\\\nassign Inmediate = InstruccionOut_IR[20:0];\\\\n\\\\n\\\\nBancoRegistros BankReg(clk, rst,REG_WR, WrDat,AddrsRs ,AddrsRt, AddDestino, REF, POT, PWM,OperaA, OperaBBancos);\\\\nConta4b PC1(RST_PC, clk, WTReady&&CE_MEM, PC);\\\\nassign AddDestino = SEL_DEST ? AddrsRt : AddrsRd;\\\\n\\\\n\\\\nALU AALU(LU_OPCODE,OperaA,OperaBALU,WrDat);\\\\n//Bloque Extension de Signo\\\\nassign ExtSign = {2*{Inmediate[15]}, Inmediate};\\\\nassign OperaBALU = SEL_OPERAB ? ExtSign : OperaBBancos; \\\\n\\\\n\\\\nassign CE_MEM=CONTROL[0];\\\\nassign LU_OPCODE=CONTROL[2:1];\\\\nassign SEL_OPERAB=CONTROL[3];\\\\nassign REG_WR=CONTROL[4];\\\\nassign SEL_DEST=CONTROL[5];\\\\n//\\\\n\\\\nControlControl CCPU(opcode,funct,WTReady,CONTROL);\\\\n\\\\nTimer5ms Time(clk,rst,1'b1,RST_PC);\\\\n\\\\nendmodule"]
["module Mod_Teste (\\\\n//Clocks\\\\ninput CLOCK_27, CLOCK_50,\\\\n//Chaves e Botoes\\\\ninput [3:0] KEY,\\\\ninput [17:0] SW,\\\\n//Displays de 7 seg e LEDs\\\\noutput [0:6] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7,\\\\noutput [8:0] LEDG,\\\\noutput [17:0] LEDR,\\\\n//Serial\\\\noutput UART_TXD,\\\\ninput UART_RXD,\\\\ninout [7:0] LCD_DATA,\\\\noutput LCD_ON, LCD_BLON, LCD_RW, LCD_EN, LCD_RS,\\\\n//GPIO\\\\ninout [35:0] GPIO_0, GPIO_1\\\\n);\\\\nassign GPIO_1 = 36'hzzzzzzzzz;\\\\nassign GPIO_0 = 36'hzzzzzzzzz;\\\\nassign LCD_ON = 1'b1;\\\\nassign LCD_BLON = 1'b1;\\\\nwire [7:0] w_d0x0, w_d0x1, w_d0x2, w_d0x3, w_d0x4, w_d0x5,\\\\nw_d1x0, w_d1x1, w_d1x2, w_d1x3, w_d1x4, w_d1x5;\\\\nLCD_TEST MyLCD (\\\\n.iCLK ( CLOCK_50 ),\\\\n.iRST_N ( KEY[0] ),\\\\n.d0x0(w_d0x0),.d0x1(w_d0x1),.d0x2(w_d0x2),.d0x3(w_d0x3),.d0x4(w_d0x4),.d0x5(w_d0x5),\\\\n.d1x0(w_d1x0),.d1x1(w_d1x1),.d1x2(w_d1x2),.d1x3(w_d1x3),.d1x4(w_d1x4),.d1x5(w_d1x5),\\\\n.LCD_DATA( LCD_DATA ),\\\\n.LCD_RW ( LCD_RW ),\\\\n.LCD_EN ( LCD_EN ),\\\\n.LCD_RS ( LCD_RS )\\\\n);\\\\n//---------- modifique a partir daqui --------\\\\n\\\\n\\\\n\\\\n\\\\n//------------------Sprint1---------------------\\\\n//---------- Unidade l\\\\u00c3\\\\u00b3gica Aritm\\\\u00c3\\\\u00a9tica -------\\\\n// ULA minha_ula(\\\\n// .sel ( SW [17] ),\\\\n// .input_a ( SW [3:0] ),\\\\n// .input_b ( SW [7:4] ),\\\\n// .output_s ( LEDR [3:0] ),\\\\n// .ovf ( LEDG [0] )\\\\n// );\\\\n\\\\n//----------------------------------------------\\\\n//------------------Sprint2---------------------\\\\n// wire w_clk_1hz, w_clk_12hz;\\\\n// wire [3:0] w_counter_value;\\\\n// assign HEX3[0:6] = SW[6:0];\\\\n// assign LEDG[0] = w_clk_1hz;\\\\n// decod_hexa2_7seg mydecod_inst01(\\\\n// .bincode ( SW [11:8] ),\\\\n// .pinoutdisplay7segment ( HEX0[0: 6] )\\\\n \\\\n// );\\\\n// decod_hexa2_7seg mydecod_inst02(\\\\n// .bincode ( w_counter_value ),\\\\n// .pinoutdisplay7segment ( HEX1[0: 6] )\\\\n// );\\\\n\\\\n\\\\n// count_M10 mycount_M10_inst01(\\\\n// .clk ( w_clk_1hz ),\\\\n// .rst ( KEY[3] ),\\\\n// .counter_value ( w_counter_value ) \\\\n// );\\\\n// frequencydivider #( .flag_ovf_mytime ( 25000000 ))\\\\n// myfreq_inst01(\\\\n// .clk ( CLOCK_50 ),\\\\n// .rst ( KEY[1] ),\\\\n// .myclk ( w_clk_1hz ) \\\\n// );\\\\n\\\\n// frequencydivider #( .flag_ovf_mytime ( 4166667 ))\\\\n// myfreq_inst02(\\\\n// .clk ( CLOCK_50 ),\\\\n// .rst ( KEY[1] ),\\\\n// .myclk ( w_clk_12hz ) \\\\n// );\\\\n\\\\n// seven_segment_loop myloop(\\\\n\\\\n// .clk ( w_clk_12hz ),\\\\n// .pinoutdisplay7segment ( HEX4[0: 6] )\\\\n// );\\\\n//------------------Sprint3---------------------\\\\n//-----------------Banco de Registradores-------\\\\n\\\\n// RegisterFile meu_registrador(\\\\n// \\\\t.clk\\\\t\\\\t(\\\\t\\\\tKEY[ 1]\\\\t ),\\\\n// \\\\t.we3\\\\t\\\\t(\\\\t\\\\tSW [ 17]\\\\t ),\\\\n// \\\\t.wa3\\\\t\\\\t(\\\\t\\\\tSW [16:14]\\\\t ),\\\\n// \\\\t.ra1\\\\t\\\\t(\\\\t\\\\tSW [13:11]\\\\t ),\\\\n// \\\\t.ra2\\\\t\\\\t(\\\\t\\\\tSW [10: 8] \\\\t ),\\\\n// \\\\t.wd3\\\\t\\\\t(\\\\t\\\\tSW\\\\t[7\\\\t: 0] ),\\\\n// \\\\t.rd1\\\\t\\\\t(\\\\t\\\\tw_d0x0[7:0]\\\\t ),\\\\n// .rst ( KEY[ 2] ),\\\\n// \\\\t.rd2\\\\t\\\\t(\\\\t\\\\tw_d0x1[7:0]\\\\t )\\\\n// );\\\\n// decod_hexa2_7seg displayWD3_LSB(\\\\n// .bincode ( SW[3:0] ),\\\\n// .pinoutdisplay7segment ( HEX0 )\\\\n// );\\\\n\\\\n// decod_hexa2_7seg displayWD3_MSB(\\\\n// .bincode ( SW[7:4] ),\\\\n// .pinoutdisplay7segment ( HEX1 )\\\\n// );\\\\n//------------------Sprint4-----------------------\\\\n//-------Banco de Registradores + ULA 5_OP-------\\\\n\\\\n// logic [7:0] w_rd1SrcA, w_rd2, w_SrcB, w_ULAResultWd3;\\\\n// RegisterFile meu_registrador(\\\\n// \\\\t.rst \\\\t\\\\t(\\\\t\\\\t\\\\t1\\\\t\\\\t\\\\t),\\\\n// \\\\t.clk\\\\t\\\\t(\\\\t\\\\tKEY[ 1]\\\\t\\\\t),\\\\n// \\\\t.we3\\\\t\\\\t(\\\\t\\\\t1'b1\\\\t\\\\t\\\\t),\\\\n// \\\\t.wa3\\\\t\\\\t(\\\\t\\\\tSW [16:14]\\\\t\\\\t),\\\\n// \\\\t.ra1\\\\t\\\\t(\\\\t\\\\tSW [13:11]\\\\t\\\\t),\\\\n// \\\\t.ra2\\\\t\\\\t(\\\\t\\\\t3'b010\\\\t \\\\t\\\\t),\\\\n// \\\\t.wd3\\\\t\\\\t(\\\\t\\\\tSW\\\\t[7\\\\t: 0]\\\\t),\\\\n// \\\\t.rd1\\\\t\\\\t(\\\\t\\\\tw_rd1SrcA\\\\t\\\\t),\\\\n// \\\\t.rd2\\\\t\\\\t(\\\\t\\\\tw_rd2 \\\\t\\\\t)\\\\n// );\\\\n// ula minha_ula_5o(\\\\n// \\\\t.ScrA\\\\t\\\\t(\\\\t\\\\tw_rd1SrcA\\\\t\\\\t),\\\\n// \\\\t.ScrB\\\\t\\\\t(\\\\t\\\\tw_SrcB ),\\\\n// \\\\t.ULAControl\\\\t(\\\\t\\\\tSW[10:8]\\\\t\\\\t),\\\\n// \\\\t.Z\\\\t\\\\t\\\\t(\\\\t\\\\tLEDG[0]\\\\t\\\\t\\\\t),\\\\n// \\\\t.ULAResult (\\\\t\\\\tw_ULAResultWd3\\\\t)\\\\n// );\\\\n// assign LEDG[1] = KEY[1]\\\\t\\\\t\\\\t\\\\t;\\\\n// assign w_d0x0 = w_rd1SrcA\\\\t\\\\t\\\\t;\\\\n// assign w_d1x0 = w_rd2\\\\t\\\\t\\\\t\\\\t;\\\\n// assign w_d1x1 = w_SrcB\\\\t\\\\t\\\\t\\\\t;\\\\n// assign w_d0x4 = w_ULAResultWd3\\\\t\\\\t;\\\\n// assign w_SrcB = SW[17] ? 8'h07 : w_rd2;\\\\n\\\\n// --------------------------------------------------\\\\n\\\\n//------------------Sprint5--------------------------\\\\n//------- CPU v0.1 ------------\\\\n\\\\n // wire [7 :0] w_PC ;\\\\n // wire [7 :0] w_PCp1 ;\\\\n // wire [31:0] w_Inst ;\\\\n // wire [4 :0] w_wa3 ;\\\\n // wire w_RegDst ;\\\\n // wire [7 :0] w_SrcB ;\\\\n // wire w_ULASrc ;\\\\n // wire [7 :0] w_rd1SrcA ;\\\\n // wire [2 :0] w_ULAControl ;\\\\n // wire [7 :0] w_ULAResultWd3 ;\\\\n // wire [7 :0] w_rd2 ;\\\\n // wire w_RegWrite ;\\\\n // wire w_Branch ;\\\\n // wire w_Jump ;\\\\n // wire w_MemWrite ;\\\\n // wire w_MemtoReg ;\\\\n\\\\n\\\\n // assign LEDR[9:0] ={w_RegDst,w_ULASrc,w_ULAControl,w_Branch,w_MemWrite,w_MemtoReg,w_Jump}; \\\\n // assign w_wa3 = ( w_RegDst ) ? w_Inst[15:11] : w_Inst[20:16];\\\\n // assign w_SrcB = ( w_ULASrc ) ? w_Inst[7 : 0] : w_rd2;\\\\n // assign w_PCp1 = w_PC + 1;\\\\n\\\\t// assign LEDG[0] = ~KEY[0]; \\\\n\\\\t// assign LEDG[1] = ~KEY[1]; \\\\n\\\\t// assign w_d0x4 = w_PC; \\\\n\\\\t \\\\n // PC myPC(\\\\n\\\\t// \\\\t\\\\t\\\\t.rst\\\\t\\\\t(\\\\t\\\\t KEY[1]\\\\t\\\\t\\\\t\\\\t),\\\\n // .clk ( KEY[0] ),\\\\n // .PCin ( w_PCp1 ),\\\\n // .PCout ( w_PC )\\\\n // );\\\\n\\\\n // InstrMemory myInstrMemory(\\\\n // .address ( w_PC ),\\\\n // .RD ( w_Inst )\\\\n // );\\\\n // control_unit myULAControl(\\\\n // .OP ( w_Inst[31:26] ),\\\\n // .Funct ( w_Inst[ 5: 0] ),\\\\n // .RegWrite ( w_RegWrite ),\\\\n // .RegDst ( w_RegDst ),\\\\n // .ULASrc ( w_ULASrc ),\\\\n // .ULAControl ( w_ULAControl ),\\\\n // .Jump ( w_Jump ),\\\\n // .MemWrite ( w_MemWrite )\\\\n // );\\\\n // RegisterFile myRegisterFile (\\\\n\\\\t// \\\\t\\\\t\\\\t.rst\\\\t\\\\t(\\\\t\\\\t KEY[1]\\\\t\\\\t\\\\t\\\\t),\\\\n // .clk ( KEY[0] ),\\\\n // .ra1 ( w_Inst[25:21] ),//pq ra1 e o e ra2 recebem 4 bits ?\\\\n // .ra2 ( w_Inst[20:16] ),\\\\n // .we3 ( w_RegWrite ),\\\\n // .wa3 ( w_wa3 ),\\\\n // .wd3 ( w_ULAResultWd3 ),\\\\n // .rd1 ( w_rd1SrcA ),\\\\n // .rd2 ( w_rd2 ),\\\\n // .rg0 ( w_d0x0 ),\\\\n // .rg1 ( w_d0x1 ),\\\\n // .rg2 ( w_d0x2 ),\\\\n // .rg3 ( w_d0x3 ),\\\\n // .rg4 ( w_d1x0 ),\\\\n // .rg5 ( w_d1x1 ),\\\\n // .rg6 ( w_d1x2 ),\\\\n // .rg7 ( w_d1x3 )\\\\n\\\\n // );\\\\n // ula myULA (\\\\n\\\\n // .ScrB ( w_SrcB ),\\\\n // .ScrA ( w_rd1SrcA ),\\\\n // .ULAControl ( w_ULAControl ),\\\\n // .ULAResult ( w_ULAResultWd3 )\\\\n // );\\\\n\\\\n// --------------------------------------------------\\\\n\\\\n\\\\n//------------------Sprint6--------------------------\\\\n//------- CPU v0.2 ------------\\\\n\\\\n // wire [7 :0] w_PC ;\\\\n // wire [7 :0] w_PCp1 ;\\\\n // wire [31:0] w_Inst ;\\\\n // wire [4 :0] w_wa3 ;\\\\n // wire w_RegDst ;\\\\n // wire [7 :0] w_SrcB ;\\\\n // wire w_ULASrc ;\\\\n // wire [7 :0] w_rd1SrcA ;\\\\n // wire [2 :0] w_ULAControl ;\\\\n // wire [7 :0] w_ULAResultWd3 ;\\\\n // wire [7 :0] w_rd2 ;\\\\n // wire w_RegWrite ;\\\\n // wire w_Branch ;\\\\n // wire w_Jump ;\\\\n // wire w_MemWrite ;\\\\n // wire w_MemtoReg ;\\\\n // wire [7:0] w_RData ;\\\\n // wire [7:0] w_wd3 ;\\\\n // wire w_1Hz ;\\\\n\\\\n // assign LEDR[9:0] ={w_RegDst,w_ULASrc,w_ULAControl,w_Branch,w_MemWrite,w_MemtoReg,w_Jump}; \\\\n // assign w_wa3 = ( w_RegDst ) ? w_Inst[15:11] : w_Inst[20:16];\\\\n // assign w_SrcB = ( w_ULASrc ) ? w_Inst[7 : 0] : w_rd2;\\\\n // assign w_PCp1 = w_PC + 1;\\\\n\\\\t// assign LEDG[0] = w_1Hz; \\\\n\\\\t// assign LEDG[1] = ~KEY[1]; \\\\n\\\\t// assign w_d0x4 = w_PC; \\\\n\\\\t \\\\n // PC myPC(\\\\n\\\\t// \\\\t\\\\t\\\\t.rst\\\\t\\\\t(\\\\t\\\\t KEY[1]\\\\t\\\\t\\\\t\\\\t),\\\\n // .clk ( w_1Hz ),\\\\n // .PCin ( w_PCp1 ),\\\\n // .PCout ( w_PC )\\\\n // );\\\\n\\\\n // // InstrMemory myInstrMemory(\\\\n // // .address ( w_PC ),\\\\n // // .RD ( w_Inst )\\\\n // // );\\\\n\\\\n // control_unit myULAControl(\\\\n // .OP ( w_Inst[31:26] ),\\\\n // .Funct ( w_Inst[ 5: 0] ),\\\\n // .RegWrite ( w_RegWrite ),\\\\n // .RegDst ( w_RegDst ),\\\\n // .ULASrc ( w_ULASrc ),\\\\n // .ULAControl ( w_ULAControl ),\\\\n // .Jump ( w_Jump ),\\\\n // .Branch ( w_Branch ),\\\\n // .MemtoReg ( w_MemtoReg ),\\\\n // .MemWrite ( w_MemWrite )\\\\n // );\\\\n // RegisterFile myRegisterFile (\\\\n\\\\t// \\\\t\\\\t\\\\t.rst\\\\t\\\\t(\\\\t\\\\tKEY[1]\\\\t\\\\t\\\\t\\\\t),\\\\n // .clk ( w_1Hz ),\\\\n // .ra1 ( w_Inst[25:21] ),//pq ra1 e o e ra2 recebem 4 bits ?\\\\n // .ra2 ( w_Inst[20:16] ),\\\\n // .we3 ( w_RegWrite ),\\\\n // .wa3 ( w_wa3 ),\\\\n // .wd3 ( w_wd3 ),\\\\n // .rd1 ( w_rd1SrcA ),\\\\n // .rd2 ( w_rd2 ),\\\\n // .rg0 ( w_d0x0 ),\\\\n // .rg1 ( w_d0x1 ),\\\\n // .rg2 ( w_d0x2 ),\\\\n // .rg3 ( w_d0x3 ),\\\\n // .rg4 ( w_d1x0 ),\\\\n // .rg5 ( w_d1x1 ),\\\\n // .rg6 ( w_d1x2 ),\\\\n // .rg7 ( w_d1x3 )\\\\n\\\\n // );\\\\n // ula myULA (\\\\n\\\\n // .ScrB ( w_SrcB ),\\\\n // .ScrA ( w_rd1SrcA ),\\\\n // .ULAControl ( w_ULAControl ),\\\\n // .ULAResult ( w_ULAResultWd3 )\\\\n // );\\\\n\\\\n\\\\n // RomInstMem myRomInstMem(\\\\n // .address ( w_PC ),\\\\n // .clock ( CLOCK_50 ),\\\\n // .q ( w_Inst )\\\\n // );\\\\n\\\\n // RamDataMem myRamDataMem(\\\\n // .clock ( CLOCK_50 ),\\\\n // .address( w_ULAResultWd3 ),\\\\n // .data ( w_rd2 ),\\\\n // .q ( w_RData ),\\\\n // .wren ( w_MemWrite )\\\\n\\\\n // );\\\\n\\\\n // frequencydivider myfrequency1Hz(\\\\n // .clk ( CLOCK_27 ),\\\\n // .rst ( 1 ),\\\\n // .myclk( w_1Hz )\\\\n\\\\n // );\\\\n // assign w_wd3 = (w_MemtoReg) ? w_RData :w_ULAResultWd3;\\\\n// --------------------------------------------------\\\\n\\\\n//------------------Sprint7--------------------------\\\\n//------- CPU v0.3 ------------\\\\n\\\\n wire [7 :0] w_PC ;\\\\n wire [7 :0] w_PCp1 ;\\\\n wire [31:0] w_Inst ;\\\\n wire [4 :0] w_wa3 ;\\\\n wire w_RegDst ;\\\\n wire [7 :0] w_SrcB ;\\\\n wire w_ULASrc ;\\\\n wire [7 :0] w_rd1SrcA ;\\\\n wire [2 :0] w_ULAControl ;\\\\n wire [7 :0] w_ULAResultWd3 ;\\\\n wire [7 :0] w_rd2 ;\\\\n wire w_RegWrite ;\\\\n wire w_Branch ;\\\\n wire w_Jump ;\\\\n wire w_MemWrite ;\\\\n wire w_MemtoReg ;\\\\n wire [7:0] w_RData ;\\\\n wire [7:0] w_wd3 ;\\\\n wire w_1Hz ;\\\\n wire w_Z ;\\\\n wire [7:0] w_nPC ;\\\\n wire w_PCBr ;\\\\n wire [7:0] w_PCBranch ;\\\\n wire [7:0] w_m1 ;\\\\n wire w_PCSrc ; \\\\n \\\\n assign LEDR[9:0] ={w_RegDst,w_ULASrc,w_ULAControl,w_Branch,w_MemWrite,w_MemtoReg,w_Jump}; \\\\n\\\\n\\\\tassign LEDG[0] = w_1Hz; \\\\n\\\\tassign LEDG[1] = ~KEY[1]; \\\\n\\\\tassign w_d0x4 = w_PC; \\\\n\\\\n assign w_PCSrc = w_Z & w_Branch;\\\\n //Somadores\\\\n assign w_PCp1 = w_PC + 1;\\\\n assign w_PCBranch = w_Inst[7:0]+w_PCp1;\\\\n //Multiplexadores da CPU\\\\n assign w_wa3 = ( w_RegDst ) ? w_Inst[15:11] : w_Inst[20:16] ;\\\\n assign w_SrcB = ( w_ULASrc ) ? w_Inst[7 : 0] : w_rd2 ;\\\\n assign w_wd3 = (w_MemtoReg) ? w_RData : w_ULAResultWd3 ;\\\\n assign w_m1 = ( w_PCSrc ) ? w_PCBranch : w_PCp1 ; \\\\n assign w_nPC = ( w_Jump ) ? w_Inst[7:0] : w_m1 ; \\\\n\\\\n\\\\t \\\\n PC myPC(\\\\n\\\\t\\\\t\\\\t\\\\t.rst\\\\t\\\\t(\\\\t\\\\t KEY[1]\\\\t\\\\t\\\\t\\\\t),\\\\n .clk ( w_1Hz ),\\\\n .PCin ( w_nPC ),\\\\n .PCout ( w_PC )\\\\n );\\\\n\\\\n // InstrMemory myInstrMemory(\\\\n // .address ( w_PC ),\\\\n // .RD ( w_Inst )\\\\n // );\\\\n\\\\n control_unit myULAControl(\\\\n .OP ( w_Inst[31:26] ),\\\\n .Funct ( w_Inst[ 5: 0] ),\\\\n .RegWrite ( w_RegWrite ),\\\\n .RegDst ( w_RegDst ),\\\\n .ULASrc ( w_ULASrc ),\\\\n .ULAControl ( w_ULAControl ),\\\\n .Jump ( w_Jump ),\\\\n .Branch ( w_Branch ),\\\\n .MemtoReg ( w_MemtoReg ),\\\\n .MemWrite ( w_MemWrite )\\\\n );\\\\n RegisterFile myRegisterFile (\\\\n\\\\t\\\\t\\\\t\\\\t.rst\\\\t\\\\t(\\\\t\\\\tKEY[1]\\\\t\\\\t\\\\t\\\\t),\\\\n .clk ( w_1Hz ),\\\\n .ra1 ( w_Inst[25:21] ),//pq ra1 e o e ra2 recebem 4 bits ?\\\\n .ra2 ( w_Inst[20:16] ),\\\\n .we3 ( w_RegWrite ),\\\\n .wa3 ( w_wa3 ),\\\\n .wd3 ( w_wd3 ),\\\\n .rd1 ( w_rd1SrcA ),\\\\n .rd2 ( w_rd2 ),\\\\n .rg0 ( w_d0x0 ),\\\\n .rg1 ( w_d0x1 ),\\\\n .rg2 ( w_d0x2 ),\\\\n .rg3 ( w_d0x3 ),\\\\n .rg4 ( w_d1x0 ),\\\\n .rg5 ( w_d1x1 ),\\\\n .rg6 ( w_d1x2 ),\\\\n .rg7 ( w_d1x3 )\\\\n\\\\n );\\\\n ula myULA (\\\\n\\\\n .ScrB ( w_SrcB ),\\\\n .ScrA ( w_rd1SrcA ),\\\\n .ULAControl ( w_ULAControl ),\\\\n .ULAResult ( w_ULAResultWd3 ),\\\\n .Z ( w_Z )\\\\n );\\\\n\\\\n\\\\n RomInstMem myRomInstMem(\\\\n .address ( w_PC ),\\\\n .clock ( CLOCK_50 ),\\\\n .q ( w_Inst )\\\\n );\\\\n\\\\n RamDataMem myRamDataMem(\\\\n .clock ( CLOCK_50 ),\\\\n .address( w_ULAResultWd3 ),\\\\n .data ( w_rd2 ),\\\\n .q ( w_RData ),\\\\n .wren ( w_MemWrite )\\\\n\\\\n );\\\\n\\\\n frequencydivider #(.frequency(2))\\\\n myfrequency1Hz(\\\\n .clk ( CLOCK_27 ),\\\\n .rst ( 1 ),\\\\n .myclk( w_1Hz )\\\\n\\\\n );\\\\n\\\\n// --------------------------------------------------\\\\nendmodule"]
["module Flow_Control_Flow (\\\\n\\\\tinput Valid_i,Ready_i,CLK,RESET_n,\\\\n\\\\tinput [7:0]Data_i,\\\\n\\\\toutput [7:0]Data_o,\\\\n\\\\toutput wire Ready_o,Valid_o\\\\n);\\\\n\\\\twire [2:0] LD;\\\\n\\\\twire [1:0] addr;\\\\n\\\\twire [7:0] Q1,Q2,Q3,Q4;\\\\n\\\\twire Q5,Q6,Q7,Q8,Q9,Q10;\\\\n\\\\twire [7:0] Data_o_DFF,ram_out;\\\\n\\\\twire [1:0] SEL;\\\\n\\\\t\\\\n\\\\tassign SEL[0] = Ready_o;\\\\n\\\\tassign SEL[1] = Ready_i;\\\\n\\\\t\\\\n\\\\tcontrol control(.Valid_i(Valid_i),.LD(LD));\\\\n\\\\tcounter count(.CLK(CLK),.addr(addr),.Reset_n(RESET_n));\\\\n\\\\t//ram_1 #(8,2)ram(.clk(CLK),.wr_(Ready_i),.addr(addr),.ram_in(Q3),.ram_out(ram_out));\\\\n\\\\tram MEM(.WE(Ready_i), .ADDRESS(addr),.ram_in(Q4),.ram_out(ram_out));\\\\n\\\\tDFF#(8) D0(.D(Data_i),.CLK(CLK),.RESET_n(RESET_n),.LD(LD[0]),.Q(Q1));\\\\n\\\\tDFF#(8) D1(.D(Q1),.CLK(CLK),.RESET_n(RESET_n),.LD(LD[1]),.Q(Q2));\\\\n\\\\tDFF#(8) D2(.D(Q2),.CLK(CLK),.RESET_n(RESET_n),.LD(LD[2]),.Q(Q3));\\\\n\\\\tDFF#(8) D3(.D(Q3),.CLK(CLK),.RESET_n(RESET_n),.LD(LD[2]),.Q(Q4));\\\\n\\\\t\\\\n\\\\tDFF#(8) Delay0(.D(Ready_i),.CLK(CLK),.RESET_n(RESET_n),.LD(1'b1),.Q(Q5));\\\\n\\\\tDFF#(8) Delay1(.D(Q5),.CLK(CLK),.RESET_n(RESET_n),.LD(1'b1),.Q(Q6));\\\\n\\\\tDFF#(8) Delay2(.D(Q6),.CLK(CLK),.RESET_n(RESET_n),.LD(1'b1),.Q(Q7));\\\\n\\\\tDFF#(8) Delay3(.D(Q7),.CLK(CLK),.RESET_n(RESET_n),.LD(1'b1),.Q(Ready_o));\\\\n\\\\t\\\\n\\\\tDFF#(8) Delay4(.D(Valid_i),.CLK(CLK),.RESET_n(RESET_n),.LD(1'b1),.Q(Q8));\\\\n\\\\tDFF#(8) Delay5(.D(Q8),.CLK(CLK),.RESET_n(RESET_n),.LD(1'b1),.Q(Q9));\\\\n\\\\tDFF#(8) Delay6(.D(Q9),.CLK(CLK),.RESET_n(RESET_n),.LD(1'b1),.Q(Q10));\\\\n\\\\tDFF#(8) Delay7(.D(Q10),.CLK(CLK),.RESET_n(RESET_n),.LD(1'b1),.Q(Valid_o));\\\\n\\\\tmux8_4to1 mux8_4to1(.SEL(SEL),.D_IN0(),.D_IN1(),.D_IN2(ram_out),.D_IN3(Q4),.D_OUT(Data_o));\\\\n\\\\nendmodule"]
['module decode(HEX0, SW);\\\\n\\\\tinput[9:0]SW;\\\\n\\\\toutput[6:0]HEX0;\\\\n\\\\t\\\\n\\\\tseven_seg s1(\\\\n\\\\t\\\\t.S(SW[3:0]),\\\\n\\\\t\\\\t.HEX0(HEX0[6:0])\\\\n\\\\t\\\\t);\\\\nendmodule', 'module seven_seg(S, HEX0);\\\\n\\\\tinput [3:0]S;\\\\n \\\\toutput [6:0]HEX0;\\\\n\\\\t\\\\n\\\\t// 3 = A, 2 = B, 1 = C, 0 = D\\\\n\\\\t\\\\n\\\\tassign HEX[0] = ~s[3] & ~s[2] & ~s[1] & s[0] |\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t~s[3] & s[2] & ~s[1] & ~s[0] |\\\\n\\\\t\\\\t\\\\t\\\\t\\\\ts[3] & ~s[2] & s[1] & s[0] |\\\\n\\\\t\\\\t\\\\t\\\\t\\\\ts[3] & s[2] & ~s[1] & s[0] ;\\\\n\\\\n\\\\n\\\\tassign HEX[1] = ~s[3] & s[2] & ~s[1] & s[0] |\\\\n\\\\t\\\\t\\\\t\\\\t\\\\ts[2] & s[1] & ~s[0] |\\\\n\\\\t\\\\t\\\\t\\\\t\\\\ts[3] & s[2] & ~s[0] |\\\\n\\\\t\\\\t\\\\t\\\\t\\\\ts[3] & s[1] & s[0] ;\\\\n\\\\n\\\\tassign HEX[2] = ~s[3] & ~s[2] & s[1] & ~s[0] |\\\\n\\\\t\\\\t\\\\t\\\\t\\\\ts[3] & s[2] & ~s[0] |\\\\n\\\\t\\\\t\\\\t\\\\t\\\\ts[3] & s[1] & s[0] ;\\\\n\\\\n\\\\n\\\\tassign HEX[3] = ~s[2] & ~s[1] & s[0] |\\\\n\\\\t\\\\t\\\\t\\\\t\\\\ts[2] & s[1] & s[0] |\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t~s[3] & s[2] & ~s[1] & ~s[0] |\\\\n\\\\t\\\\t\\\\t\\\\t\\\\ts[3] & ~s[2] & s[1] & ~s[0] ;\\\\n\\\\n\\\\n\\\\tassign HEX[4] = ~s[2] & ~s[1] & s[0] |\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t~s[3] & s[1] & s[0] |\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t~s[3] & s[2] & ~s[1] ;\\\\n\\\\n\\\\n\\\\tassign HEX[5] = ~s[3] & ~s[2] & s[0] |\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t~s[3] & ~s[2] & s[1] |\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t~s[3] & s[1] & s[0] |\\\\n\\\\t\\\\t\\\\t\\\\t\\\\ts[3] & s[2] & ~s[1] & s[0] ;\\\\n\\\\n\\\\n\\\\tassign HEX[6] = ~s[3] & ~s[2] & ~s[1] |\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t~s[3] & s[2] & s[1] & s[0] |\\\\n\\\\t\\\\t\\\\t\\\\t\\\\ts[3] & s[2] & ~s[1] & ~s[0] ;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\nendmodule']
['module lab4_task5(SW,LEDR,LEDG,KEY,HEX7, HEX6, HEX5, HEX4, HEX3, HEX2, HEX1, HEX0);\\\\n\\\\tinput [17:0] SW;\\\\n input [3:0] KEY;\\\\n output [0:6] HEX7, HEX6, HEX5, HEX4, HEX3, HEX2, HEX1, HEX0;\\\\n\\\\toutput [17:0] LEDR;\\\\n\\\\toutput [7:0] LEDG;\\\\n\\\\twire [15:0] W_LED_SEG;\\\\n\\\\t\\\\n\\\\twire [7:0] W_READ_ADDRESS;\\\\n\\\\t\\\\n\\\\thex_ssd (W_LED_SEG[3:0], HEX0);\\\\n\\\\thex_ssd (W_LED_SEG[7:4], HEX1);\\\\n\\\\thex_ssd (W_LED_SEG[11:8],HEX2);\\\\n\\\\thex_ssd (W_LED_SEG[15:12],HEX3);\\\\t\\\\n\\\\t\\\\n\\\\thex_ssd (W_READ_ADDRESS[3:0],HEX6);\\\\n\\\\thex_ssd (W_READ_ADDRESS[4:4],HEX7);\\\\n\\\\t\\\\n\\\\tdata_path_instruction_mem(.reset(SW[17]),.clk(KEY[0]),.read_address(W_READ_ADDRESS),.instruction(W_LED_SEG));\\\\nendmodule', "module hex_ssd (BIN, SSD);\\\\n input [3:0] BIN;\\\\n output reg [0:6] SSD;\\\\n\\\\n always begin\\\\n case(BIN)\\\\n 0:SSD=7'b0000001;\\\\n 1:SSD=7'b1001111;\\\\n 2:SSD=7'b0010010;\\\\n 3:SSD=7'b0000110;\\\\n 4:SSD=7'b1001100;\\\\n 5:SSD=7'b0100100;\\\\n 6:SSD=7'b0100000;\\\\n 7:SSD=7'b0001111;\\\\n 8:SSD=7'b0000000;\\\\n 9:SSD=7'b0001100;\\\\n 10:SSD=7'b0001000;\\\\n 11:SSD=7'b1100000;\\\\n 12:SSD=7'b0110001;\\\\n 13:SSD=7'b1000010;\\\\n 14:SSD=7'b0110000;\\\\n 15:SSD=7'b0111000;\\\\n endcase\\\\n end\\\\nendmodule", "module data_path_instruction_mem(reset,clk,read_address,instruction);\\\\ninput reset,clk;\\\\noutput [7:0] read_address;\\\\noutput [15:0] instruction;\\\\nwire [7:0] W_PC_add_1;\\\\n\\\\nProgram_Counter C1(.clk(clk), .reset(reset), .PC_in(W_PC_add_1), .PC_out(read_address));\\\\nAdder8Bit C2(.input1(8'b1), .input2(read_address), .out(W_PC_add_1));\\\\nInstruction_Memory C3(.reset(reset),.read_address(read_address), .instruction(instruction));\\\\nendmodule", "module Instruction_Memory (reset,read_address, instruction);\\\\n\\\\tinput reset;\\\\n\\\\tinput [7:0] read_address;\\\\n\\\\toutput [15:0] instruction;\\\\n\\\\treg [15:0] Imemory [255:0];\\\\n\\\\tinteger k;\\\\n\\\\t// I-MEM in this case is addressed by word, not by byte\\\\n\\\\tassign instruction = Imemory[read_address];\\\\n\\\\n\\\\talways @(posedge reset)\\\\n\\\\tbegin\\\\n\\\\tfor (k=0; k<39; k=k+1) \\\\nbegin \\\\n// here Out changes k=0 to k=16\\\\n\\\\t\\\\t\\\\t Imemory[k] = 16'b0;\\\\n\\\\t\\\\t\\\\tend\\\\nImemory[0] = 32'b00100000000010000000000000100000; \\\\n//addi $t0, $zero, 32\\\\nImemory[1] = 32'b00100000000010010000000000110111; \\\\n//addi $t1, $zero, 55\\\\nImemory[2] = 32'b00000001000010011000000000100100; \\\\n//and $s0, $t0, $t1\\\\nImemory[3] = 32'b00000001000010011000000000100101; \\\\n//or $s0, $t0, $t1\\\\nImemory[4] = 32'b10101100000100000000000000000100; \\\\n//sw $s0, 4($zero)\\\\nImemory[5] = 32'b10101100000010000000000000001000; \\\\n//sw $t0, 8($zero)\\\\nImemory[6] = 32'b00000001000010011000100000100000; \\\\n//add $s1, $t0, $t1\\\\nImemory[7] = 32'b00000001000010011001000000100010; \\\\n//sub $s2, $t0, $t1\\\\nImemory[8] = 32'b00010010001100100000000000001001; \\\\n//beq $s1, $s2, error0\\\\nImemory[9] = 32'b10001100000100010000000000000100; \\\\n//lw $s1, 4($zero)\\\\nImemory[10]= 32'b00110010001100100000000001001000; \\\\n//andi $s2, $s1, 48\\\\nImemory[11] =32'b00010010001100100000000000001001; \\\\n//beq $s1, $s2, error1\\\\nImemory[12] =32'b10001100000100110000000000001000; \\\\n//lw $s3, 8($zero)\\\\nImemory[13] =32'b00010010000100110000000000001010; \\\\n//beq $s0, $s3, error2\\\\nImemory[14] =32'b00000010010100011010000000101010; \\\\n//slt $s4, $s2, $s1 (Last)\\\\nImemory[15] =32'b00010010100000000000000000001111; \\\\n//beq $s4, $0, EXIT\\\\nImemory[16] =32'b00000010001000001001000000100000; \\\\n//add $s2, $s1, $0\\\\nImemory[17] =32'b00001000000000000000000000001110; \\\\n//j Last\\\\nImemory[18] =32'b00100000000010000000000000000000; \\\\n//addi $t0, $0, 0(error0)\\\\nImemory[19] =32'b00100000000010010000000000000000; \\\\n//addi $t1, $0, 0\\\\nImemory[20] =32'b00001000000000000000000000011111; \\\\n//j EXIT\\\\nImemory[21] =32'b00100000000010000000000000000001; \\\\n//addi $t0, $0, 1(error1)\\\\nImemory[22] =32'b00100000000010010000000000000001; \\\\n//addi $t1, $0, 1\\\\nImemory[23] =32'b00001000000000000000000000011111; \\\\n//j EXIT\\\\nImemory[24] =32'b00100000000010000000000000000010; \\\\n//addi $t0, $0, 2(error2)\\\\nImemory[25] =32'b00100000000010010000000000000010; \\\\n//addi $t1, $0, 2\\\\nImemory[26] =32'b00001000000000000000000000011111; \\\\n//j EXIT\\\\nImemory[27] =32'b00100000000010000000000000000011; \\\\n//addi $t0, $0, 3(error3)\\\\nImemory[28] =32'b00100000000010010000000000000011; \\\\n//addi $t1, $0, 3\\\\nImemory[29] =32'b00001000000000000000000000011111; \\\\n//j EXIT \\\\nend\\\\nendmodule", "module Program_Counter (clk, reset, PC_in, PC_out);\\\\n\\\\tinput clk, reset;\\\\n\\\\tinput [7:0] PC_in;\\\\n\\\\toutput [7:0] PC_out;\\\\n\\\\treg [7:0] PC_out;\\\\n\\\\talways @ (posedge clk or posedge reset)\\\\n\\\\tbegin\\\\n if(reset==1'b1)\\\\n\\\\t\\\\t\\\\tPC_out<=8'b0;\\\\n\\\\t\\\\telse\\\\n\\\\t\\\\t\\\\tPC_out<=PC_in;\\\\n\\\\tend\\\\nendmodule", 'module Adder8Bit(input1, input2, out);\\\\n\\\\n input [7:0] input1, input2;\\\\n output [7:0] out;\\\\n reg [7:0]out;\\\\n always@( input1 or input2)\\\\n begin\\\\n \\\\tout <= input1 + input2;\\\\n end\\\\nendmodule']
['module stack(input wire clk, reset, push, pop, input wire [15:0] value_in, output wire [15:0] value_out);\\\\nmodule tb;\\\\n reg clk, reset, push, pop;\\\\n // reg [2:0] rd_addr_a, rd_addr_b, wr_addr; \\\\n reg [15:0] value_in;\\\\n wire [15:0] value_out;\\\\n wire full, empty;\\\\n reg [17:0] test_vecs [0:(`TESTVECS-1)];\\\\n\\\\n integer i;\\\\n initial begin $dumpfile(\\\\"tb_stack4.vcd\\\\"); $dumpvars(0,tb); end\\\\n initial begin reset = 1\\'b1; #12.5 reset = 1\\'b0; end\\\\n initial clk = 1\\'b0; always #5 clk = ~clk;\\\\n initial begin\\\\n test_vecs[0][17] = 1\\'b1; test_vecs[0][16] = 1\\'b0; test_vecs[0][15:0] = 15\\'h13;\\\\n test_vecs[1][17] = 1\\'b1; test_vecs[1][16] = 1\\'b0; test_vecs[1][15:0] = 15\\'h13;\\\\n test_vecs[2][17] = 1\\'b1; test_vecs[2][16] = 1\\'b0; test_vecs[2][15:0] = 15\\'h13;\\\\n test_vecs[3][17] = 1\\'b1; test_vecs[3][16] = 1\\'b0; test_vecs[3][15:0] = 15\\'h13;\\\\n test_vecs[4][17] = 1\\'b1; test_vecs[4][16] = 1\\'b0; test_vecs[4][15:0] = 15\\'h13;\\\\n test_vecs[5][17] = 1\\'b1; test_vecs[5][16] = 1\\'b0; test_vecs[5][15:0] = 15\\'h13;\\\\n test_vecs[6][17] = 1\\'b1; test_vecs[6][16] = 1\\'b0; test_vecs[6][15:0] = 15\\'h13;\\\\n test_vecs[7][17] = 1\\'b1; test_vecs[7][16] = 1\\'b0; test_vecs[7][15:0] = 15\\'h13;\\\\n test_vecs[8][17] = 1\\'b1; test_vecs[8][16] = 1\\'b0; test_vecs[8][15:0] = 15\\'h13;\\\\n test_vecs[9][17] = 1\\'b1; test_vecs[9][16] = 1\\'b0; test_vecs[9][15:0] = 15\\'h13;\\\\n test_vecs[10][17] = 1\\'b0; test_vecs[10][16] = 1\\'b1; test_vecs[10][15:0] = 15\\'hxx;\\\\n test_vecs[11][17] = 1\\'b0; test_vecs[11][16] = 1\\'b1; test_vecs[11][15:0] = 15\\'hxx;\\\\n test_vecs[12][17] = 1\\'b0; test_vecs[12][16] = 1\\'b1; test_vecs[12][15:0] = 15\\'hxx;\\\\n test_vecs[13][17] = 1\\'b0; test_vecs[13][16] = 1\\'b1; test_vecs[13][15:0] = 15\\'hxx;\\\\n test_vecs[14][17] = 1\\'b0; test_vecs[14][16] = 1\\'b0; test_vecs[14][15:0] = 15\\'h14;\\\\n end\\\\n initial {push, pop, value_in} = 0;\\\\n stack stk_0(clk, reset, push, pop, value_in, value_out, full, empty);\\\\ninitial begin\\\\n #4 for(i=0;i<`TESTVECS;i=i+1)\\\\n begin #10 {push, pop, value_in}=test_vecs[i]; end\\\\n #100 $finish;\\\\nend\\\\nendmodule']
["module toplevel(\\\\n\\\\tinput clk, //100 MHz\\\\n\\\\tinput rst,\\\\n\\\\tinout [3:0] btn,\\\\n\\\\tinput [7:0] sw,\\\\n\\\\toutput[7:0] led,\\\\n\\\\toutput[3:0] an,\\\\n\\\\toutput[7:0] seg\\\\n);\\\\n\\\\n\\\\t/* aritmetikai egysegek */\\\\n\\\\twire[4:0] res_add;\\\\n\\\\twire sign_add=0;\\\\n\\\\tadd add_i(\\\\n\\\\t\\\\t.in1(sw[7:4]),\\\\n\\\\t\\\\t.in2(sw[3:0]),\\\\n\\\\t\\\\t.out(res_add)\\\\n\\\\t);\\\\n\\\\n\\\\twire[3:0] res_sub;\\\\n\\\\twire sign_sub=(sw[7:4]<sw[3:0]);\\\\n\\\\tsub sub_i(\\\\n\\\\t\\\\t.in1(sw[7:4]),\\\\n\\\\t\\\\t.in2(sw[3:0]),\\\\n\\\\t\\\\t.out(res_sub)\\\\n\\\\t);\\\\n\\\\n\\\\twire[7:0] res_mul;\\\\n\\\\twire sign_mul=0;\\\\n\\\\tmul mul_i(\\\\n\\\\t\\\\t.clk(clk),\\\\n\\\\t\\\\t.rst(rst),\\\\n\\\\t\\\\t.in1(sw[7:4]),\\\\n\\\\t\\\\t.in2(sw[3:0]),\\\\n\\\\t\\\\t.out(res_mul)\\\\n\\\\t);\\\\n\\\\n\\\\twire[3:0] res_div;\\\\n\\\\twire sign_div=0;\\\\n\\\\tdiv div_i(\\\\n\\\\t\\\\t.clk(clk),\\\\n\\\\t\\\\t.rst(rst),\\\\n\\\\t\\\\t.in1(sw[7:4]),\\\\n\\\\t\\\\t.in2(sw[3:0]),\\\\n\\\\t\\\\t.out(res_div)\\\\n\\\\t);\\\\n\\\\n\\\\n\\\\t/* kimenetvalaszto multiplexer */\\\\n\\\\treg[1:0] select;\\\\n\\\\talways@(posedge clk)\\\\n\\\\t\\\\tif(rst)\\\\n\\\\t\\\\t\\\\tselect<=0;\\\\n\\\\t\\\\telse\\\\n\\\\t\\\\t\\\\tcase(btn)\\\\n\\\\t\\\\t\\\\t\\\\t4'b0001: select<=0;\\\\n\\\\t\\\\t\\\\t\\\\t4'b0010: select<=1;\\\\n\\\\t\\\\t\\\\t\\\\t4'b0100: select<=2;\\\\n\\\\t\\\\t\\\\t\\\\t4'b1000: select<=3;\\\\n\\\\t\\\\t\\\\tendcase\\\\n\\\\n\\\\treg[7:0] res;\\\\n\\\\treg sign;\\\\n\\\\talways@(*)\\\\n\\\\t\\\\tcase(select)\\\\n\\\\t\\\\t\\\\t0: begin res<={3'd0,res_add}; sign<=sign_add; end\\\\n\\\\t\\\\t\\\\t1: begin res<={4'd0,res_sub}; sign<=sign_sub; end\\\\n\\\\t\\\\t\\\\t2: begin res<=res_mul; sign<=sign_mul; end\\\\n\\\\t\\\\t\\\\t3: begin res<={4'd0,res_div}; sign<=sign_div; end\\\\n\\\\t\\\\tendcase\\\\n\\\\n\\\\n\\\\t/* kijelzes */\\\\n\\\\twire[3:0] d2, d1, d0;\\\\n\\\\n\\\\tbin2bcd bin2bcd_i(\\\\n\\\\t\\\\t.clk(clk),\\\\n\\\\t\\\\t.rst(rst),\\\\n\\\\t\\\\t.in(res),\\\\n\\\\t\\\\t.d2(d2),\\\\n\\\\t\\\\t.d1(d1),\\\\n\\\\t\\\\t.d0(d0)\\\\n\\\\t);\\\\n\\\\n\\\\tbcd_to_7seg bcd_to_7seg_i(\\\\n\\\\t\\\\t.clk(clk),\\\\n\\\\t\\\\t.rst(rst),\\\\n\\\\t\\\\t.digit0(d0),\\\\n\\\\t\\\\t.digit1(d1),\\\\n\\\\t\\\\t.digit2(d2),\\\\n\\\\t\\\\t.digit3(sign?4'hA:4'hF),\\\\n\\\\t\\\\t.an(an),\\\\n\\\\t\\\\t.seg(seg)\\\\n\\\\t);\\\\n\\\\n\\\\tassign led=sw;\\\\n\\\\nendmodule"]
['module enc_module(output [7:0]out, input wire[7:0] x, input wire[7:0]y);\\\\n\\\\treg inv;\\\\n\\\\treg test;\\\\n\\\\twire [6:0]inT2, inT4stst;\\\\n\\\\twire [2:0]countT2,countT4stst;\\\\n\\\\t//reg [4:0]ctT2, ctT4stst;\\\\n\\\\n\\\\t//Module instantiation\\\\n\\\\t// Here the flit size is 32 bits, and the 0th bit indicates the inverted condition, and hence is reserved\\\\n\\\\t// for that. Care must be taken that while encoding(inverting), this 0th bit should be excluded.\\\\n\\\\tT2 t2[6:0](.out(inT2), .a(x[6:0]), .b(x[7:1]), .c(y[6:0]), .d(y[7:1]));\\\\n\\\\tT4stst t4stst[6:0](.out(inT4stst),.a(x[6:0]), .b(x[7:1]), .c(y[6:0]), .d(y[7:1]));\\\\n\\\\tones oneT2(.count(countT2) , .in(inT2));\\\\n\\\\tones oneT4stst(.count(countT4stst) , .in(inT4stst));\\\\n\\\\texor xr[6:0](.out(out[6:0]), .a(x[6:0]), .b({7{inv}}));\\\\n\\\\tassign out[7] = inv;\\\\n\\\\talways@(*) begin\\\\n\\\\tif (countT2> countT4stst) begin\\\\n\\\\t\\\\tinv = 1;\\\\n\\\\t\\\\t//test= 1;\\\\n\\\\t\\\\t\\\\n\\\\tend else \\\\n\\\\t\\\\tinv = 0;\\\\n\\\\tend\\\\nendmodule', 'module encoder(output [31:0]out, input wire[31:0] x, input wire[31:0]y);\\\\n\\\\tenc_module enc1(.out(out[7:0]),.x(x[7:0]), .y(y[7:0]));\\\\n\\\\tenc_module enc2(.out(out[15:8]), .x(x[15:8]), .y(y[15:8])); \\\\n\\\\tenc_module enc3(.out(out[23:16]),.x(x[23:16]), .y(y[23:16]));\\\\n\\\\tenc_module enc4(.out(out[31:24]), .x(x[31:24]), .y(y[31:24])); \\\\nendmodule']
["module shr_op_tb; \\\\t\\\\n\\\\treg\\\\tPCout, ZHighout, ZLowout, MDRout, R2Out, R4Out;// add any other signals to see in your simulation\\\\n\\\\treg\\\\tMARin, PCin, MDRin, IRin, Yin;\\\\n\\\\treg \\\\tIncPC, Read;\\\\n\\\\treg \\\\t[4:0] SHR; \\\\n\\\\treg \\\\tR5in, R2in, R4in;\\\\n\\\\treg\\\\tHIin, LOin, ZHighIn, Cin, ZLowIn;\\\\n\\\\treg\\\\tClock, Clear;\\\\t\\\\t// US clear\\\\n\\\\treg\\\\t[31:0] Mdatain;\\\\n\\\\nparameter\\\\tDefault = 4'b0000, Reg_load1a= 4'b0001, Reg_load1b= 4'b0010,\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tReg_load2a= 4'b0011, Reg_load2b = 4'b0100, Reg_load3a = 4'b0101,\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tReg_load3b = 4'b0110, T0= 4'b0111, T1= 4'b1000,T2= 4'b1001, T3= 4'b1010, T4= 4'b1011, T5= 4'b1100;\\\\nreg\\\\t[3:0] Present_state= Default;\\\\n\\\\ninitial Clear = 0;\\\\n\\\\ncpu_phase1 DUT(PCout, ZHighout, Zlowout, MDRout, R2out, R4out, MARin, Zin, PCin, MDRin, IRin, Yin, IncPC, Read, SHR, R5in, R2in, R4in, Clock, Clear, Mdatain);\\\\n\\\\t //the input (in.port) and output (out.port) connects the CPU to the outside world\\\\n //the input (in.port) and output (out.port) connects the CPU to the outside world\\\\n\\\\ninitial \\\\n\\\\tbegin\\\\n\\\\t\\\\tClock = 0;\\\\n\\\\t\\\\tforever #10 Clock = ~ Clock;\\\\nend\\\\n\\\\nalways @(posedge Clock)//finite state machine; if clock rising-edge\\\\nbegin\\\\n\\\\tcase (Present_state)\\\\n\\\\t\\\\tDefault\\\\t\\\\t\\\\t:\\\\t#40 Present_state = Reg_load1a;\\\\n\\\\t\\\\tReg_load1a\\\\t\\\\t:\\\\t#40 Present_state = Reg_load1b;\\\\n\\\\t\\\\tReg_load1b\\\\t\\\\t:\\\\t#40 Present_state = Reg_load2a;\\\\n\\\\t\\\\tReg_load2a\\\\t\\\\t:\\\\t#40 Present_state = Reg_load2b;\\\\n\\\\t\\\\tReg_load2b\\\\t\\\\t:\\\\t#40 Present_state = Reg_load3a;\\\\n\\\\t\\\\tReg_load3a\\\\t\\\\t:\\\\t#40 Present_state = Reg_load3b;\\\\n\\\\t\\\\tReg_load3b\\\\t\\\\t:\\\\t#40 Present_state = T0;\\\\n\\\\t\\\\tT0\\\\t\\\\t\\\\t\\\\t\\\\t:\\\\t#40 Present_state = T1;\\\\n\\\\t\\\\tT1\\\\t\\\\t\\\\t\\\\t\\\\t:\\\\t#40 Present_state = T2;\\\\n\\\\t\\\\tT2\\\\t\\\\t\\\\t\\\\t\\\\t:\\\\t#40 Present_state = T3;\\\\n\\\\t\\\\tT3\\\\t\\\\t\\\\t\\\\t\\\\t:\\\\t#40 Present_state = T4;\\\\n\\\\t\\\\tT4\\\\t\\\\t\\\\t\\\\t\\\\t:\\\\t#40 Present_state = T5;\\\\n\\\\t\\\\tendcase\\\\n\\\\tend\\\\n\\\\nalways @(Present_state)// do the required job ineach state\\\\nbegin\\\\n\\\\tcase (Present_state) //assert the required signals in each clock cycle\\\\n\\\\t\\\\tDefault: begin\\\\n\\\\t\\\\t\\\\t\\\\tPCout <= 0; ZLowout <= 0; ZHighout <= 0; MDRout<= 0; //initialize the signals\\\\n\\\\t\\\\t\\\\t\\\\tR2Out <= 0; R4Out <= 0; MARin <= 0; ZLowIn <= 0; \\\\n\\\\t\\\\t\\\\t\\\\tPCin <=0; MDRin <= 0; IRin <= 0; Yin <= 0; \\\\n\\\\t\\\\t\\\\t\\\\tIncPC <= 0; Read <= 0; SHR <= 0;\\\\n\\\\t\\\\t\\\\t\\\\tR5in <= 0; R2in <= 0; R4in <= 0; Mdatain <= 32'h00000000;\\\\n\\\\t\\\\tend\\\\n\\\\t\\\\tReg_load1a: begin \\\\n\\\\t\\\\t\\\\t\\\\tMdatain<= 32'h00000004;\\\\n\\\\t\\\\t\\\\t\\\\tRead = 0; MDRin = 0;\\\\t\\\\n\\\\t\\\\t\\\\t\\\\t#10 Read <= 1; MDRin <= 1; \\\\n\\\\t\\\\t\\\\t\\\\t#15 Read <= 0; MDRin <= 0;\\\\n\\\\t\\\\tend\\\\n\\\\t\\\\tReg_load1b: begin\\\\n\\\\t\\\\t\\\\t\\\\t#10 MDRout<= 1; R2in <= 1; \\\\n\\\\t\\\\t\\\\t\\\\t#15 MDRout<= 0; R2in <= 0; \\\\n\\\\t\\\\tend\\\\n\\\\t\\\\tReg_load2a: begin \\\\n\\\\t\\\\t\\\\t\\\\tMdatain <= 32'h00000002;\\\\n\\\\t\\\\t\\\\t\\\\t#10 Read <= 1; MDRin <= 1; \\\\n\\\\t\\\\t\\\\t\\\\t#15 Read <= 0; MDRin <= 0;\\\\n\\\\t\\\\tend\\\\n\\\\t\\\\tReg_load2b: begin\\\\n\\\\t\\\\t\\\\t\\\\t#10 MDRout<= 1; R4in <= 1; \\\\n\\\\t\\\\t\\\\t\\\\t#15 MDRout<= 0; R4in <= 0;\\\\n\\\\t\\\\tend\\\\n\\\\t\\\\tReg_load3a: begin \\\\n\\\\t\\\\t\\\\t\\\\tMdatain <= 32'h00000027;\\\\n\\\\t\\\\t\\\\t\\\\t#10 Read <= 1; MDRin <= 1; \\\\n\\\\t\\\\t\\\\t\\\\t#15 Read <= 0; MDRin <= 0;\\\\n\\\\t\\\\tend\\\\n\\\\t\\\\tReg_load3b: begin\\\\n\\\\t\\\\t\\\\t\\\\t#10 MDRout<= 1; R5in <= 1; \\\\n\\\\t\\\\t\\\\t\\\\t#15 MDRout<= 0; R5in <= 0;\\\\n\\\\t\\\\tend\\\\n\\\\t\\\\n\\\\t\\\\tT0: begin//see if you need to de-assert these signals\\\\n\\\\t\\\\t\\\\t\\\\tMdatain <= 32'h00000007; // dummy pc\\\\n\\\\t\\\\t\\\\t\\\\tPCin <= 1; MDRout <=1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\n\\\\t\\\\t\\\\t\\\\t#10 PCout<= 1; MARin <= 1; IncPC <= 1; \\\\n\\\\t\\\\t\\\\t\\\\t#10 PCin <= 0; MDRout <=0; PCout<= 0; MARin <= 0; IncPC <= 0;\\\\n\\\\t\\\\tend\\\\n\\\\t\\\\tT1: begin\\\\n\\\\t\\\\t\\\\t\\\\tMdatain <= 32'h4A920000; \\\\n\\\\t\\\\t\\\\t\\\\tRead <= 1; MDRin <= 1;\\\\n\\\\t\\\\t\\\\t\\\\t#10 Read <= 0; MDRin <= 0;\\\\n\\\\t\\\\t\\\\t\\\\t//ZLowout<= 1; PCin <= 1; \\\\n\\\\t\\\\t\\\\t\\\\t\\\\n\\\\t\\\\tend\\\\n\\\\t\\\\tT2: begin\\\\n\\\\t\\\\t\\\\t\\\\tMDRout<= 1; IRin <= 1; \\\\n\\\\t\\\\t\\\\t\\\\t#10 MDRout<= 0; IRin <= 0; \\\\n\\\\t\\\\tend\\\\n\\\\t\\\\tT3: begin\\\\n\\\\t\\\\t\\\\t\\\\t#10 R2Out<= 1; Yin <= 1; \\\\n\\\\t\\\\t\\\\t\\\\t#15 R2Out<= 0; Yin <= 0;\\\\n\\\\t\\\\tend\\\\n\\\\t\\\\tT4: begin\\\\n\\\\t\\\\t\\\\t\\\\tR4Out<= 1; SHR <= 5'b00101; ZLowIn <= 1; \\\\n\\\\t\\\\t\\\\t\\\\t#25 R4Out<= 0; ZLowIn <= 0; \\\\n\\\\t\\\\tend\\\\n\\\\t\\\\tT5: begin\\\\n\\\\t\\\\t\\\\t\\\\tZLowout<= 1; R5in <= 1; \\\\n\\\\t\\\\t\\\\t\\\\t#25 ZLowout<= 0; R5in <= 0;\\\\n\\\\t\\\\tend\\\\n\\\\tendcase\\\\nend\\\\nendmodule"]
["module ppc(y,x,rst,clk,a,b,c,d);\\\\n\\\\ninput [31:0][7:0]x;\\\\ninput [31:0] a,b;\\\\n\\\\nwire [31:0][7:0]reg1,reg2,reg3,reg4,reg5;\\\\nwire[31:0] wire6,wire7,wire8,wire9,wire10,wire11,wire12,wire13,wire14,wire15;\\\\n\\\\noutput [31:0][7:0] y ;\\\\noutput [31:0] c,d;\\\\nwire [31:0][7:0] wire1,wire2,wire3,wire4,wire5 ;\\\\n\\\\ninput rst,clk;\\\\n\\\\n\\\\n// Second level of pipeline.\\\\ndff_lvl c1(x,rst,clk,reg1,wire6,wire7,a,b); //pipeline-2\\\\n\\\\n//generate level 1 of the RD Matrix\\\\nlvl m1(wire1,reg1,3'd0);\\\\n\\\\ndff_lvl c2(wire1,rst,clk,reg2,wire8,wire9,wire6,wire7); //pipeline-3\\\\nlvl m2(wire2,reg2,3'd1);\\\\n\\\\ndff_lvl c3(wire2,rst,clk,reg3,wire10,wire11,wire8,wire9); //pipeline-4\\\\nlvl m3(wire3,reg3,3'd2);\\\\n\\\\ndff_lvl c4(wire3,rst,clk,reg4,wire12,wire13,wire10,wire11); //pipeline-5\\\\nlvl m4(wire4,reg4,3'd3);\\\\n\\\\ndff_lvl c5(wire4,rst,clk,reg5,wire14,wire15,wire12,wire13); //pipeline-6\\\\nlvl m5(wire5,reg5,3'd4);\\\\n\\\\ndff_lvl c6(wire5,rst,clk,y,c,d,wire14,wire15); //pipeline-7\\\\n\\\\nendmodule"]
['module seg7_run(HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7,clk,select_seg,\\\\ncheck_pass,enableir,input_string,reset,CLOCK_50,IRDA_RXD,checkremote);\\\\ninput checkremote;\\\\ninput CLOCK_50;\\\\ninput reset;\\\\ninput IRDA_RXD;\\\\ninput clk;\\\\n//input [31:0] hex_data;\\\\ninput enableir;\\\\ninput [2:0] select_seg;\\\\noutput reg [1:0] check_pass;\\\\noutput reg [4*8-1:0] input_string; \\\\noutput [6:0] HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7;\\\\nparameter zero = 7\\'b1000000;\\\\ninteger t=0;\\\\n\\\\tparameter one = 7\\'b1111001;\\\\n\\\\tparameter two = 7\\'b0100100;\\\\n\\\\tparameter three = 7\\'b0110000;\\\\n\\\\tparameter four = 7\\'b0011001;\\\\n\\\\tparameter five = 7\\'b0010010;\\\\n\\\\tparameter six = 7\\'b0000010;\\\\n\\\\tparameter seven = 7\\'b1111000;\\\\n\\\\tparameter eight = 7\\'b0000000;\\\\n\\\\tparameter nine = 7\\'b0011000;\\\\n\\\\tparameter pl = 7\\'b0001100;\\\\n\\\\tparameter al = 7\\'b0001000;\\\\n\\\\tparameter sl = 7\\'b0010010;\\\\n\\\\tparameter blank = 7\\'b1111111;\\\\n\\\\treg [6:0] hex;\\\\n\\\\treg [6:0] hex1;\\\\n\\\\treg [6:0] hex2;\\\\n\\\\treg [6:0] hex3;\\\\n\\\\treg [6:0] hex4;\\\\n\\\\treg [6:0] hex5;\\\\n\\\\treg [6:0] hex6;\\\\n\\\\treg [6:0] hex7;\\\\n\\\\treg [6:0] hex8;\\\\n\\\\treg [6:0] hex9;\\\\n\\\\treg [6:0] hex10;\\\\n\\\\treg [6:0] hexarray [4:0];\\\\n\\\\treg [6:0] hexarrayt [4:0];\\\\n\\\\treg [6:0] hexarrayck [4:0];\\\\n\\\\treg [6:0] hextemp = blank;\\\\n\\\\treg [6:0] hex_out;\\\\n\\\\tinteger ii;\\\\n\\\\tinteger i=0;\\\\n\\\\talways @(posedge clk)\\\\n\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\tcase(i)\\\\n\\\\t\\\\t\\\\t\\\\t0: begin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\thex <= eight;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\ti <= i + 1;\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t\\\\t1: begin \\\\n\\\\t\\\\t\\\\t\\\\t\\\\thex <= blank;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\ti <= 0;\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\tendcase\\\\n\\\\t\\\\tend\\\\n\\\\tinteger iii=0;\\\\n\\\\ninteger dem =0;\\\\n\\\\nalways @( posedge clk)begin\\\\nif ((select_seg == 3\\'b010)) begin\\\\n\\\\tif (dem < 3) begin\\\\n\\\\t\\\\t\\\\tcase(iii)\\\\n\\\\t\\\\t\\\\t\\\\t0: begin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\n\\\\t\\\\t\\\\t\\\\t\\\\thex1 = blank;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tiii = iii + 1;\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t\\\\t1: begin \\\\n\\\\t\\\\t\\\\t\\\\t\\\\thex1 = eight;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tiii = iii - 1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tdem = dem + 1;\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\tendcase\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\telse begin hex1 = blank; end\\\\nend\\\\n\\\\telse begin dem =0; hex1 = blank;\\\\nend \\\\nend\\\\n\\\\n\\\\n\\\\n\\\\n\\\\n\\\\n\\\\n\\\\t//\\\\n\\\\t/*genvar demmm;\\\\n\\\\tgenerate \\\\n\\\\tfor (demmm =0; demmm <2; demmm =demmm+1)\\\\n\\\\tbegin\\\\n\\\\tinteger dem = 0;\\\\n\\\\talways @( posedge clk)begin\\\\n\\\\t\\\\t\\\\tcase(iii)\\\\n\\\\t\\\\t\\\\t\\\\t0: begin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\thex1 <= eight;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tiii <= iii + 1;\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t\\\\t1: begin \\\\n\\\\t\\\\t\\\\t\\\\t\\\\thex1<= blank;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tiii <= iii - 1;\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\tendcase\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\tend\\\\n\\\\tendgenerate*/\\\\n\\\\n\\\\ninteger iss =0;\\\\nreg [6:0] Hex1s;\\\\n\\\\talways@(posedge clk) begin\\\\n\\\\tif (check_pass == 2\\'b11)\\\\n\\\\tbegin\\\\n\\\\tcase(iss)\\\\n\\\\t\\\\t0:\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\tHex1s <= zero;\\\\n\\\\t\\\\t\\\\t\\\\tiss = iss +1;\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t1:\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\tHex1s <= one;\\\\n\\\\t\\\\t\\\\t\\\\tiss = iss +1;\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t2:\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\tHex1s <= two;\\\\n\\\\t\\\\t\\\\t\\\\tiss = iss +1;\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t3:\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\tHex1s <= three;\\\\n\\\\t\\\\t\\\\t\\\\tiss = iss +1;\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t4:\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\tHex1s <= four;\\\\n\\\\t\\\\t\\\\t\\\\tiss = iss +1;\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t5:\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\tHex1s <= five;iss = iss +1;\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t6:\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\tHex1s <= six;\\\\n\\\\t\\\\t\\\\t\\\\tiss = iss +1;\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t7:\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\tHex1s <= seven;\\\\n\\\\t\\\\t\\\\t\\\\tiss = iss +1;\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t8:\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\tHex1s <= eight;iss = iss +1;\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t9:\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\tHex1s <= nine;iss = iss +1;\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t10: begin\\\\n\\\\t\\\\t\\\\t\\\\tHex1s <= zero;\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\tendcase\\\\nend\\\\nelse iss = 0;\\\\nend\\\\n\\\\n\\\\n\\\\n\\\\t\\\\n\\\\twire data_ready;\\\\n\\\\twire [31:0] hex_data; \\\\n\\\\tIR_RECEIVE u2(\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t///clk 50MHz////\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t.iCLK(CLOCK_50), \\\\n\\\\t\\\\t\\\\t\\\\t\\\\t//reset \\\\n\\\\t\\\\t\\\\t\\\\t\\\\t.iRST_n(1\\'b1), \\\\n\\\\t\\\\t\\\\t\\\\t\\\\t//IRDA code input\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t.iIRDA(IRDA_RXD), \\\\n\\\\t\\\\t\\\\t\\\\t\\\\t//read command \\\\n\\\\t\\\\t\\\\t\\\\t\\\\t//.iREAD(data_read),\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t//data ready \\\\t\\\\t\\\\t\\\\t\\\\t\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t.oDATA_READY(data_ready),\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t//decoded data 32bit\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t.oDATA(hex_data) \\\\n\\\\t\\\\t\\\\t\\\\t\\\\t);\\\\t\\\\t\\\\ninteger iis =0;\\\\ninteger iisck =0;\\\\nalways@(negedge data_ready)begin \\\\n\\\\t//if (select_seg == 3\\'b100) begin\\\\n\\\\t\\\\t\\\\tif (checkremote == 1\\'b0)\\\\n\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\thextemp = blank;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\thexarray[4] <= hextemp;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\thexarray[3] <= hextemp;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\thexarray[2] <= hextemp;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\thexarray[1] <= hextemp;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\thexarray[0] <= hextemp;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\thexarrayck[4] <= hextemp;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\thexarrayck[3] <= two;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\thexarrayck[2] <= five;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\thexarrayck[1] <= four;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\thexarrayck[0] <= one;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\thexarrayt[4] <= hextemp;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\thexarrayt[3] <= hextemp;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\thexarrayt[2] <= hextemp;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\thexarrayt[1] <= hextemp;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\thexarrayt[0] <= hextemp;\\\\n\\\\t\\\\t\\\\t\\\\tii=0;\\\\t\\\\n\\\\t\\\\t\\\\t\\\\tiis=0;\\\\n\\\\t\\\\t\\\\t\\\\tiisck =0;\\\\n\\\\t\\\\t\\\\t\\\\tcheck_pass = 2\\'b00;\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\telse\\\\n\\\\t\\\\t\\\\tif ((ii < 4)) begin\\\\n\\\\t\\\\t\\\\tcase(hex_data[23:16])\\\\n\\\\t\\\\t\\\\t\\\\t8\\'h00: begin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tinput_string[ii] = \\\\"0\\\\";\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t//ii =ii +1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\thextemp= zero;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t/*hexarray[ii] = hextemp;\\\\n\\\\t\\\\t\\\\t\\\\thexarrayt[ii] = hextemp;\\\\n\\\\t\\\\t\\\\t\\\\tii = ii+1;*/\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\n\\\\t\\\\t\\\\t\\\\t8\\'h01: begin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tinput_string[ii] = \\\\"1\\\\";\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t//ii =ii +1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\thextemp= one;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t/*hexarray[ii] = hextemp;\\\\n\\\\t\\\\t\\\\t\\\\thexarrayt[ii] = hextemp;\\\\n\\\\t\\\\t\\\\t\\\\tii = ii+1;*/\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\n\\\\t\\\\t\\\\t\\\\t8\\'h02: begin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tinput_string[ii] = \\\\"2\\\\";\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t//ii =ii +1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\thextemp= two;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t/*hexarray[ii] = hextemp;\\\\n\\\\t\\\\t\\\\t\\\\thexarrayt[ii] = hextemp;\\\\n\\\\t\\\\t\\\\t\\\\tii = ii+1;*/\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\n\\\\t\\\\t\\\\t\\\\t8\\'h03: begin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tinput_string[ii] = \\\\"3\\\\";\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t//ii =ii +1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\thextemp= three;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t/*hexarray[ii] = hextemp;\\\\n\\\\t\\\\t\\\\t\\\\thexarrayt[ii] = hextemp;\\\\n\\\\t\\\\t\\\\t\\\\tii = ii+1;*/\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\n\\\\t\\\\t\\\\t\\\\t8\\'h04: begin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tinput_string[ii] = \\\\"4\\\\";\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t//ii =ii +1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\thextemp= four;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t/*hexarray[ii] = hextemp;\\\\n\\\\t\\\\t\\\\t\\\\thexarrayt[ii] = hextemp;\\\\n\\\\t\\\\t\\\\t\\\\tii = ii+1;*/\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\n\\\\t\\\\t\\\\t\\\\t8\\'h05: begin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tinput_string[ii] = \\\\"5\\\\";\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t//ii =ii +1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\thextemp= five;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t/*hexarray[ii] = hextemp;\\\\n\\\\t\\\\t\\\\t\\\\thexarrayt[ii] = hextemp;\\\\n\\\\t\\\\t\\\\t\\\\tii = ii+1;*/\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t\\\\t8\\'h06: begin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tinput_string[ii] = \\\\"6\\\\";\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t//ii =ii +1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\thextemp= six;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t/*hexarray[ii] = hextemp;\\\\n\\\\t\\\\t\\\\t\\\\thexarrayt[ii] = hextemp;\\\\n\\\\t\\\\t\\\\t\\\\tii = ii+1;*/\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\n\\\\t\\\\t\\\\t\\\\t8\\'h07: begin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tinput_string[ii] = \\\\"7\\\\";\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t//ii =ii +1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\thextemp= seven;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t/*hexarray[ii] = hextemp;\\\\n\\\\t\\\\t\\\\t\\\\thexarrayt[ii] = hextemp;\\\\n\\\\t\\\\t\\\\t\\\\tii = ii+1;*/\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\n\\\\t\\\\t\\\\t\\\\t8\\'h08: begin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tinput_string[ii] = \\\\"8\\\\";\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t//ii =ii +1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\thextemp= eight;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t/*hexarray[ii] = hextemp;\\\\n\\\\t\\\\t\\\\t\\\\thexarrayt[ii] = hextemp;\\\\n\\\\t\\\\t\\\\t\\\\tii = ii+1;*/\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\n\\\\t\\\\t\\\\t\\\\t8\\'h09: begin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tinput_string[ii] = \\\\"9\\\\";\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t//ii =ii +1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\thextemp= nine;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t/*hexarray[ii] = hextemp;\\\\n\\\\t\\\\t\\\\t\\\\thexarrayt[ii] = hextemp;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tii = ii+1;*/\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t\\\\tdefault: begin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\thextemp = blank;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\thexarray[4] <= hextemp;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\thexarray[3] <= hextemp;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\thexarray[2] <= hextemp;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\thexarray[1] <= hextemp;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\thexarray[0] <= hextemp;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\thexarrayt[4] <= hextemp;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\thexarrayt[3] <= hextemp;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\thexarrayt[2] <= hextemp;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\thexarrayt[1] <= hextemp;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\thexarrayt[0] <= hextemp;\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\tendcase\\\\n\\\\t\\\\t\\\\t\\\\thexarray[ii] <= eight;\\\\n\\\\t\\\\t\\\\t\\\\thexarrayt[ii] <= hextemp;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tii = ii+1;\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\telse begin\\\\n\\\\t\\\\t\\\\t\\\\tcase(hex_data[23:16])\\\\n\\\\t\\\\t\\\\t\\\\t8\\'h1E: begin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\td=1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t\\\\t8\\'h1A: begin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tfor (iis =0; iis <4; iis = iis +1)\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tif (hexarrayt[iis] == hexarrayck[iis]) \\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tiisck = iisck+1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tif (iisck >= 3) begin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\td=1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tcheck_pass = 2\\'b01;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t\\\\t\\\\telse begin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\thextemp = blank;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\thexarray[4] <= hextemp;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\thexarray[3] <= hextemp;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\thexarray[2] <= hextemp;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\thexarray[1] <= hextemp;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\thexarray[0] <= hextemp;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\thexarrayt[4] <= hextemp;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\thexarrayt[3] <= hextemp;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\thexarrayt[2] <= hextemp;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\thexarrayt[1] <= hextemp;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\thexarrayt[0] <= hextemp;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tii=0;\\\\t\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tiis=0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tiisck =0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tcheck_pass = 2\\'b10;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\td=3;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t\\\\t8\\'h16:begin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tif(check_pass ==2\\'b01) begin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\td=2;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tcheck_pass = 2\\'b11;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t\\\\t\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t\\\\tdefault: begin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\td=3;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t\\\\tendcase\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\tend\\\\n\\\\t//end\\\\n\\\\t\\\\n\\\\tinteger d=0;\\\\nalways @(*)\\\\nbegin\\\\ncase(select_seg)\\\\n\\\\t3\\'b000:\\\\n\\\\tbegin\\\\n\\\\t\\\\tt=0;\\\\n\\\\t\\\\thex_out = blank;\\\\n\\\\tend\\\\n\\\\t3\\'b001:\\\\n\\\\tbegin\\\\n\\\\tt=0;\\\\n\\\\t\\\\thex_out = hex;\\\\n\\\\tend\\\\n\\\\t3\\'b010:\\\\n\\\\tbegin\\\\n\\\\tt=0;\\\\n\\\\t\\\\thex_out = hex1;\\\\n\\\\tend\\\\n\\\\t3\\'b011:\\\\n\\\\tbegin\\\\n\\\\tt=0;\\\\n\\\\t\\\\thex_out = blank;\\\\n\\\\tend\\\\n\\\\t3\\'b100:\\\\n\\\\tbegin\\\\n\\\\t\\\\t//t=1;\\\\n\\\\t\\\\thex2 = pl;\\\\n\\\\t\\\\thex3 = al;\\\\n\\\\t\\\\thex4 = sl;\\\\n\\\\t\\\\thex5 = sl;\\\\n\\\\t\\\\tif (d==1) t = 1;\\\\n\\\\t\\\\telse if (d==2) t=3;\\\\n\\\\t\\\\telse t =4;\\\\n\\\\t\\\\t\\\\n\\\\t\\\\t\\\\n\\\\t\\\\t/*for(d =0 ;d <4; d= d+1) begin\\\\n\\\\t\\\\t\\\\thexarrayt[d] = blank;\\\\n\\\\t\\\\t\\\\thexarray[d] = blank;\\\\n\\\\t\\\\t\\\\n\\\\t\\\\tend*/\\\\n\\\\t\\\\t\\\\n\\\\t\\\\t\\\\n\\\\t\\\\t\\\\n\\\\t\\\\t\\\\n\\\\t\\\\t/*case(hex_data[23:16])\\\\n\\\\t\\\\t\\\\t\\\\t8\\'h01: begin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\thextemp <= one;\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t\\\\t8\\'h00: begin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\thextemp <= zero;\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t\\\\tdefault: begin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\thextemp <= blank;\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\tendcase\\\\n\\\\t\\\\thexarrayt[0] = hextemp;\\\\n\\\\t\\\\thexarrayt[1] = hextemp;\\\\n\\\\t\\\\thexarrayt[2] = hextemp;\\\\n\\\\t\\\\thexarrayt[3] = hextemp;*/\\\\n\\\\t\\\\t\\\\n\\\\t\\\\t/*hex6 <= eight;\\\\n\\\\t\\\\thex7 <= eight;\\\\n\\\\t\\\\thex8 <= eight;\\\\n\\\\t\\\\thex9 <= eight;*/\\\\n\\\\t\\\\t\\\\n\\\\t\\\\t/*if (ii < 4) begin\\\\n\\\\t\\\\t\\\\tcase(hex_data[23:16])\\\\n\\\\t\\\\t\\\\t\\\\t8\\'h00: begin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tinput_string[ii] = \\\\"0\\\\";\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t//ii =ii +1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\thextemp<= zero;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\thexarray[ii] = hextemp;\\\\n\\\\t\\\\t\\\\t\\\\thexarrayt[ii] = hextemp;\\\\n\\\\t\\\\t\\\\t\\\\tii = ii+1;\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\n\\\\t\\\\t\\\\t\\\\t8\\'h01: begin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tinput_string[ii] = \\\\"1\\\\";\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t//ii =ii +1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\thextemp<= one;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\thexarray[ii] = hextemp;\\\\n\\\\t\\\\t\\\\t\\\\thexarrayt[ii] = hextemp;\\\\n\\\\t\\\\t\\\\t\\\\tii = ii+1;\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\n\\\\t\\\\t\\\\t\\\\t8\\'h02: begin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tinput_string[ii] = \\\\"2\\\\";\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t//ii =ii +1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\thextemp<= two;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\thexarray[ii] = hextemp;\\\\n\\\\t\\\\t\\\\t\\\\thexarrayt[ii] = hextemp;\\\\n\\\\t\\\\t\\\\t\\\\tii = ii+1;\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\n\\\\t\\\\t\\\\t\\\\t8\\'h03: begin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tinput_string[ii] = \\\\"3\\\\";\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t//ii =ii +1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\thextemp<= three;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\thexarray[ii] = hextemp;\\\\n\\\\t\\\\t\\\\t\\\\thexarrayt[ii] = hextemp;\\\\n\\\\t\\\\t\\\\t\\\\tii = ii+1;\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\n\\\\t\\\\t\\\\t\\\\t8\\'h04: begin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tinput_string[ii] = \\\\"4\\\\";\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t//ii =ii +1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\thextemp<= four;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\thexarray[ii] = hextemp;\\\\n\\\\t\\\\t\\\\t\\\\thexarrayt[ii] = hextemp;\\\\n\\\\t\\\\t\\\\t\\\\tii = ii+1;\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\n\\\\t\\\\t\\\\t\\\\t8\\'h05: begin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tinput_string[ii] = \\\\"5\\\\";\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t//ii =ii +1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\thextemp<= five;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\thexarray[ii] = hextemp;\\\\n\\\\t\\\\t\\\\t\\\\thexarrayt[ii] = hextemp;\\\\n\\\\t\\\\t\\\\t\\\\tii = ii+1;\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t\\\\t8\\'h06: begin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tinput_string[ii] = \\\\"6\\\\";\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t//ii =ii +1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\thextemp<= six;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\thexarray[ii] = hextemp;\\\\n\\\\t\\\\t\\\\t\\\\thexarrayt[ii] = hextemp;\\\\n\\\\t\\\\t\\\\t\\\\tii = ii+1;\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\n\\\\t\\\\t\\\\t\\\\t8\\'h07: begin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tinput_string[ii] = \\\\"7\\\\";\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t//ii =ii +1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\thextemp<= seven;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\thexarray[ii] = hextemp;\\\\n\\\\t\\\\t\\\\t\\\\thexarrayt[ii] = hextemp;\\\\n\\\\t\\\\t\\\\t\\\\tii = ii+1;\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\n\\\\t\\\\t\\\\t\\\\t8\\'h08: begin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tinput_string[ii] = \\\\"8\\\\";\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t//ii =ii +1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\thextemp<= eight;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\thexarray[ii] = hextemp;\\\\n\\\\t\\\\t\\\\t\\\\thexarrayt[ii] = hextemp;\\\\n\\\\t\\\\t\\\\t\\\\tii = ii+1;\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\n\\\\t\\\\t\\\\t\\\\t8\\'h09: begin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tinput_string[ii] = \\\\"9\\\\";\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t//ii =ii +1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\thextemp<= nine;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\thexarray[ii] = hextemp;\\\\n\\\\t\\\\t\\\\t\\\\thexarrayt[ii] = hextemp;\\\\n\\\\t\\\\t\\\\t\\\\tii = ii+1;\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t\\\\tdefault: begin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\thextemp <= blank;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\thexarray[ii] = hextemp;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\thexarrayt[ii] = hextemp;\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\tendcase\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\tif ((hex_data[23:16] == 8\\'h1A)) begin\\\\n\\\\t\\\\tt = 2;\\\\n\\\\t\\\\tend*/\\\\n\\\\t\\\\t\\\\n\\\\tend\\\\n\\\\tdefault:\\\\n\\\\tbegin\\\\n\\\\thex_out = blank;\\\\n\\\\tend\\\\nendcase\\\\nend\\\\n/*assign HEX0 = hex_out;\\\\n\\\\tassign HEX1 = hex_out;\\\\n\\\\tassign HEX2 = hex_out;\\\\n\\\\tassign HEX3 = hex_out;\\\\n\\\\tassign HEX4 = hex_out;\\\\n\\\\tassign HEX5 = hex_out;\\\\n\\\\tassign HEX6 = hex_out;\\\\n\\\\tassign HEX7 = hex_out;\\\\n\\\\t*/\\\\n\\\\tassign HEX0 = (t==0)?hex_out:(t==1)?hexarrayt[0]:(t==3)?Hex1s:hexarray[0];\\\\n\\\\tassign HEX1 = (t==0)?hex_out:(t==1)?hexarrayt[1]:(t==3)?Hex1s:hexarray[1];\\\\n\\\\tassign HEX2 = (t==0)?hex_out:(t==1)?hexarrayt[2]:(t==3)?Hex1s:hexarray[2];\\\\n\\\\tassign HEX3 = (t==0)?hex_out:(t==1)?hexarrayt[3]:(t==3)?Hex1s:hexarray[3];\\\\n\\\\tassign HEX4 = (t==0)?hex_out:(t==1)?hex5:(t==3)?Hex1s:hex5;\\\\n\\\\tassign HEX5 = (t==0)?hex_out:(t==1)?hex4:(t==3)?Hex1s:hex4;\\\\n\\\\tassign HEX6 =(t==0)?hex_out:(t==1)?hex3:(t==3)?Hex1s:hex3;\\\\n\\\\tassign HEX7 = (t==0)?hex_out:(t==1)?hex2:(t==3)?Hex1s:hex2;\\\\nendmodule']
["module NN(\\\\n\\\\t// Input signals\\\\n\\\\tclk,\\\\n\\\\trst_n,\\\\n\\\\tin_valid,\\\\n\\\\tweight_u,\\\\n\\\\tweight_w,\\\\n\\\\tweight_v,\\\\n\\\\tdata_x,\\\\n\\\\tdata_h,\\\\n\\\\t// Output signals\\\\n\\\\tout_valid,\\\\n\\\\tout\\\\n);\\\\n\\\\n//---------------------------------------------------------------------\\\\n// PARAMETER\\\\n//---------------------------------------------------------------------\\\\n\\\\n// IEEE floating point paramenters\\\\nparameter inst_sig_width = 23;\\\\nparameter inst_exp_width = 8;\\\\nparameter inst_ieee_compliance = 0;\\\\nparameter inst_arch = 2;\\\\n\\\\n//---------------------------------------------------------------------\\\\n// INPUT AND OUTPUT DECLARATION\\\\n//---------------------------------------------------------------------\\\\ninput clk, rst_n, in_valid;\\\\ninput [inst_sig_width+inst_exp_width:0] weight_u, weight_w, weight_v;\\\\ninput [inst_sig_width+inst_exp_width:0] data_x,data_h;\\\\noutput reg\\\\tout_valid;\\\\noutput reg [inst_sig_width+inst_exp_width:0] out;\\\\n\\\\n//---------------------------------------------------------------------\\\\n// WIRE AND REG DECLARATION\\\\n//---------------------------------------------------------------------\\\\ninteger i;\\\\n\\\\n\\\\n//---------------------------------------------------------------------\\\\n// WIRE AND REG DECLARATION\\\\n//---------------------------------------------------------------------\\\\nreg [5:0] count;\\\\n\\\\nreg [31:0] U[8:0];\\\\nreg [31:0] V[8:0];\\\\nreg [31:0] W[8:0];\\\\nreg [31:0] X[8:0];\\\\nreg [31:0] H[2:0];\\\\n\\\\nreg [31:0] mult_1_in_1;\\\\nreg [31:0] mult_1_in_2;\\\\nreg [31:0] mult_2_in_1;\\\\nreg [31:0] mult_2_in_2;\\\\nreg [31:0] mult_3_in_1;\\\\nreg [31:0] mult_3_in_2;\\\\n\\\\nwire [31:0] mult_1_out;\\\\nwire [31:0] mult_2_out;\\\\nwire [31:0] mult_3_out;\\\\n\\\\nreg [31:0] mult_1_out_buffer;\\\\nreg [31:0] mult_2_out_buffer;\\\\nreg [31:0] mult_3_out_buffer;\\\\n\\\\nreg [31:0] add_1_in_1;\\\\nreg [31:0] add_1_in_2;\\\\nreg [31:0] add_2_in_1;\\\\nreg [31:0] add_2_in_2;\\\\nreg [31:0] add_3_in_1;\\\\nreg [31:0] add_3_in_2;\\\\n\\\\nwire [31:0] add_1_out;\\\\nwire [31:0] add_2_out;\\\\nwire [31:0] add_3_out;\\\\n\\\\nreg [31:0] matrix_out_buffer[2:0];\\\\n\\\\nreg [31:0] add_out_buffer[2:0];\\\\n\\\\nreg [31:0] leaky_relu_out[2:0];\\\\n\\\\nreg [31:0] y_temp[2:0];\\\\n\\\\nwire [31:0] exp_in;\\\\nwire [31:0] exp_out;\\\\nreg [31:0] exp_out_buffer;\\\\n\\\\nwire [31:0] recip_out;\\\\n\\\\nreg [31:0] next_output;\\\\nreg next_outvalid;\\\\n\\\\n//---------------------------------------------------------------------\\\\n// STORE INPUT\\\\n//---------------------------------------------------------------------\\\\nalways @(posedge clk or negedge rst_n) begin\\\\n if(!rst_n)begin\\\\n\\\\t\\\\tfor(i=0;i<9;i=i+1) begin\\\\n\\\\t\\\\t\\\\tU[i] <= 0;\\\\n\\\\t\\\\tend\\\\n end \\\\n else begin\\\\n\\\\t\\\\tif(in_valid) begin\\\\n\\\\t\\\\t\\\\tfor(i=0;i<8;i=i+1) begin\\\\n\\\\t\\\\t\\\\t\\\\tU[i+1] <= U[i];\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\tU[0] <= weight_u;\\\\n\\\\t\\\\tend\\\\n\\\\t\\\\telse begin\\\\n\\\\t\\\\t\\\\tfor(i=0;i<9;i=i+1) begin\\\\n\\\\t\\\\t\\\\t\\\\tU[i] <= U[i];\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\tend\\\\n\\\\tend\\\\nend\\\\n\\\\nalways @(posedge clk or negedge rst_n) begin\\\\n if(!rst_n)begin\\\\n\\\\t\\\\tfor(i=0;i<9;i=i+1) begin\\\\n\\\\t\\\\t\\\\tV[i] <= 0;\\\\n\\\\t\\\\tend\\\\n end \\\\n else begin\\\\n\\\\t\\\\tif(in_valid) begin\\\\n\\\\t\\\\t\\\\tfor(i=0;i<8;i=i+1) begin\\\\n\\\\t\\\\t\\\\t\\\\tV[i+1] <= V[i];\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\tV[0] <= weight_v;\\\\n\\\\t\\\\tend\\\\n\\\\t\\\\telse begin\\\\n\\\\t\\\\t\\\\tfor(i=0;i<9;i=i+1) begin\\\\n\\\\t\\\\t\\\\t\\\\tV[i] <= V[i];\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\tend\\\\n\\\\tend\\\\nend\\\\n\\\\nalways @(posedge clk or negedge rst_n) begin\\\\n if(!rst_n)begin\\\\n\\\\t\\\\tfor(i=0;i<9;i=i+1) begin\\\\n\\\\t\\\\t\\\\tW[i] <= 0;\\\\n\\\\t\\\\tend\\\\n end \\\\n else begin\\\\n\\\\t\\\\tif(in_valid) begin\\\\n\\\\t\\\\tfor(i=0;i<8;i=i+1) begin\\\\n\\\\t\\\\t\\\\tW[i+1] <= W[i];\\\\n\\\\t\\\\tend\\\\n\\\\t\\\\tW[0] <= weight_w;\\\\n\\\\t\\\\tend\\\\n\\\\t\\\\telse begin\\\\n\\\\t\\\\t\\\\tfor(i=0;i<9;i=i+1) begin\\\\n\\\\t\\\\t\\\\t\\\\tW[i] <= W[i];\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\tend\\\\n\\\\tend\\\\nend\\\\n\\\\nalways @(posedge clk or negedge rst_n) begin\\\\n if(!rst_n)begin\\\\n\\\\t\\\\tfor(i=0;i<9;i=i+1) begin\\\\n\\\\t\\\\t\\\\tX[i] <= 0;\\\\n\\\\t\\\\tend\\\\n end \\\\n else begin\\\\n\\\\t\\\\tcase(count)\\\\n\\\\t\\\\t\\\\t'd0, 'd1, 'd2, 'd3, 'd4, 'd5, 'd6, 'd7, 'd8: begin\\\\n\\\\t\\\\t\\\\t\\\\tfor(i=0;i<8;i=i+1) begin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tX[i+1] <= X[i];\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t\\\\tX[0] <= data_x;\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t'd17, 'd27: begin\\\\n\\\\t\\\\t\\\\t\\\\tX[5] <= matrix_out_buffer[2];\\\\n\\\\t\\\\t\\\\t\\\\tX[4] <= matrix_out_buffer[0];\\\\n\\\\t\\\\t\\\\t\\\\tX[3] <= add_2_out;\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t'd31: begin\\\\n\\\\t\\\\t\\\\t\\\\tX[2] <= leaky_relu_out[2];\\\\n\\\\t\\\\t\\\\t\\\\tX[1] <= leaky_relu_out[1];\\\\n\\\\t\\\\t\\\\t\\\\tX[0] <= leaky_relu_out[0];\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\tdefault: begin\\\\n\\\\t\\\\t\\\\t\\\\tfor(i=0;i<9;i=i+1) begin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tX[i] <= X[i];\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\tendcase\\\\n\\\\tend\\\\nend\\\\n\\\\nalways @(posedge clk or negedge rst_n) begin\\\\n if(!rst_n)begin\\\\n\\\\t\\\\tfor(i=0;i<3;i=i+1) begin\\\\n\\\\t\\\\t\\\\tH[i] <= 0;\\\\n\\\\t\\\\tend\\\\n end \\\\n else begin\\\\n\\\\t\\\\tcase(count)\\\\n\\\\t\\\\t'd0, 'd1, 'd2: begin\\\\n\\\\t\\\\t\\\\tfor(i=0;i<2;i=i+1) begin\\\\n\\\\t\\\\t\\\\t\\\\tH[i+1] <= H[i];\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\tH[0] <= data_h;\\\\n\\\\t\\\\tend\\\\n\\\\t\\\\t'd10: begin\\\\n\\\\t\\\\t\\\\tH[2] <= matrix_out_buffer[1];\\\\n\\\\t\\\\t\\\\tH[1] <= matrix_out_buffer[0];\\\\n\\\\t\\\\t\\\\tH[0] <= add_2_out;\\\\n\\\\t\\\\tend\\\\n\\\\t\\\\t'd14: begin\\\\n\\\\t\\\\t\\\\tH[2] <= leaky_relu_out[2];\\\\n\\\\t\\\\t\\\\tH[1] <= leaky_relu_out[1];\\\\n\\\\t\\\\t\\\\tH[0] <= leaky_relu_out[0];\\\\n\\\\t\\\\tend\\\\n\\\\t\\\\t'd24: begin\\\\n\\\\t\\\\t\\\\tH[2] <= leaky_relu_out[2];\\\\n\\\\t\\\\t\\\\tH[1] <= leaky_relu_out[1];\\\\n\\\\t\\\\t\\\\tH[0] <= leaky_relu_out[0];\\\\n\\\\t\\\\tend\\\\n\\\\t\\\\tdefault: begin\\\\n\\\\t\\\\t\\\\tfor(i=0;i<3;i=i+1) begin\\\\n\\\\t\\\\t\\\\t\\\\tH[i] <= H[i];\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\tend\\\\n\\\\t\\\\tendcase\\\\n\\\\tend\\\\nend\\\\n\\\\n\\\\n//---------------------------------------------------------------------\\\\n// COUNT\\\\n//---------------------------------------------------------------------\\\\nwire [9:0] next_count;\\\\nassign next_count = count + 1;\\\\nalways @(posedge clk or negedge rst_n) begin\\\\n\\\\tif(!rst_n) begin\\\\n\\\\t\\\\tcount <= 0;\\\\n\\\\tend\\\\n\\\\telse begin\\\\n\\\\t\\\\tif(in_valid || (count > 0 && count < 42))\\\\n\\\\t\\\\t\\\\tcount <= next_count;\\\\n\\\\t\\\\telse\\\\n\\\\t\\\\t\\\\tcount <= 0;\\\\n\\\\tend\\\\nend\\\\n\\\\n//---------------------------------------------------------------------\\\\n// DESIGN WARE\\\\n//---------------------------------------------------------------------\\\\nfp_mult M1 (.a(mult_1_in_1), .b(mult_1_in_2), .out(mult_1_out));\\\\nfp_mult M2 (.a(mult_2_in_1), .b(mult_2_in_2), .out(mult_2_out));\\\\nfp_mult M3 (.a(mult_3_in_1), .b(mult_3_in_2), .out(mult_3_out));\\\\n\\\\nfp_add A1 (.a(add_1_in_1), .b(add_1_in_2), .out(add_1_out));\\\\nfp_add A2 (.a(add_2_in_1), .b(add_2_in_2), .out(add_2_out));\\\\nfp_add A3 (.a(add_3_in_1), .b(add_3_in_2), .out(add_3_out));\\\\n\\\\nfp_exp E1(.a(exp_in), .out(exp_out));\\\\nfp_recip R1(.a(add_out_buffer[0]), .out(recip_out));\\\\n\\\\n//---------------------------------------------------------------------\\\\n// DESIGN WARE INPUT CONTROL\\\\n//---------------------------------------------------------------------\\\\n\\\\n// multiplier input\\\\nalways@(*) begin\\\\n\\\\tcase(count)\\\\n\\\\t'd7, 'd8, 'd9, 'd17, 'd18, 'd19, 'd20, 'd21, 'd22, 'd27, 'd28, 'd29, 'd30, 'd32, 'd33: mult_1_in_1 = H[2];\\\\n\\\\t'd10, 'd11, 'd12: mult_1_in_1 = X[8];\\\\n\\\\t'd14, 'd24, 'd31: mult_1_in_1 = 'b00111101110011001100110011001101;\\\\n\\\\t'd13, 'd15, 'd16: mult_1_in_1 = X[5];\\\\n\\\\t'd23, 'd25, 'd26, 'd34, 'd35, 'd36: mult_1_in_1 = X[2];\\\\n\\\\tdefault: mult_1_in_1 = 0;\\\\n\\\\tendcase\\\\nend\\\\n\\\\nalways@(*) begin\\\\n\\\\tcase(count)\\\\n\\\\t'd7: mult_1_in_2 = W[6];\\\\n\\\\t'd8: mult_1_in_2 = W[4];\\\\n\\\\t'd9: mult_1_in_2 = W[2];\\\\n\\\\t'd10, 'd13, 'd23: mult_1_in_2 = U[8];\\\\n\\\\t'd11, 'd15, 'd25: mult_1_in_2 = U[5];\\\\n\\\\t'd12, 'd16, 'd26: mult_1_in_2 = U[2];\\\\n\\\\t'd14, 'd24, 'd31: mult_1_in_2 = add_out_buffer[2];\\\\n\\\\t'd17, 'd30, 'd34: mult_1_in_2 = V[8];\\\\n\\\\t'd18, 'd32, 'd35: mult_1_in_2 = V[5];\\\\n\\\\t'd19, 'd33, 'd36: mult_1_in_2 = V[2];\\\\n\\\\t'd20, 'd27: mult_1_in_2 = W[8];\\\\n\\\\t'd21, 'd28: mult_1_in_2 = W[5];\\\\n\\\\t'd22, 'd29: mult_1_in_2 = W[2];\\\\n\\\\tdefault: mult_1_in_2 = 0;\\\\n\\\\tendcase\\\\nend\\\\n\\\\nalways@(*) begin\\\\n\\\\tcase(count)\\\\n\\\\t\\\\t'd7, 'd8, 'd9, 'd17, 'd18, 'd19, 'd20, 'd21, 'd22, 'd27, 'd28, 'd29, 'd30, 'd32, 'd33: mult_2_in_1 = H[1];\\\\n\\\\t\\\\t'd10, 'd11, 'd12: mult_2_in_1 = X[7];\\\\n\\\\t\\\\t'd14, 'd24, 'd31: mult_2_in_1 = 'b00111101110011001100110011001101;\\\\n\\\\t\\\\t'd13, 'd15, 'd16: mult_2_in_1 = X[4];\\\\n\\\\t\\\\t'd23, 'd25, 'd26, 'd34, 'd35, 'd36: mult_2_in_1 = X[1];\\\\n\\\\t\\\\tdefault: mult_2_in_1 = 0;\\\\n\\\\tendcase\\\\nend\\\\n\\\\nalways@(*) begin\\\\n\\\\tcase(count)\\\\n\\\\t'd7: mult_2_in_2 = W[5];\\\\n\\\\t'd8: mult_2_in_2 = W[3];\\\\n\\\\t'd9: mult_2_in_2 = W[1];\\\\n\\\\t'd10, 'd13, 'd23: mult_2_in_2 = U[7];\\\\n\\\\t'd11, 'd15, 'd25: mult_2_in_2 = U[4];\\\\n\\\\t'd12, 'd16, 'd26: mult_2_in_2 = U[1];\\\\n\\\\t'd14, 'd24, 'd31: mult_2_in_2 = add_out_buffer[1];\\\\n\\\\t'd17, 'd30, 'd34: mult_2_in_2 = V[7];\\\\n\\\\t'd18, 'd32, 'd35: mult_2_in_2 = V[4];\\\\n\\\\t'd19, 'd33, 'd36: mult_2_in_2 = V[1];\\\\n\\\\t'd20, 'd27: mult_2_in_2 = W[7];\\\\n\\\\t'd21, 'd28: mult_2_in_2 = W[4];\\\\n\\\\t'd22, 'd29: mult_2_in_2 = W[1];\\\\n\\\\tdefault: mult_2_in_2 = 0;\\\\n\\\\tendcase\\\\nend\\\\n\\\\nalways@(*) begin\\\\n\\\\tcase(count)\\\\n\\\\t'd7, 'd8, 'd9, 'd17, 'd18, 'd19, 'd20, 'd21, 'd22, 'd27, 'd28, 'd29, 'd30, 'd32, 'd33: mult_3_in_1 = H[0];\\\\n\\\\t'd10, 'd11, 'd12: mult_3_in_1 = X[6];\\\\n\\\\t'd14, 'd24, 'd31: mult_3_in_1 = 'b00111101110011001100110011001101;\\\\n\\\\t'd13, 'd15, 'd16: mult_3_in_1 = X[3];\\\\n\\\\t'd23, 'd25, 'd26, 'd34, 'd35, 'd36: mult_3_in_1 = X[0];\\\\n\\\\tdefault: mult_3_in_1 = 0;\\\\n\\\\tendcase\\\\nend\\\\n\\\\nalways@(*) begin\\\\n\\\\tcase(count)\\\\n\\\\t'd7: mult_3_in_2 = W[4];\\\\n\\\\t'd8: mult_3_in_2 = W[2];\\\\n\\\\t'd9: mult_3_in_2 = W[0];\\\\n\\\\t'd10, 'd13, 'd23: mult_3_in_2 = U[6];\\\\n\\\\t'd11, 'd15, 'd25: mult_3_in_2 = U[3];\\\\n\\\\t'd12, 'd16, 'd26: mult_3_in_2 = U[0];\\\\n\\\\t'd14, 'd24, 'd31: mult_3_in_2 = add_out_buffer[0];\\\\n\\\\t'd17, 'd30, 'd34: mult_3_in_2 = V[6];\\\\n\\\\t'd18, 'd32, 'd35: mult_3_in_2 = V[3];\\\\n\\\\t'd19, 'd33, 'd36: mult_3_in_2 = V[0];\\\\n\\\\t'd20, 'd27: mult_3_in_2 = W[6];\\\\n\\\\t'd21, 'd28: mult_3_in_2 = W[3];\\\\n\\\\t'd22, 'd29: mult_3_in_2 = W[0];\\\\n\\\\tdefault: mult_3_in_2 = 0;\\\\n\\\\tendcase\\\\nend\\\\n\\\\n// multiplier output buffer\\\\nalways@(posedge clk or negedge rst_n) begin\\\\n\\\\tif(!rst_n)\\\\n\\\\t\\\\tmult_1_out_buffer <= 0;\\\\n\\\\telse begin\\\\n\\\\t\\\\tmult_1_out_buffer <= mult_1_out;\\\\n\\\\tend\\\\nend\\\\n\\\\nalways@(posedge clk or negedge rst_n) begin\\\\n\\\\tif(!rst_n)\\\\n\\\\t\\\\tmult_2_out_buffer <= 0;\\\\n\\\\telse begin\\\\n\\\\t\\\\tmult_2_out_buffer <= mult_2_out;\\\\n\\\\tend\\\\nend\\\\n\\\\nalways@(posedge clk or negedge rst_n) begin\\\\n\\\\tif(!rst_n)\\\\n\\\\t\\\\tmult_3_out_buffer <= 0;\\\\n\\\\telse begin\\\\n\\\\t\\\\tmult_3_out_buffer <= mult_3_out;\\\\n\\\\tend\\\\nend\\\\n\\\\n// adder input control\\\\nalways@(*) begin\\\\n\\\\tadd_1_in_1 = mult_1_out_buffer;\\\\nend\\\\n\\\\nalways@(*) begin\\\\n\\\\tadd_1_in_2 = mult_2_out_buffer;\\\\nend\\\\n\\\\nalways@(*) begin\\\\n\\\\tadd_2_in_1 = mult_3_out_buffer;\\\\nend\\\\n\\\\nalways@(*) begin\\\\n\\\\tcase(count)\\\\n\\\\t\\\\t'd11: add_2_in_2 = H[2];\\\\n\\\\t\\\\t'd12: add_2_in_2 = H[1];\\\\n\\\\t\\\\t'd13: add_2_in_2 = H[0];\\\\n\\\\t\\\\t'd21, 'd28: add_2_in_2 = X[5];\\\\n\\\\t\\\\t'd22, 'd29: add_2_in_2 = X[4];\\\\n\\\\t\\\\t'd23, 'd30: add_2_in_2 = X[3];\\\\n\\\\t\\\\tdefault: add_2_in_2 = add_1_out;\\\\n\\\\tendcase\\\\nend\\\\n\\\\nalways@(*) begin\\\\n\\\\tcase(count)\\\\n\\\\t\\\\t'd24, 'd25, 'd26: add_3_in_1 = y_temp[2];\\\\n\\\\t\\\\t'd33, 'd34, 'd35, 'd36, 'd37, 'd38, 'd39: add_3_in_1 = exp_out_buffer;\\\\n\\\\t\\\\tdefault: add_3_in_1 = add_1_out;\\\\n\\\\tendcase\\\\nend\\\\n\\\\nalways@(*) begin\\\\n\\\\tcase(count)\\\\n\\\\t\\\\t'd24, 'd25, 'd26, 'd33, 'd34, 'd35, 'd36, 'd37, 'd38, 'd39: add_3_in_2 = 'b00111111100000000000000000000000;\\\\n\\\\t\\\\tdefault: add_3_in_2 = add_2_out;\\\\n\\\\tendcase\\\\nend\\\\n\\\\n// matrix_out_buffer\\\\nalways@(posedge clk or negedge rst_n) begin\\\\n\\\\tif(!rst_n) begin\\\\n\\\\t\\\\tmatrix_out_buffer[0] <= 0;\\\\n\\\\t\\\\tmatrix_out_buffer[1] <= 0;\\\\n\\\\t\\\\tmatrix_out_buffer[2] <= 0;\\\\n\\\\tend\\\\n\\\\telse begin\\\\n\\\\t\\\\tmatrix_out_buffer[0] <= add_2_out;\\\\n\\\\t\\\\tmatrix_out_buffer[1] <= matrix_out_buffer[0];\\\\n\\\\t\\\\tmatrix_out_buffer[2] <= matrix_out_buffer[1];\\\\n\\\\tend\\\\nend\\\\n\\\\n// add_out_buffer\\\\nalways@(posedge clk or negedge rst_n) begin\\\\n\\\\tif(!rst_n) begin\\\\n\\\\t\\\\tadd_out_buffer[0] <= 0;\\\\n\\\\t\\\\tadd_out_buffer[1] <= 0;\\\\n\\\\t\\\\tadd_out_buffer[2] <= 0;\\\\n\\\\tend\\\\n\\\\telse begin\\\\n\\\\t\\\\tadd_out_buffer[0] <= add_3_out;\\\\n\\\\t\\\\tadd_out_buffer[1] <= add_out_buffer[0];\\\\n\\\\t\\\\tadd_out_buffer[2] <= add_out_buffer[1];\\\\n\\\\tend\\\\nend\\\\n\\\\n// leaky relu out\\\\nalways@(*) begin\\\\n\\\\tif(add_out_buffer[0][31] == 'd1) begin\\\\n\\\\t\\\\tleaky_relu_out[0] = mult_3_out;\\\\n\\\\tend\\\\n\\\\telse begin\\\\n\\\\t\\\\tleaky_relu_out[0] = add_out_buffer[0];\\\\n\\\\tend\\\\nend\\\\n\\\\nalways@(*) begin\\\\n\\\\tif(add_out_buffer[1][31] == 'd1) begin\\\\n\\\\t\\\\tleaky_relu_out[1] = mult_2_out;\\\\n\\\\tend\\\\n\\\\telse begin\\\\n\\\\t\\\\tleaky_relu_out[1] = add_out_buffer[1];\\\\n\\\\tend\\\\nend\\\\n\\\\nalways@(*) begin\\\\n\\\\tif(add_out_buffer[2][31] == 'd1) begin\\\\n\\\\t\\\\tleaky_relu_out[2] = mult_1_out;\\\\n\\\\tend\\\\n\\\\telse begin\\\\n\\\\t\\\\tleaky_relu_out[2] = add_out_buffer[2];\\\\n\\\\tend\\\\nend\\\\n\\\\n// y temp\\\\nalways@(posedge clk or negedge rst_n) begin\\\\n\\\\tif(!rst_n) begin\\\\n\\\\t\\\\ty_temp[2] <= 0;\\\\n\\\\t\\\\ty_temp[1] <= 0;\\\\n\\\\t\\\\ty_temp[0] <= 0;\\\\n\\\\tend\\\\n\\\\telse begin\\\\n\\\\t\\\\tcase(count)\\\\n\\\\t\\\\t'd19, 'd20, 'd21: begin\\\\n\\\\t\\\\t\\\\ty_temp[2] <= y_temp[1];\\\\n\\\\t\\\\t\\\\ty_temp[1] <= y_temp[0];\\\\n\\\\t\\\\t\\\\ty_temp[0] <= exp_out;\\\\n\\\\t\\\\tend\\\\n\\\\t\\\\t'd24, 'd25, 'd26, 'd27, 'd34, 'd36, 'd37, 'd38, 'd39, 'd40: begin\\\\n\\\\t\\\\t\\\\ty_temp[2] <= y_temp[1];\\\\n\\\\t\\\\t\\\\ty_temp[1] <= y_temp[0];\\\\n\\\\t\\\\t\\\\ty_temp[0] <= recip_out;\\\\n\\\\t\\\\tend\\\\n\\\\t\\\\tdefault: begin\\\\n\\\\t\\\\t\\\\ty_temp[2] <= y_temp[2];\\\\n\\\\t\\\\t\\\\ty_temp[1] <= y_temp[1];\\\\n\\\\t\\\\t\\\\ty_temp[0] <= y_temp[0];\\\\n\\\\t\\\\tend\\\\n\\\\t\\\\tendcase\\\\n\\\\tend\\\\nend\\\\n\\\\n// exp in control\\\\nassign exp_in = {~matrix_out_buffer[0][31],matrix_out_buffer[0][30:0]};\\\\n\\\\n// exp out buffer\\\\nalways@(posedge clk or negedge rst_n) begin\\\\n\\\\tif(!rst_n)\\\\n\\\\t\\\\texp_out_buffer <= 0;\\\\n\\\\telse begin\\\\n\\\\t\\\\texp_out_buffer <= exp_out;\\\\n\\\\tend\\\\nend\\\\n\\\\n\\\\n//---------------------------------------------------------------------\\\\n// OUTPUT\\\\n//---------------------------------------------------------------------\\\\nalways@(*) begin\\\\n\\\\tcase(count)\\\\n\\\\t'd33: next_output = y_temp[2];\\\\n\\\\t'd34: next_output = y_temp[1];\\\\n\\\\t'd35: next_output = y_temp[1];\\\\n\\\\t'd36: next_output = y_temp[0];\\\\n\\\\t'd37: next_output = y_temp[0];\\\\n\\\\t'd38: next_output = y_temp[0];\\\\n\\\\t'd39: next_output = y_temp[0];\\\\n\\\\t'd40: next_output = y_temp[0];\\\\n\\\\t'd41: next_output = y_temp[0];\\\\n\\\\tdefault: next_output = 'd0;\\\\n\\\\tendcase\\\\nend\\\\n\\\\nalways@(*) begin\\\\n\\\\tcase(count)\\\\n\\\\t'd33, 'd34, 'd35, 'd36, 'd37, 'd38, 'd39, 'd40, 'd41: next_outvalid = 'd1;\\\\n\\\\tdefault: next_outvalid = 'd0;\\\\n\\\\tendcase\\\\nend\\\\n\\\\nalways @(posedge clk or negedge rst_n) begin\\\\n if(!rst_n)begin\\\\n\\\\t\\\\tout_valid <= 0;\\\\n end \\\\n else begin\\\\n\\\\t\\\\tout_valid <= next_outvalid;\\\\n\\\\tend\\\\nend\\\\n\\\\nalways @(posedge clk or negedge rst_n) begin\\\\n if(!rst_n)begin\\\\n out <= 0;\\\\n end \\\\n else begin\\\\n\\\\t\\\\tout <= next_output;\\\\n\\\\tend\\\\nend\\\\n\\\\nendmodule", "module fp_mult(\\\\n\\\\ta,\\\\n\\\\tb,\\\\n\\\\tout\\\\n);\\\\n// IEEE floating point paramenters\\\\nparameter inst_sig_width = 23;\\\\nparameter inst_exp_width = 8;\\\\nparameter inst_ieee_compliance = 0;\\\\nparameter inst_arch = 2;\\\\n\\\\ninput [inst_sig_width+inst_exp_width:0] a, b;\\\\noutput [inst_sig_width+inst_exp_width:0] out;\\\\n\\\\nDW_fp_mult #(inst_sig_width, inst_exp_width, inst_ieee_compliance) M1(.a(a), .b(b), .rnd(3'b000), .z(out));\\\\n\\\\n// synopsys dc_script_begin\\\\n// set_implementation rtl M1\\\\n// synopsys dc_script_end\\\\n\\\\nendmodule", "module fp_add(\\\\n\\\\ta,\\\\n\\\\tb,\\\\n\\\\tout\\\\n);\\\\n// IEEE floating point paramenters\\\\nparameter inst_sig_width = 23;\\\\nparameter inst_exp_width = 8;\\\\nparameter inst_ieee_compliance = 0;\\\\n\\\\ninput [inst_sig_width+inst_exp_width:0] a, b;\\\\noutput [inst_sig_width+inst_exp_width:0] out;\\\\n\\\\nDW_fp_add #(inst_sig_width, inst_exp_width, inst_ieee_compliance) A1(.a(a), .b(b), .rnd(3'b000), .z(out));\\\\n\\\\n// synopsys dc_script_begin\\\\n// set_implementation rtl A1\\\\n// synopsys dc_script_end\\\\n\\\\nendmodule", 'module fp_exp(\\\\n\\\\ta,\\\\n\\\\tout\\\\n);\\\\n// IEEE floating point paramenters\\\\nparameter inst_sig_width = 23;\\\\nparameter inst_exp_width = 8;\\\\nparameter inst_ieee_compliance = 0;\\\\nparameter inst_arch = 2;\\\\n\\\\ninput [inst_sig_width+inst_exp_width:0] a;\\\\noutput [inst_sig_width+inst_exp_width:0] out;\\\\n\\\\nDW_fp_exp #(inst_sig_width, inst_exp_width, inst_ieee_compliance, inst_arch) E1(.a(a), .z(out));\\\\n\\\\n// synopsys dc_script_begin\\\\n// set_implementation rtl E1\\\\n// synopsys dc_script_end\\\\n\\\\nendmodule', "module fp_recip(\\\\n\\\\ta,\\\\n\\\\tout\\\\n);\\\\n// IEEE floating point paramenters\\\\nparameter inst_sig_width = 23;\\\\nparameter inst_exp_width = 8;\\\\nparameter inst_ieee_compliance = 0;\\\\n\\\\ninput [inst_sig_width+inst_exp_width:0] a;\\\\noutput [inst_sig_width+inst_exp_width:0] out;\\\\n\\\\nDW_fp_recip #(inst_sig_width, inst_exp_width, inst_ieee_compliance) R1(.a(a), .rnd(3'b000), .z(out));\\\\n\\\\n// synopsys dc_script_begin\\\\n// set_implementation rtl R1\\\\n// synopsys dc_script_end\\\\n\\\\nendmodule"]
["module Divider(A, B, Out);\\\\n\\\\ninput [31:0] A, B;\\\\noutput [63:0] Out;\\\\n\\\\nwire ALB, AEB, AGB;\\\\nwire [31:0] A_Tmp, A_In, B_In, Preset;\\\\n\\\\nDividerController DIV_CRTL(.Reset(Reset));\\\\n\\\\nClock_Enable CLOCK_EN(.Clk(ClkEn));\\\\n\\\\n// It plays a role in setting Preset in the initialization step.\\\\nMux2to1_32bit SET_PRESET(.I0(32'H00000000), .I1(A), .Sel(Reset), .Out(Preset));\\\\n\\\\n// 95ns\\\\n// It can only be stored in Reg if it is not A<B.\\\\nAND2_1bit REG_ENABLE(.A(ClkEn), .B(Enable), .Out(RegEn));\\\\nRegister_32bit_with_Preset REG(.Clk(ClkEn), .En(RegEn), .Reset(Reset), .Preset(Preset), .In(A_Tmp), .Out(Out[31:0]));\\\\n\\\\n// 205ns\\\\n// It is a comparator that compares A and B.\\\\nComparator_32bit COMP(.A(Out[31:0]), .B(B), .ALB(ALB), .AEB(AEB), .AGB(AGB));\\\\n\\\\nNOT_1bit ENABLE(.A(ALB), .Out(Enable));\\\\n\\\\n// 90ns\\\\n// Subtract when A is greater than B; otherwise, 0 enters the subtractor and computes.\\\\nMux2to1_32bit MUX_A(.I0(32'H00000000), .I1(Out[31:0]), .Sel(Enable), .Out(A_In));\\\\nMux2to1_32bit MUX_B(.I0(32'H00000000), .I1(B), .Sel(Enable), .Out(B_In));\\\\nAdderAndSubtractor_32bit SUB(.A(A_In), .B(B_In), .Cin(Enable), .Out(A_Tmp));\\\\n\\\\n// Once subtracted, the counter value increases once.\\\\nDividerCounter DC(.Clk(ClkEn), .En(Enable), .Reset(Reset), .Out(Out[63:32]));\\\\n\\\\nendmodule", "module TB_Divider();\\\\n\\\\nreg [31:0] A, B;\\\\nwire [63:0] Out;\\\\n\\\\nDivider DIV(.A(A), .B(B), .Out(Out));\\\\n\\\\ninitial begin\\\\n\\\\tA = 32'H00054123;\\\\n\\\\tB = 32'H0000547B;\\\\nend\\\\nendmodule"]
["module FFT_8point_16bit(\\\\n input [15:0] x0,x1,x2,x3,x4,x5,x6,x7,\\\\n\\\\t input en,clk,rst,\\\\n output [15:0] r7,r6,r5,r4,r3,r2,r1,r0,i7,i6,i5,i4,i3,i2,i1,i0);\\\\n\\\\t wire [15:0] w[7:0]; //stage 1 outputs\\\\n\\\\t wor [15:0] r [7:0]; //stage 2 real outputs\\\\n\\\\t wor [15:0] i [7:0]; //stage 2 imag outputs\\\\n\\\\t wire [15:0] t1,t2,t3,t4; //complex multiplier outputs\\\\n\\\\t wire [15:0] re[7:0]; //stage 2 before delay\\\\n\\\\t wire [15:0] im[7:0]; //stage 2 before delay\\\\n\\\\t \\\\n\\\\t assign r[6]=16'b0;\\\\n\\\\t assign i0=16'b0;\\\\n\\\\t assign i4=16'b0;\\\\n\\\\t \\\\n\\\\t//STAGE 1\\\\n\\\\tbutterfly1_FFT BF1(x0,x4,en,clk,rst,1'b0,w[0],w[1]);\\\\n\\\\tbutterfly1_FFT BF2(x6,x2,en,clk,rst,1'b0,w[2],w[3]);\\\\n\\\\tbutterfly1_FFT BF3(x1,x5,en,clk,rst,1'b0,w[4],w[5]);\\\\n\\\\tbutterfly1_FFT BF4(x7,x3,en,clk,rst,1'b0,w[6],w[7]);\\\\n\\\\t\\\\n\\\\t//STAGE 2\\\\n\\\\tbutterfly1_FFT BF5(w[0],w[2],en,clk,rst,1'b0,re[0],re[2]);\\\\n\\\\tbutterfly2_FFT BF6(w[1],w[3],en,clk,rst,re[1],im[1],re[3],im[3]);\\\\n\\\\tbutterfly1_FFT BF7(w[4],w[6],en,clk,rst,1'b0,re[4],im[6]);\\\\n\\\\tdelay_16bit_4unit D1(re[0],en,clk,rst,r[0]); //4 units delay to synchronize stage 2 outputs with output of complex multipliers\\\\n\\\\tdelay_16bit_4unit D2(re[2],en,clk,rst,r[2]);\\\\n\\\\tdelay_16bit_4unit D3(re[1],en,clk,rst,r[1]);\\\\n\\\\tdelay_16bit_4unit D4(re[3],en,clk,rst,r[3]);\\\\n\\\\tdelay_16bit_4unit D5(re[4],en,clk,rst,r[4]);\\\\n\\\\tdelay_16bit_4unit D6(im[1],en,clk,rst,i[1]);\\\\n\\\\tdelay_16bit_4unit D7(im[3],en,clk,rst,i[3]);\\\\n\\\\tdelay_16bit_4unit D8(im[6],en,clk,rst,i[6]);\\\\n\\\\tbutterfly2_FFT BF8(w[5],w[7],en,clk,rst,t1,t2,t3,t4);\\\\n\\\\tcomplex_multiplier_FFT C1(t1,t2,en,clk,rst,1'b0,r[5],i[5]);\\\\n\\\\tcomplex_multiplier_FFT C2(t3,t4,en,clk,rst,1'b1,i[7],r[7]);\\\\n\\\\t\\\\n\\\\t//stage 3 - real parts\\\\n\\\\tbutterfly1_FFT BF9(r[0],r[4],en,clk,rst,1'b0,r0,r4);\\\\n\\\\tbutterfly1_FFT BF10(r[1],r[5],en,clk,rst,1'b0,r1,r5);\\\\n\\\\tbutterfly1_FFT BF11(r[2],r[6],en,clk,rst,1'b0,r2,r6);\\\\n\\\\tbutterfly1_FFT BF12(i[7],i[3],en,clk,rst,1'b1,r3,r7);\\\\n\\\\t//stage 3 - imag parts\\\\n\\\\tassign i[2]=16'b0;\\\\n\\\\tbutterfly1_FFT BF13(i[1],i[5],en,clk,rst,1'b0,i1,i5);\\\\n\\\\tbutterfly1_FFT BF14(i[2],i[6],en,clk,rst,1'b0,i6,i2);\\\\n\\\\tbutterfly1_FFT BF15(r[7],r[3],en,clk,rst,1'b1,i3,i7);\\\\n\\\\t\\\\nendmodule"]
["module tpu_structural (\\\\n\\\\treset, clk, out_HL,error, input1, input2, out\\\\n\\\\t);\\\\n\\\\n\\\\tinput wire reset, clk, out_HL;\\\\n\\\\tinput wire [7:0] input1;\\\\n\\\\tinput wire [7:0] input2;\\\\n\\\\n\\\\toutput wire error;\\\\n\\\\toutput wire [16:0] out;\\\\n\\\\n\\\\twire [33:0] accumulate;\\\\n\\\\twire [33:0] accumulate_wire;\\\\n\\\\twire [33:0] accumulate_wire_final;\\\\n\\\\n\\\\twire [33:0] product_regular;\\\\n\\\\twire [33:0] product_tcomp;\\\\n\\\\twire [7:0] \\\\tmult_output;\\\\n\\\\n\\\\twire [4:0] \\\\texponent;\\\\n\\\\twire [4:0] \\\\texp_mod1;\\\\n\\\\twire [4:0] \\\\texp_mod2;\\\\n\\\\n\\\\twire sign;\\\\n\\\\n\\\\twire t1_1, t2_1, norm_1;\\\\n\\\\twire t1_2, t2_2, norm_2;\\\\n\\\\n\\\\t/* Calculate sign and exponent */\\\\n\\\\txor\\\\t\\\\t\\\\tx1(sign, input1[7], input2[7]);\\\\n\\\\tadd4b\\\\t\\\\ta1(exponent, input1[6:3], input2[6:3], 0);\\\\n\\\\n\\\\t/* Get normalized vs. denormanlized for each input */\\\\n\\\\tor \\\\t\\\\t\\\\to1(t1_1, input1[3], input1[4]);\\\\n\\\\tor \\\\t\\\\t\\\\to2(t2_1, input1[5], input1[6]);\\\\n\\\\tor \\\\t\\\\t\\\\to3(norm_1, t2_1, t1_1);\\\\n\\\\tor \\\\t\\\\t\\\\to4(t1_2, input2[3], input2[4]);\\\\n\\\\tor \\\\t\\\\t\\\\to5(t2_2, input2[5], input2[6]);\\\\n\\\\tor \\\\t\\\\t\\\\to6(norm_2, t2_2, t1_2);\\\\n\\\\n\\\\t/* Calculate ~mult_output~ */\\\\n\\\\tmult4b\\\\t\\\\tm1(mult_output, {norm_1, input1[2:0]}, {norm_2, input2[2:0]});\\\\n\\\\n\\\\t/* Adjust exponent */\\\\n\\\\tsub4b\\\\t\\\\tz1(exp_mod1, exponent, norm_1);\\\\n\\\\tsub4b\\\\t\\\\tz2(exp_mod2, exp_mod1, norm_2);\\\\n\\\\n\\\\t/* Shift input correctly */\\\\n\\\\tshifter\\\\t\\\\ts1(product_regular, error, mult_output, exp_mod2);\\\\n\\\\n\\\\t/* Get the twos complement of the product*/\\\\n\\\\txor34b\\\\t\\\\tx2(product_tcomp, product_regular, sign);\\\\n\\\\n\\\\t/* Add the accumulate and the product */\\\\n\\\\tadd34b\\\\t\\\\ta2(accumulate_wire, accumulate, product_tcomp, sign); // sign is cin\\\\n\\\\n\\\\t/* Either 0 or accumulate wire goes to accumulate*/\\\\n\\\\tmux2_34b \\\\tm2(accumulate_wire_final, accumulate_wire, 34'b0, reset);\\\\n\\\\n\\\\t/* Only change on posedge */\\\\n\\\\td_flip_flop34b\\\\td1(accumulate, clk, accumulate_wire_final);\\\\n\\\\t//always @(posedge clk) begin\\\\n\\\\t//\\\\taccumulate = accumulate_wire_final;\\\\n\\\\t//end\\\\n\\\\n\\\\t/* See which bits to select */\\\\n\\\\tmux2_17b\\\\tm3(out, accumulate[16:0], accumulate[33:17], out_HL);\\\\n\\\\nendmodule"]
["module array_multiplier(\\\\ninput [3:0] A,\\\\ninput [3:0] B,\\\\noutput [7:0] product\\\\n);\\\\n\\\\n//For B0\\\\nwire [3:0] inp0_0, inp0_1;\\\\nwire [3:0] inp1_0, inp1_1, inp2_0, inp2_1;\\\\n\\\\nwire [3:0] S0;\\\\nwire [3:0] S1;\\\\nwire [3:0] S2;\\\\n\\\\nwire c0, c1, c2;\\\\n\\\\nassign inp0_0 = {1'b0, (B[0] & A[3]), (B[0] & A[2]), (B[0] & A[1])}; \\\\nassign inp0_1 = {(B[1] & A[3]), (B[1] & A[2]), (B[1] & A[1]), (B[1] & A[0])};\\\\n\\\\nassign inp1_0 = {c0, S0[3], S0[2], S0[1]};\\\\nassign inp1_1 = {(B[2] & A[3]), (B[2] & A[2]), (B[2] & A[1]), (B[2] & A[0])};\\\\n\\\\nassign inp2_0 = {c1, S1[3], S1[2], S1[1]};\\\\nassign inp2_1 = {(B[3] & A[3]), (B[3] & A[2]), (B[3] & A[1]), (B[3] & A[0])};\\\\n\\\\nripple_carry_add_4bit rca1(inp0_0, inp0_1, 1'b0, S0, c0);\\\\nripple_carry_add_4bit rca2(inp1_0, inp1_1, 1'b0, S1, c1);\\\\nripple_carry_add_4bit rca3(inp2_0, inp2_1, 1'b0, S2, c2);\\\\n\\\\nassign product[0] = A[0] & B[0];\\\\nassign product[1] = S0[0];\\\\nassign product[2] = S1[0];\\\\nassign product[3] = S2[0];\\\\nassign product[4] = S2[1];\\\\nassign product[5] = S2[2];\\\\nassign product[6] = S2[3];\\\\nassign product[7] = c2;\\\\n\\\\nendmodule"]
["module////////////////////////\\\\n///////////////////////////////////////////////////////// \\\\nmodule Subtractor(\\\\n input [15:0] SW,\\\\n input Center,\\\\n output [7:0] AN,\\\\n output [6:0] a_to_g,\\\\n output [3:0] LED,\\\\n input CLK100MHZ\\\\n //output [15:0] A, //testbench only\\\\n //output [15:0] B, //testbench only\\\\n //output [26:0] binary //testbench only\\\\n);\\\\nparameter width1 = 100000000;\\\\nparameter width2 = 10000; \\\\nwire Clk_Slow, Clk_Multi, Clk_Slower;\\\\nwire [7:0]ANhold;\\\\nwire [6:0]a_to_gohold;\\\\nwire clk = CLK100MHZ;\\\\nreg [26:0] binary;\\\\n///BCD into decimal places\\\\nwire [3:0] ones, tens, hundreds, thousand1, thousand10, thousand100, million, million10;\\\\nwire [6:0] _ones, _tens, _hundreds, _thousand1, _thousand10, _thousand100, _million, _million10;\\\\nwire [55:0] disarray;\\\\nreg [15:0] A,B; //reenable\\\\nreg [3:0] led;\\\\nreg [1:0] Sel;\\\\n\\\\ninteger x;\\\\nwire [26:0] addition_total;\\\\nwire [26:0] subtraction_total;\\\\nwire [15:0] shift_total;\\\\n\\\\ninitial begin\\\\n//A = 16'b0101001100100011; //21283\\\\n//B = 16'b0001000011011000; //4312\\\\nA = 0; //testbenchonly\\\\nB = 0; //testbenchonly\\\\nbinary = 0;\\\\nABSRes = 2'b00;\\\\nend\\\\nreg [1:0] ABSRes;\\\\nalways @ (posedge Clk_Slow) begin\\\\ncase (ABSRes)\\\\n2'b00: begin if (Center) begin Sel[1:0] = SW[1:0]; end ABSRes = 2'b01; end\\\\n2'b01: begin if (Center) begin A[15:0] = SW[15:0]; end ABSRes = 2'b10; end\\\\n2'b10: begin if (Center) begin B[15:0] = SW[15:0]; end ABSRes = 2'b11; end\\\\n2'b11: begin if (Center) begin Sel[1:0] = 0; A[15:0] = 0; B[15:0] = 0; end ABSRes = 2'b00; end\\\\nendcase\\\\nend\\\\n\\\\nalways @ (Sel) begin\\\\ncase (Sel)\\\\n2'b00: begin\\\\nbinary = addition_total;\\\\nled [3:0] = 4'b0001;\\\\nend\\\\n2'b01: begin\\\\nbinary = subtraction_total;\\\\nled [3:0] = 4'b0010;\\\\nend\\\\n2'b10: begin\\\\nbinary = A*B;\\\\nled [3:0] = 4'b0100;\\\\nend\\\\n2'b11: begin\\\\nbinary = shift_total;\\\\nled [3:0] = 4'b1000;\\\\nend\\\\ndefault: binary = A+B;\\\\nendcase\\\\nend\\\\n\\\\nAdder_16 add1(A,B,1'b0,addition_total);\\\\nAdder_16 sub1(A,~B+1,1'b0,subtraction_total);\\\\nRight_Shift RS1(A,shift_total);\\\\n\\\\n\\\\n///call BCD to convert calculated # to binary coded decimal\\\\nBCD x1(binary, ones, tens, hundreds, thousand1, thousand10, thousand100, million, million10);\\\\n///call to convert binard coded decimal # to 7 segment code\\\\nconversion c1(ones, _ones); conversion c6(tens, _tens); conversion c2(hundreds, _hundreds); conversion c3(thousand1, _thousand1); conversion c4(thousand10, _thousand10); conversion c5(thousand100, _thousand100);\\\\nconversion c7(million, _million); conversion c8(million10, _million10); \\\\n///combine all 7 segment codes into one array for easier handling\\\\nassign disarray = {_million10,_million,_thousand100,_thousand10,_thousand1,_hundreds,_tens,_ones};\\\\n\\\\nassign LED = led;\\\\nassign AN = ANhold;\\\\nassign a_to_g = a_to_gohold;\\\\n\\\\n//call to display module that multiplexes each digit changed with slower clock signal\\\\ndisplay z1(Clk_Multi, disarray, a_to_gohold, ANhold);\\\\n\\\\n//call to clock slow down module for multiplexed display clk pulse\\\\nClk_Divide # (width1,width2) In1 (CLK100MHZ, Clk_Slow, Clk_Multi);\\\\n\\\\nendmodule", "module to take array of 7seg coded array, multiplex using slow clock, and display on 7segment displays/////////////////\\\\n//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////\\\\nmodule display(input Clk_multi,\\\\ninput [55:0] disarray,\\\\noutput reg [6:0] a_to_g,\\\\noutput reg [7:0] cathode\\\\n);\\\\nreg [3:0]count;\\\\n\\\\nalways @ (posedge Clk_multi) begin\\\\ncase (count)\\\\n\\\\n4'b0000: begin\\\\na_to_g = disarray [6:0];\\\\ncathode = 8'b11111110;\\\\ncount = count + 1;\\\\nend\\\\n\\\\n4'b0001: begin\\\\na_to_g = disarray [13:7];\\\\ncathode = 8'b11111101;\\\\ncount = count + 1;\\\\nend\\\\n\\\\n4'b0010: begin\\\\na_to_g = disarray [20:14];\\\\ncathode = 8'b11111011;\\\\ncount = count + 1;\\\\nend\\\\n\\\\n4'b0011: begin\\\\na_to_g = disarray [27:21];\\\\ncathode = 8'b11110111;\\\\ncount = count + 1;\\\\nend\\\\n\\\\n4'b0100: begin\\\\na_to_g = disarray [34:28];\\\\ncathode = 8'b11101111;\\\\ncount = count + 1;\\\\nend\\\\n\\\\n4'b0101: begin\\\\na_to_g = disarray [41:35];\\\\ncathode = 8'b11011111;\\\\ncount = count + 1;\\\\nend\\\\n\\\\n4'b0110: begin\\\\na_to_g = disarray [48:42];\\\\ncathode = 8'b10111111;\\\\ncount = count + 1;\\\\nend\\\\n\\\\n4'b0111: begin\\\\na_to_g = disarray [55:49];\\\\ncathode = 8'b01111111;\\\\ncount = count + 1;\\\\nend\\\\n\\\\ndefault: count = 4'b0000;\\\\nendcase\\\\nend\\\\n\\\\nendmodule", "module BCD(\\\\ninput [26:0] binary,\\\\noutput reg [3:0] ones,\\\\noutput reg [3:0] tens,\\\\noutput reg [3:0] hundreds,\\\\noutput reg [3:0] thousand1,\\\\noutput reg [3:0] thousand10,\\\\noutput reg [3:0] thousand100,\\\\noutput reg [3:0] million,\\\\noutput reg [3:0] million10\\\\n);\\\\n\\\\ninteger i;\\\\n\\\\nalways @ (binary) begin\\\\n\\\\nones = 4'b0000; tens = 4'b0000; hundreds = 4'b0000; thousand1 = 4'b0000; thousand10 = 4'b0000; thousand100 = 4'b0000; million = 4'b0000; million10 = 4'b0000;\\\\n\\\\nfor (i=26;i>=0;i=i-1) begin\\\\nif (million10 >= 4'b0101)\\\\n million10 = million10 + 3;\\\\nif (million >= 4'b0101)\\\\n million = million + 3;\\\\nif (thousand100 >= 4'b0101)\\\\n thousand100 = thousand100 + 3;\\\\nif (thousand10 >= 4'b0101)\\\\n thousand10 = thousand10 + 3;\\\\nif (thousand1 >= 4'b0101)\\\\n thousand1 = thousand1 + 3;\\\\nif (hundreds >= 4'b0101)\\\\n hundreds = hundreds + 3;\\\\nif (tens >= 4'b0101)\\\\n tens = tens + 3;\\\\nif (ones >= 4'b0101)\\\\n ones = ones + 3;\\\\n\\\\nmillion10 = million10 << 1;\\\\nmillion10[0] = million[3];\\\\n\\\\nmillion = million << 1;\\\\nmillion[0] = thousand100[3];\\\\n\\\\nthousand100 = thousand100 << 1;\\\\nthousand100[0] = thousand10[3];\\\\n\\\\nthousand10 = thousand10 << 1;\\\\nthousand10[0] = thousand1[3];\\\\n\\\\nthousand1 = thousand1 << 1;\\\\nthousand1[0] = hundreds[3];\\\\n\\\\nhundreds = hundreds << 1;\\\\nhundreds[0] = tens[3];\\\\n\\\\ntens = tens << 1;\\\\ntens[0] = ones[3];\\\\n\\\\nones = ones << 1;\\\\nones[0] = binary[i];\\\\nend\\\\n//this section gets rid of leading zeros\\\\nif (million10 == 4'b0000) begin million10 = 4'b1111;\\\\n if (million == 4'b0000) begin million = 4'b1111;\\\\n if (thousand100 == 4'b0000) begin thousand100 = 4'b1111;\\\\n if (thousand10 == 4'b0000) begin thousand10 = 4'b1111;\\\\n if (thousand1 == 4'b0000) begin thousand1 = 4'b1111;\\\\n if (hundreds == 4'b0000) begin hundreds = 4'b1111;\\\\n if (tens == 4'b0000) begin tens = 4'b1111;\\\\n if (ones == 4'b0000) begin ones = 4'b1111;\\\\nend\\\\n end\\\\n end\\\\n end\\\\n end\\\\n end\\\\n end\\\\n end\\\\nend\\\\nendmodule", "module conversion(\\\\n input [3:0]number,\\\\n output reg [6:0]led\\\\n ); \\\\n \\\\n always @(number[3:0]) begin\\\\n case (number[3:0])\\\\n 4'b0000: led = ~(7'b0111111);\\\\n 4'b0001: led = ~(7'b0000110);\\\\n 4'b0010: led = ~(7'b1011011);\\\\n 4'b0011: led = ~(7'b1001111);\\\\n 4'b0100: led = ~(7'b1100110);\\\\n 4'b0101: led = ~(7'b1101101);\\\\n 4'b0110: led = ~(7'b1111101);\\\\n 4'b0111: led = ~(7'b0000111);\\\\n 4'b1000: led = ~(7'b1111111);\\\\n 4'b1001: led = ~(7'b1101111);\\\\n 4'b1111: led = ~(7'b0000000);\\\\n endcase\\\\n end \\\\n \\\\nendmodule", "module to create slower clock signal for display multiplex///////////\\\\n////////////////////////////////////////////////////////////////////////\\\\nmodule Clk_Divide (Clk, Clk_Slow, Clk_multi,Clk_Slower);\\\\ninput Clk;\\\\noutput Clk_Slow,Clk_multi,Clk_Slower;\\\\nreg Clk_Slow;\\\\nreg Clk_multi;\\\\nreg Clk_Slower;\\\\n\\\\nparameter size1 = 100000000;\\\\nparameter size2 = 10000;\\\\nreg [31:0] counter_out1, counter_out2, counter_out3;\\\\n\\\\tinitial begin\\\\t//Note this will synthesize because we are using an FPGA and not making an IC\\\\n\\\\tcounter_out1<= 32'h00000000;\\\\n\\\\tcounter_out2<= 32'h00000000;\\\\n\\\\tcounter_out3<= 32'h00000000;\\\\n\\\\tClk_Slow <= 1'b0;\\\\n\\\\tClk_multi <= 1'b0;\\\\n Clk_Slower <= 1'b0;\\\\n\\\\tend\\\\nalways @(posedge Clk) begin\\\\n\\\\tcounter_out1<= counter_out1 + 32'h00000016;\\\\n\\\\tcounter_out2<= counter_out2 + 32'h00000001;\\\\n\\\\tcounter_out3<= counter_out3 + 32'h00000002;\\\\n\\\\tif (counter_out1 > size1) begin\\\\n\\\\t\\\\tcounter_out1<= 32'h00000000;\\\\n\\\\t\\\\tClk_Slow <= !Clk_Slow;\\\\n\\\\tend\\\\n if (counter_out2 > size2) begin\\\\n counter_out2<= 32'h00000000;\\\\n Clk_multi <= !Clk_multi;\\\\n end\\\\n if (counter_out3 > size1) begin\\\\n counter_out3<= 32'h00000000;\\\\n Clk_Slower <= !Clk_Slower;\\\\n end\\\\nend\\\\nendmodule", 'module Adder_16 (input [15:0] a, b, input cin,\\\\n output [15:0] sum, output cout);\\\\n wire [16:0] c;\\\\t // carry bits\\\\n assign c[0] = cin;\\\\t// carry input\\\\n assign cout = c[16];\\\\t// carry output\\\\n Full_Adder adder [15:0] (a[15:0], b[15:0], c[15:0], c[16:1], sum[15:0]);\\\\nendmodule', 'module Full_Adder(input a, b, c, output cout, sum);\\\\n wire w1, w2, w3;\\\\n and (w1, a, b);\\\\n xor (w2, a, b);\\\\n and (w3, w2, c);\\\\n xor (sum, w2, c);\\\\n or (cout, w1, w3);\\\\nendmodule', "module Right_Shift(input [15:0] a, output [15:0] c);\\\\nreg [15:0] c_1;\\\\n\\\\nalways @ (a) begin\\\\nc_1 <= a;\\\\nc_1 [0] <= a [1];\\\\nc_1 [1] <= a [2];\\\\nc_1 [2] <= a [3];\\\\nc_1 [3] <= a [4];\\\\nc_1 [4] <= a [5];\\\\nc_1 [5] <= a [6];\\\\nc_1 [6] <= a [7];\\\\nc_1 [7] <= a [8];\\\\nc_1 [8] <= a [9];\\\\nc_1 [9] <= a [10];\\\\nc_1 [10] <= a [11];\\\\nc_1 [11] <= a [12];\\\\nc_1 [12] <= a [13];\\\\nc_1 [13] <= a [14];\\\\nc_1 [14] <= a [15];\\\\nc_1 [15] <= 1'b0; \\\\nend\\\\n\\\\nassign c = c_1;\\\\n\\\\nendmodule"]
["module\\\\n// Project Name: \\\\n// Target Devices: \\\\n// Tool Versions: \\\\n// Description: \\\\n// \\\\n// Dependencies: \\\\n// \\\\n// Revision:\\\\n// Revision 0.01 - File Created\\\\n// Additional Comments:\\\\n// \\\\n//////////////////////////////////////////////////////////////////////////////////\\\\n\\\\n\\\\nmodule led_counter_module(\\\\n input clk,\\\\n input R,\\\\n input CE, //this is set as qsec\\\\n output [3:0] Q\\\\n );\\\\n wire [7:0] D;\\\\n wire [7:0] out;\\\\n wire ce = CE; \\\\n FDRE #(.INIT(1'b1)) Q0_FF (.C(clk), .R(R), .CE(ce), .D(out[6]), .Q(out[0]));\\\\n FDRE #(.INIT(1'b0)) Q1_FF (.C(clk), .R(R), .CE(ce), .D(D[1]), .Q(out[1]));\\\\n FDRE #(.INIT(1'b0)) Q2_FF (.C(clk), .R(R), .CE(ce), .D(D[2]), .Q(out[2]));\\\\n FDRE #(.INIT(1'b0)) Q3_FF (.C(clk), .R(R), .CE(ce), .D(D[3]), .Q(out[3]));\\\\n FDRE #(.INIT(1'b0)) Q4_FF (.C(clk), .R(R), .CE(ce), .D(D[4]), .Q(out[4]));\\\\n FDRE #(.INIT(1'b0)) Q5_FF (.C(clk), .R(R), .CE(ce), .D(D[5]), .Q(out[5]));\\\\n FDRE #(.INIT(1'b0)) Q6_FF (.C(clk), .R(R), .CE(ce), .D(D[6]), .Q(out[6]));\\\\n assign D[0] = out[0] ^ CE;\\\\n assign D[1] = out[1] ^ (CE&out[0]);\\\\n assign D[2] = out[2] ^ (CE&out[0]&out[1]);\\\\n assign D[3] = out[3] ^ (CE&out[0]&out[1]&out[2]);\\\\n assign D[4] = out[4] ^ (CE&out[0]&out[1]&out[2]&out[3]);\\\\n assign D[5] = out[5] ^ (CE&out[0]&out[1]&out[2]&out[3]&out[4]);\\\\n assign D[6] = out[6] ^ (CE&out[0]&out[1]&out[2]&out[3]&out[4]);\\\\n \\\\n assign Q[0] = out[1];\\\\n assign Q[1] = out[2];\\\\n assign Q[2] = out[3];\\\\n assign Q[3] = out[4];\\\\n //assign Q[4] = out[6];\\\\n \\\\nendmodule"]
["module char_r_lut(x, y, out);\\\\n\\\\tinput [7:0] x;\\\\n\\\\tinput [7:0] y;\\\\n\\\\toutput reg [6:0] out;\\\\n\\\\n\\\\talways@(*)\\\\n\\\\tbegin\\\\n\\\\t\\\\tout[6] <= 1'b1;\\\\n\\\\t\\\\tcase({x, y})\\\\n\\\\t\\\\t\\\\t16'h0200: out[5:0] <= 6'b111111;\\\\n\\\\t\\\\t\\\\t16'h0300: out[5:0] <= 6'b111111;\\\\n\\\\t\\\\t\\\\t16'h0400: out[5:0] <= 6'b111111;\\\\n\\\\t\\\\t\\\\t16'h0500: out[5:0] <= 6'b111111;\\\\n\\\\t\\\\t\\\\t16'h0600: out[5:0] <= 6'b111111;\\\\n\\\\t\\\\t\\\\t\\\\n\\\\t\\\\t\\\\t16'h0201: out[5:0] <= 6'b111111;\\\\n\\\\t\\\\t\\\\t16'h0701: out[5:0] <= 6'b111111;\\\\n\\\\t\\\\t\\\\t\\\\n\\\\t\\\\t\\\\t16'h0202: out[5:0] <= 6'b111111;\\\\n\\\\t\\\\t\\\\t16'h0702: out[5:0] <= 6'b111111;\\\\n\\\\n\\\\t\\\\t\\\\t16'h0203: out[5:0] <= 6'b111111;\\\\n\\\\t\\\\t\\\\t16'h0703: out[5:0] <= 6'b111111;\\\\n\\\\t\\\\t\\\\t\\\\n\\\\t\\\\t\\\\t16'h0203: out[5:0] <= 6'b111111;\\\\n\\\\t\\\\t\\\\t16'h0303: out[5:0] <= 6'b111111;\\\\n\\\\t\\\\t\\\\t16'h0403: out[5:0] <= 6'b111111;\\\\n\\\\t\\\\t\\\\t16'h0503: out[5:0] <= 6'b111111;\\\\n\\\\t\\\\t\\\\t16'h0603: out[5:0] <= 6'b111111;\\\\n\\\\t\\\\t\\\\t\\\\n\\\\t\\\\t\\\\t16'h0204: out[5:0] <= 6'b111111;\\\\n\\\\t\\\\t\\\\t16'h0604: out[5:0] <= 6'b111111;\\\\n\\\\t\\\\t\\\\t\\\\n\\\\t\\\\t\\\\t16'h0205: out[5:0] <= 6'b111111;\\\\n\\\\t\\\\t\\\\t16'h0605: out[5:0] <= 6'b111111;\\\\n\\\\t\\\\t\\\\t\\\\n\\\\t\\\\t\\\\t16'h0206: out[5:0] <= 6'b111111;\\\\n\\\\t\\\\t\\\\t16'h0606: out[5:0] <= 6'b111111;\\\\n\\\\n\\\\t\\\\t\\\\t16'h0207: out[5:0] <= 6'b111111;\\\\n\\\\t\\\\t\\\\t16'h0607: out[5:0] <= 6'b111111;\\\\n\\\\t\\\\t\\\\t\\\\n\\\\t\\\\t\\\\t16'h0208: out[5:0] <= 6'b111111;\\\\n\\\\t\\\\t\\\\t16'h0708: out[5:0] <= 6'b111111;\\\\n\\\\t\\\\t\\\\t\\\\n\\\\t\\\\t\\\\t16'h0209: out[5:0] <= 6'b111111;\\\\n\\\\t\\\\t\\\\t16'h0709: out[5:0] <= 6'b111111;\\\\n\\\\t\\\\t\\\\tdefault: out[6] <= 1'b0;\\\\n\\\\t\\\\tendcase\\\\n\\\\tend\\\\nendmodule", 'module char_r(x, y, flush_x, flush_y, colour, enable);\\\\n\\\\tinput [7:0] x;\\\\n\\\\tinput [7:0] y;\\\\n\\\\tinput [7:0] flush_x;\\\\n\\\\tinput [7:0] flush_y;\\\\n\\\\t\\\\n\\\\toutput [5:0] colour;\\\\n\\\\toutput enable;\\\\n\\\\t\\\\n\\\\twire [6:0] lut_out;\\\\n\\\\t\\\\n\\\\tchar_r_lut(flush_x - x, flush_y - y, lut_out);\\\\n\\\\t\\\\n\\\\tassign colour = lut_out[5:0];\\\\n\\\\tassign enable = lut_out[6];\\\\nendmodule']
["module pc_unit (\\\\n input [31:0] reg1_data,\\\\n input [31:0] inst,\\\\n input [31:0] ecall,\\\\n input cmp_in,\\\\n input clk,\\\\n input reset,\\\\n output [31:0] pc,\\\\n output [31:0] pc_4\\\\n);\\\\n\\\\nreg [31:0] pc_reg = 32'b0;\\\\n\\\\nwire [31:0] pcadd4;\\\\nwire [31:0] pc_mux_out;\\\\nwire [31:0] branch_out;\\\\nwire [31:0] jump_out;\\\\nwire [31:0] pc_in;\\\\nwire [1:0] control;\\\\n\\\\nassign pcadd4 = pc_reg + 4;\\\\nassign pc_4 = pcadd4;\\\\nassign pc = pc_reg;\\\\n\\\\n// pc_sel control\\\\npc_sel pc_control (.inst(inst), .control(control));\\\\n// branch\\\\nbrancher branch (.inst(inst), .pc(pc_reg), .pc_4(pcadd4),\\\\n .cmp_in(cmp_in), .addr_out(branch_out)\\\\n);\\\\n// jump\\\\njumper jump_unit (.pc(pc_reg), .inst(inst), .reg1_data(reg1_data), .addr_out(jump_out));\\\\n// pc_sel\\\\nx_bit_mux_4 #(.WIDTH(32)) pc_mux (\\\\n .a(pcadd4), .b(branch_out), .c(jump_out), .d(ecall), .s0(control[0]), .s1(control[1]), .out(pc_mux_out)\\\\n);\\\\n// reset\\\\nx_bit_mux_2 #(.WIDTH(32)) reset_sel (.a(pc_mux_out), .b({32{1'b0}}), .s(reset), .out(pc_in));\\\\n\\\\nalways @ (posedge clk) begin\\\\n pc_reg <= pc_in;\\\\nend\\\\n\\\\nendmodule"]
["module Arpeggiator (\\\\n// Inputs\\\\ninput CLK100MHZ,\\\\ninput BTNC,\\\\ninput [7:0] SW,\\\\n// Outputs\\\\noutput AUD_SD,\\\\noutput AUD_PWM,\\\\noutput [2:0] LED\\\\n);\\\\n\\\\n// BRAM\\\\nwire ena = 1'b1; // Read enable always on\\\\nwire wea = 1'b0; // Write enable always off\\\\nreg [7:0] addra = 0; // Read data address\\\\nwire [10:0] dina = 0; // Write data blank\\\\nwire [10:0] douta; // Read data wire\\\\nBRAM_fullsine BRAM1 (CLK100MHZ, ena, wea, addra, dina, douta); // BRAM IP module instantiation\\\\n\\\\n// PWM Audio\\\\nassign AUD_SD = 1'b1; // Audio PWM amplifier always on\\\\nPWM #(.resolution_bits(11)) audioPWM (CLK100MHZ, douta, AUD_PWM); // PWM module instantiation\\\\n\\\\n// Clock divider for PWM value changing\\\\nreg [11:0] sine_clk_div = 1;\\\\nwire sin_clk;\\\\nClockDivider #(.reg_width(12)) sineClock (CLK100MHZ, sine_clk_div, sin_clk); // Clock divider module instantiation\\\\n\\\\n// Arpeggiator button\\\\nwire btn_arpeg;\\\\nDebounce #(.delay_ms(30)) arpeggiatorButton (CLK100MHZ, BTNC, btn_arpeg); // Button debounce module instantiation\\\\n\\\\n// Mode/state variables\\\\nreg arpeggiatorMode = 0;\\\\nreg [1:0] note;\\\\nreg [25:0] note_cnt;\\\\nreg [11:0] freq_base = 1;\\\\nassign LED[2] = arpeggiatorMode;\\\\nassign LED[1:0] = note;\\\\n\\\\nalways @(posedge CLK100MHZ) begin // CLK100MHZ clock domain\\\\n freq_base <= 746 + SW[7:0]; // Get base frequency\\\\n\\\\n if (~arpeggiatorMode) begin // Base frequency mode\\\\n sine_clk_div <= freq_base;\\\\n note <= 0;\\\\n note_cnt <= 0;\\\\n\\\\n end else begin // Arpeggiator mode\\\\n note_cnt <= (note_cnt >= 50000000)? 0:note_cnt+1;\\\\n note <= (note_cnt >= 50000000)? note+1:note;\\\\n\\\\n case (note)\\\\n 0: begin // Base note\\\\n sine_clk_div <= freq_base;\\\\n end\\\\n 1: begin // 1.25x\\\\n sine_clk_div <= freq_base*4/5;\\\\n end\\\\n 2: begin // 1.5x\\\\n sine_clk_div <= freq_base*2/3;\\\\n end\\\\n 3: begin // 2x\\\\n sine_clk_div <= freq_base*2;\\\\n end\\\\n endcase;\\\\n\\\\n end\\\\nend\\\\n\\\\nalways @(posedge sin_clk) begin // sin_clk clock domain (change PWM value)\\\\n addra <= addra + 1; // Increment BRAM address\\\\nend\\\\n\\\\nalways @(posedge btn_arpeg) begin // Arpeggiator button clock domain (toggle arpeggiator mode)\\\\n arpeggiatorMode <= ~arpeggiatorMode;\\\\nend\\\\n\\\\nendmodule"]
['module ROUND(\\\\n input [31:0] D_IN,\\\\n input [7:0] K_IN,\\\\n output [31:0] D_OUT\\\\n );\\\\n\\\\t\\\\n\\\\twire [39:0] SML_in;\\\\n\\\\twire [31:0] SML_out;\\\\n\\\\tassign SML_in = {K_IN[7],D_IN[31:28],K_IN[6],D_IN[27:24],K_IN[5],D_IN[23:20],K_IN[4],D_IN[19:16],\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t K_IN[3],D_IN[15:12],K_IN[2],D_IN[11: 8],K_IN[1],D_IN[ 7: 4],K_IN[0],D_IN[ 3: 0]};\\\\n\\\\t\\\\n\\\\tSM SM3 (\\\\n .D_IN(SML_in[39:30]), \\\\n .D_OUT(SML_out[31:24])\\\\n );\\\\n\\\\t\\\\n\\\\tSM SM2 (\\\\n .D_IN(SML_in[29:20]), \\\\n .D_OUT(SML_out[23:16])\\\\n );\\\\n\\\\t\\\\n\\\\tSM SM1 (\\\\n .D_IN(SML_in[19:10]), \\\\n .D_OUT(SML_out[15:8])\\\\n );\\\\n\\\\t\\\\n\\\\tSM SM0 (\\\\n .D_IN(SML_in[9:0]), \\\\n .D_OUT(SML_out[7:0])\\\\n );\\\\n\\\\t \\\\n\\\\tPERM8 PERM8 (\\\\n .D_IN(SML_out), \\\\n .D_OUT(D_OUT)\\\\n );\\\\nendmodule']
["module ADC_INT_TrigUPDOWN(clk,rst,dpwm_angle,dpwm_s,updateo);\\\\n\\\\n// dpwm_duty must be fed in at positive clock edge so it is stable at negative clock edge\\\\n// reset signal must be inserted at negative clock edge so the ramp initial values are loaded properly\\\\n\\\\ninput clk;\\\\ninput rst;\\\\ninput unsigned [10:0] dpwm_angle;\\\\noutput dpwm_s;\\\\noutput updateo;\\\\nwire unsigned dpwm_s_temp;\\\\nwire unsigned [10:0] ramp_ref;\\\\nreg unsigned adc; \\\\nreg unsigned [3:0] counter;\\\\nreg unsigned adcout; \\\\nreg [2:0] dpwm_s_tempr;\\\\nreg update;\\\\nalways @ (posedge clk) dpwm_s_tempr <= {dpwm_s_tempr[1:0],dpwm_s_temp}; \\\\nwire dpwm_s_tempre = (dpwm_s_tempr[2:1] == 2'b01);\\\\nwire dpwm_s_tempfe = (dpwm_s_tempr[2:1] == 2'b10);\\\\n// pipe positive edge\\\\nRAMPUPDOWN inst_ramp(\\\\n.clk(clk),\\\\n.rst(rst),\\\\n.dpwm_angle(dpwm_angle),\\\\n.ramp_ref(ramp_ref));\\\\n\\\\n// pipe negative edge\\\\nCOMP inst_compADC(\\\\n.clk(clk),\\\\n.rst(rst),\\\\n.ramp_ref(ramp_ref),\\\\n.dpwm_duty(11'd484), \\\\n.dpwm(dpwm_s_temp));\\\\n//COMP inst_compADC(\\\\n//.clk(clk),\\\\n//.rst(rst),\\\\n//.ramp_ref(ramp_ref),\\\\n//.dpwm_duty(11'd100),\\\\n//.dpwm(dpwm_s_temp));\\\\nalways @ (negedge clk)\\\\nbegin\\\\n\\\\tif(ramp_ref <= 11'd2)\\\\n\\\\tbegin\\\\n\\\\t\\\\tupdate = 1'b1;\\\\n\\\\tend\\\\n\\\\telse\\\\n\\\\t\\\\tupdate = 1'b0;\\\\nend\\\\n//always@(posedge clk)\\\\n//begin\\\\n//\\\\tif(counter < 4'd9)\\\\n//\\\\tbegin\\\\n//\\\\t\\\\tcounter <= counter + (1'b1 & dpwm_s_tempre);\\\\n//\\\\t\\\\tif(dpwm_s_tempfe)\\\\n//\\\\t\\\\t\\\\tadcout <= 0;\\\\n//\\\\tend\\\\n//\\\\telse\\\\n//\\\\tbegin\\\\n//\\\\t\\\\tcounter <= 4'd0;\\\\n//\\\\t\\\\tadcout <= 1;\\\\n//\\\\tend\\\\n//end\\\\n\\\\n// pipe positive edge\\\\n//assign dpwm_s = (adcout & dpwm_s_temp);\\\\nassign dpwm_s = dpwm_s_temp;\\\\nassign updateo = update;\\\\nendmodule"]
['module decode(clock,instruction,opcode,data1,data2,signex,rt,rd);\\\\n\\\\tinput clock;\\\\n\\\\twire writReg=0;\\\\n\\\\twire [31:0]writeData=0;\\\\n\\\\tinput[31:0]instruction;\\\\n\\\\toutput [5:0]opcode;\\\\n\\\\toutput [31:0]data1;\\\\n\\\\toutput [31:0]data2;\\\\n\\\\toutput [31:0]signex;\\\\n\\\\toutput [4:0]rt;\\\\n\\\\toutput [4:0]rd;\\\\n\\\\t\\\\t\\\\t\\\\n\\\\t\\\\tregfile regFile (\\\\n\\\\t\\\\t.clock(clock), \\\\n\\\\t\\\\t.regwrite(regwrite), \\\\n\\\\t\\\\t.readReg1(instruction[25:21]), \\\\n\\\\t\\\\t.readReg2(instruction[20:16]), \\\\n\\\\t\\\\t.writeReg(writeReg), \\\\n\\\\t\\\\t.writeData(instruction[15:11]),\\\\n\\\\t\\\\t.data1(data1),\\\\n\\\\t\\\\t.data2(data2)\\\\n\\\\t);\\\\n\\\\t\\\\tsignEx signextention (\\\\n\\\\t\\\\t.address16(instruction[15:0]), \\\\n\\\\t\\\\t.address32(signex)\\\\n\\\\t);\\\\n\\\\t\\\\n\\\\tassign opcode = instruction[31:26];\\\\n\\\\tassign rt = instruction[20:16];\\\\n\\\\tassign rd = instruction[15:11];\\\\n\\\\nendmodule']
["module controller(clk,rst,start,Asel,Bsel,mult_sel,ans_sel,resultRes);\\\\ninput clk,rst,start;\\\\noutput wire Asel,Bsel,resultRes,mult_sel;\\\\noutput wire[1:0] ans_sel;\\\\n\\\\nwire a,b,c,not_a,not_b,not_c;\\\\nwire Bsel_1,Bsel_2,ans_sel_0_1,ans_sel_0_2;\\\\nwire ns_a,ns_b,ns_c;\\\\nwire ns_a_1,ns_a_2,ns_b_1,ns_b_2,ns_c_1,ns_c_2,ns_c_3;\\\\n\\\\nnot_gate not1(not_a,a);\\\\nnot_gate not2(not_b,b);\\\\nnot_gate not3(not_c,c);\\\\nnot_gate not4(not_Asel,Asel);\\\\nnot_gate not5(not_Bsel,Bsel);\\\\nnot_gate not6(not_resultRes,resultRes);\\\\n\\\\nand_gate_3inputs and1(resultRes,not_a,not_b,c);//result res\\\\n\\\\nand_gate_2inputs and2(Asel,a,not_b);//Asel\\\\n\\\\nand_gate_3inputs and3(Bsel_1,not_a,b,c);\\\\nand_gate_3inputs and4(Bsel_2,a,not_b,c);\\\\nor_gate_2inputs or1(Bsel,Bsel_1,Bsel_2);//Bsel\\\\n\\\\nand_gate_4inputs and_mult(mult_sel,not_Asel,not_Bsel,not_resultRes,not_b);//mult_sel\\\\n\\\\nand_gate_3inputs and5(ans_sel[1],a,not_b,c);//ans_sel[1]\\\\nand_gate_3inputs and6(ans_sel_0_1,not_a,b,c);\\\\nand_gate_3inputs and7(ans_sel_0_2,a,not_b,not_c);\\\\nor_gate_2inputs or2(ans_sel[0],ans_sel_0_1,ans_sel_0_2);//ans_sel[0]\\\\n\\\\nand_gate_3inputs and8(ns_a_1,not_a,b,c);\\\\nand_gate_3inputs and9(ns_a_2,a,not_b,not_c);\\\\nor_gate_2inputs or3(ns_a,ns_a_1,ns_a_2);//A'\\\\n\\\\nand_gate_3inputs and10(ns_b_1,not_a,b,not_c);\\\\nand_gate_3inputs and11(ns_b_2,not_a,not_b,c);\\\\nor_gate_2inputs or4(ns_b,ns_b_1,ns_b_2);//B'\\\\n\\\\nand_gate_3inputs and12(ns_c_1,not_a,b,not_c);\\\\nand_gate_3inputs and13(ns_c_2,not_c,start,not_a);\\\\nand_gate_3inputs and14(ns_c_3,a,not_b,not_c);\\\\nor_gate_3inputs or5(ns_c,ns_c_1,ns_c_2,ns_c_3);//C'\\\\n\\\\nS2 s2_module1({3'b000,ns_a},{2'b00},{2'b00},rst,clk,a);\\\\nS2 s2_module2({3'b000,ns_b},{2'b00},{2'b00},rst,clk,b);\\\\nS2 s2_module3({3'b000,ns_c},{2'b00},{2'b00},rst,clk,c);\\\\n\\\\nendmodule"]
['module TestMIPS;\\\\n\\\\nreg clk;\\\\nreg rst;\\\\n\\\\nwire [31:0] AddressBus, DataBus, ProgramCounter, Instruction, ALUResult;\\\\nwire BusCycle, MemRead;\\\\nwire [3:0] MemWrite;\\\\n\\\\nMIPS mips(\\\\n .clk(!clk),\\\\n .rst(rst),\\\\n .BusCycle(BusCycle),\\\\n .MemWrite(MemWrite),\\\\n .MemRead(MemRead),\\\\n .AddressBus(AddressBus),\\\\n .DataBus(DataBus),\\\\n .ProgramCounter(ProgramCounter),\\\\n .ALUResult(ALUResult),\\\\n .Instruction(Instruction)\\\\n);\\\\n\\\\nwire ram_cs;\\\\n\\\\nOR #(.WIDTH(2))\\\\nram_cs_or\\\\n(\\\\n .in({ |MemWrite, MemRead }),\\\\n\\\\t.out(ram_cs)\\\\n);\\\\n\\\\n/* Instruction Memory */\\\\nROM #(\\\\n .LENGTH(32\\'h1000),\\\\n .WIDTH(32),\\\\n .FILE_NAME(\\\\"CPU_TEST.mem\\\\")\\\\n) rom (\\\\n\\\\t.a({2\\'b00, ProgramCounter[31:2]}),\\\\n\\\\t.out(Instruction)\\\\n);\\\\n/* Data Memory */\\\\n\\\\nRAM_B #(\\\\n .LENGTH(32\\'d255),\\\\n .COLUMN(3),\\\\n .USE_FILE(1),\\\\n .FILE_NAME(\\\\"ram.mem\\\\")\\\\n) ramb_3 (\\\\n .clk(clk),\\\\n .we(MemWrite[3]),\\\\n .cs(ram_cs),\\\\n .oe(MemRead),\\\\n .address(AddressBus[13:2]),\\\\n .data(DataBus[31:24])\\\\n);\\\\n\\\\nRAM_B #(\\\\n .LENGTH(32\\'d255),\\\\n .COLUMN(2),\\\\n .USE_FILE(1),\\\\n .FILE_NAME(\\\\"ram.mem\\\\")\\\\n) ramb_2 (\\\\n .clk(clk),\\\\n .we(MemWrite[2]),\\\\n .cs(ram_cs),\\\\n .oe(MemRead),\\\\n .address(AddressBus[13:2]),\\\\n .data(DataBus[23:16])\\\\n);\\\\n\\\\n RAM_B #(\\\\n .LENGTH(32\\'d255),\\\\n .COLUMN(1),\\\\n .USE_FILE(1),\\\\n .FILE_NAME(\\\\"ram.mem\\\\")\\\\n) ramb_1 (\\\\n .clk(clk),\\\\n .we(MemWrite[1]),\\\\n .cs(ram_cs),\\\\n .oe(MemRead),\\\\n .address(AddressBus[13:2]),\\\\n .data(DataBus[15:8])\\\\n);\\\\n\\\\nRAM_B #(\\\\n .LENGTH(32\\'d255),\\\\n .COLUMN(0),\\\\n .USE_FILE(1),\\\\n .FILE_NAME(\\\\"ram.mem\\\\")\\\\n) ramb_0 (\\\\n .clk(clk),\\\\n .we(MemWrite[0]),\\\\n .cs(ram_cs),\\\\n .oe(MemRead),\\\\n .address(AddressBus[13:2]),\\\\n .data(DataBus[7:0])\\\\n);\\\\n\\\\n// RAM #(\\\\n// .LENGTH(32\\'d255),\\\\n// .WIDTH(32),\\\\n// .USE_FILE(0),\\\\n// .FILE_NAME(\\\\"ram.mem\\\\")\\\\n// ) ram (\\\\n// .clk(clk),\\\\n// .we(|MemWrite),\\\\n// .cs(ram_cs),\\\\n// .oe(MemRead),\\\\n// .address(AddressBus[9:2]),\\\\n// .data(DataBus)\\\\n// );\\\\n\\\\ntask RESET;\\\\nbegin\\\\n rst = 0;\\\\n clk = 0;\\\\n #5\\\\n rst = 1;\\\\n #5\\\\n rst = 0;\\\\n clk = 0;\\\\nend\\\\nendtask;\\\\n\\\\ntask CLOCK;\\\\n\\\\tinput [31:0] count;\\\\n\\\\tinteger k;\\\\nbegin\\\\n\\\\tfor (k=0; k < count; k = k+1)\\\\n\\\\tbegin\\\\n\\\\t\\\\t#5\\\\n\\\\t\\\\tclk = 1;\\\\n\\\\t\\\\t#5\\\\n\\\\t\\\\tclk = 0;\\\\n\\\\tend\\\\nend\\\\nendtask\\\\n\\\\nparameter FULL_CYCLE = 32\\'d60;\\\\n\\\\ninitial begin\\\\n #10\\\\n #10\\\\n\\\\tRESET;\\\\n\\\\tCLOCK(FULL_CYCLE);\\\\n\\\\n #10 $stop;\\\\n #5 $finish;\\\\nend\\\\n\\\\nendmodule']
['module game_mode_test(CLOCK_50,resetn, ps2_key_data, ps2_key_pressed, speed, CounterValue, Note, current_state, aud_en, score, game_str, notes);\\\\n\\\\tinput CLOCK_50,resetn; \\\\n\\\\tinput [7:0]ps2_key_data; \\\\n\\\\tinput ps2_key_pressed;\\\\n\\\\tinput [1:0] speed;\\\\n\\\\twire [7:0]keyPressedCode;\\\\n\\\\toutput [11:0]current_state;\\\\n\\\\toutput aud_en;\\\\n\\\\twire sel_note_en;\\\\n\\\\twire load_str_en;\\\\n\\\\toutput [63:0] notes;\\\\n\\\\twire gameCheckDone;\\\\n\\\\twire EnableDC;\\\\n\\\\twire [30:0]downcount;\\\\n\\\\toutput [63:0]game_str; // to be fed to comparison module\\\\n\\\\twire game_check_en;\\\\n\\\\toutput [3:0]score;\\\\n\\\\twire [3:0]counter;\\\\n\\\\toutput [3:0]CounterValue;\\\\n\\\\toutput [7:0]Note;\\\\n\\\\t\\\\n\\\\n\\\\tcontrolpath p1(CLOCK_50, resetn, ps2_key_data, ps2_key_pressed, keyPressedCode, current_state, aud_en, sel_note_en, notes, gameCheckDone, load_str_en, game_check_en);\\\\n\\\\tRateDivider r1(CLOCK_50, resetn, speed, sel_note_en, EnableDC, downcount);\\\\n\\\\tGameSelectNotes g1(CLOCK_50, resetn, EnableDC, sel_note_en, notes, CounterValue, Note);\\\\n\\\\tload_str l1(CLOCK_50, resetn, load_str_en, ps2_key_data, ps2_key_pressed, game_str, counter);\\\\n\\\\tgame_check_str g2(CLOCK_50, game_check_en, notes, game_str, gameCheckDone, score);\\\\nendmodule', "module RateDivider\\\\n#(parameter CLOCK_FREQUENCY = 50000000) (\\\\ninput ClockIn,\\\\ninput Resetn,\\\\ninput [1:0] Speed,\\\\ninput sel_note_en,\\\\noutput Enable,\\\\noutput reg [30:0] downcount\\\\n);\\\\n always @ (posedge ClockIn)\\\\n begin\\\\n\\\\t if(sel_note_en)\\\\n\\\\t begin\\\\n\\\\tif((!Resetn) || (downcount == 0))\\\\n\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\tif(Speed == 2'b00)\\\\n\\\\t\\\\t\\\\t\\\\tdowncount <= 0;\\\\n\\\\t\\\\t\\\\t\\\\telse if(Speed == 2'b01)\\\\n\\\\t\\\\t\\\\t\\\\tdowncount <= 24999999;\\\\n\\\\t\\\\t\\\\t\\\\telse if(Speed == 2'b10)\\\\n\\\\t\\\\t\\\\t\\\\tdowncount <= CLOCK_FREQUENCY - 1;\\\\n\\\\t\\\\t\\\\t\\\\telse if(Speed == 2'b11)\\\\n\\\\t\\\\t\\\\t\\\\tdowncount <= CLOCK_FREQUENCY * 2 - 1;\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\telse downcount <= downcount - 1;\\\\n\\\\tend\\\\n end\\\\n\\\\tassign Enable = (downcount == 0)?1'b1:1'b0;\\\\nendmodule", "module GameSelectNotes (\\\\ninput Clock,\\\\ninput Resetn,\\\\ninput EnableDC,\\\\ninput selNoteEn,\\\\ninput [63:0] notes,\\\\noutput [3:0] CounterValue,\\\\noutput reg[7:0] Note\\\\n);\\\\n\\\\treg [3:0] counter;\\\\n\\\\t\\\\n\\\\talways @ (posedge Clock)\\\\n\\\\tbegin\\\\n\\\\t if(!Resetn) counter <= 4'b0000;\\\\n if(selNoteEn)\\\\n begin\\\\n if(counter == 4'd8)\\\\n counter <= 4'b0000;\\\\n\\\\t\\\\telse if(EnableDC)\\\\n\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\tcounter <= counter + 1'b1;\\\\n\\\\t\\\\t\\\\tbegin\\\\n \\\\t\\\\tif(counter == 4'd0) Note <= notes[63:56];\\\\n\\\\t\\\\t\\\\telse if(counter == 4'd1) Note <= notes[55:48];\\\\n\\\\t\\\\t\\\\telse if(counter == 4'd2) Note <= notes[47:40];\\\\n\\\\t\\\\t\\\\telse if(counter == 4'd3) Note <= notes[39:32];\\\\n\\\\t\\\\t\\\\telse if(counter == 4'd4) Note <= notes[31:24];\\\\n\\\\t\\\\t\\\\telse if(counter == 4'd5) Note <= notes[23:16];\\\\n\\\\t\\\\t\\\\telse if(counter == 4'd6) Note <= notes[15:8];\\\\n\\\\t\\\\t\\\\telse if(counter == 4'd7) Note <= notes[7:0];\\\\n \\\\tend\\\\n\\\\t\\\\t\\\\tend\\\\n \\\\t\\\\telse counter <= counter;\\\\n end\\\\n end\\\\n\\\\tassign CounterValue = counter;\\\\nendmodule", "module controlpath(CLOCK_50, resetn, ps2_key_data, ps2_key_pressed, keyPressedCode, current_state, aud_en, sel_note_en, notes, gameCheckDone, load_str_en, game_check_en);\\\\n input CLOCK_50, resetn;\\\\n\\\\t\\\\t\\\\t\\\\t// this is a register that stores the CODEWORD for 7 different notes (8 bits each), this traindataset will\\\\n // be fed into an audio output module when in the TR_FIRST_NOTE state and output the audio\\\\n output reg [11:0] current_state;\\\\n reg [11:0] next_state;\\\\n\\\\n input\\\\t\\\\t [7:0] ps2_key_data;\\\\n input\\\\t\\\\t\\\\tps2_key_pressed;\\\\n input gameCheckDone;\\\\n\\\\n\\\\n output reg [7:0] keyPressedCode; //register to store data\\\\n output reg aud_en, sel_note_en, load_str_en, game_check_en;\\\\n output reg [63:0] notes;\\\\n\\\\n\\\\n localparam HOME_SCREEN = 12'd0,\\\\n TRAIN_MODE = 12'd1,\\\\n GAME_MODE = 12'd2,\\\\n TR_FIRST_NOTE = 12'd3,\\\\n TR_LOAD_FIRST_NOTE = 12'd4,\\\\n TR_CHECK_FIRST = 12'd5,\\\\n TR_SECOND_NOTE = 12'd6,\\\\n TR_LOAD_SECOND_NOTE = 12'd7,\\\\n TR_CHECK_SECOND = 12'd8,\\\\n TR_THIRD_NOTE = 12'd9,\\\\n TR_LOAD_THIRD_NOTE = 12'd10,\\\\n TR_CHECK_THIRD = 12'd11,\\\\n TR_FOURTH_NOTE = 12'd12,\\\\n TR_LOAD_FOURTH_NOTE = 12'd13,\\\\n TR_CHECK_FOURTH = 12'd14,\\\\n TR_FIFTH_NOTE = 12'd15,\\\\n TR_LOAD_FIFTH_NOTE = 12'd16,\\\\n TR_CHECK_FIFTH = 12'd17,\\\\n TR_SIXTH_NOTE = 12'd18,\\\\n TR_LOAD_SIXTH_NOTE = 12'd19,\\\\n TR_CHECK_SIXTH = 12'd20,\\\\n TR_SEVENTH_NOTE = 12'd21,\\\\n TR_LOAD_SEVENTH_NOTE = 12'd22,\\\\n TR_CHECK_SEVENTH = 12'd23,\\\\n\\\\n GAME_FIRST_ROUND = 12'd24,\\\\n GAME_LOAD_FIRST_STR = 12'd25,\\\\n GAME_CHECK_FIRST = 12'd26,\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tGAME_SECOND_ROUND = 12'd27,\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tGAME_LOAD_SECOND_STR = 12'd28,\\\\n GAME_CHECK_SECOND = 12'd29,\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tGAME_THIRD_ROUND = 12'd30,\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tGAME_LOAD_THIRD_STR = 12'd31,\\\\n GAME_CHECK_THIRD = 12'd32,\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tGAME_FOURTH_ROUND = 12'd33,\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tGAME_LOAD_FOURTH_STR = 12'd34,\\\\n GAME_CHECK_FOURTH = 12'd35,\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tGAME_FIFTH_ROUND = 12'd36,\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tGAME_LOAD_FIFTH_STR = 12'd37,\\\\n GAME_CHECK_FIFTH = 12'd38;\\\\n\\\\n\\\\n\\\\n \\\\n\\\\n\\\\n\\\\n always @ (*)\\\\n begin: state_table\\\\n case(current_state)\\\\n HOME_SCREEN: \\\\n begin\\\\n if(keyPressedCode == 8'b00101100) next_state = TRAIN_MODE; //key = 2c = T\\\\n else if(keyPressedCode == 8'b00110100) next_state = GAME_MODE; //key = 34 = G\\\\n else next_state = HOME_SCREEN;\\\\n end\\\\n TRAIN_MODE: next_state = (keyPressedCode == 8'b00101001)? TR_FIRST_NOTE : TRAIN_MODE; // key = 29 = space key\\\\n TR_FIRST_NOTE: next_state = TR_LOAD_FIRST_NOTE;\\\\n TR_LOAD_FIRST_NOTE: next_state = (ps2_key_pressed)? TR_CHECK_FIRST: TR_LOAD_FIRST_NOTE;\\\\n TR_CHECK_FIRST: next_state = (keyPressedCode == 8'b00100001)? TR_SECOND_NOTE: TR_FIRST_NOTE; // key = 21 = C\\\\n TR_SECOND_NOTE: next_state = TR_LOAD_SECOND_NOTE;\\\\n TR_LOAD_SECOND_NOTE: next_state = (ps2_key_pressed)? TR_CHECK_SECOND: TR_LOAD_SECOND_NOTE;\\\\n TR_CHECK_SECOND: next_state = (keyPressedCode == 8'b00100011)? TR_THIRD_NOTE: TR_SECOND_NOTE; // key = 23 = D \\\\n TR_THIRD_NOTE: next_state = TR_LOAD_THIRD_NOTE;\\\\n TR_LOAD_THIRD_NOTE: next_state = (ps2_key_pressed)? TR_CHECK_THIRD: TR_LOAD_THIRD_NOTE;\\\\n TR_CHECK_THIRD: next_state = (keyPressedCode == 8'b00100100)? TR_FOURTH_NOTE: TR_THIRD_NOTE; // key = 24 = E\\\\n TR_FOURTH_NOTE: next_state = TR_LOAD_FOURTH_NOTE;\\\\n TR_LOAD_FOURTH_NOTE: next_state = (ps2_key_pressed)? TR_CHECK_FOURTH: TR_LOAD_FOURTH_NOTE;\\\\n TR_CHECK_FOURTH: next_state = (keyPressedCode == 8'b00101011)? TR_FIFTH_NOTE: TR_FOURTH_NOTE; // key = 2B = F\\\\n TR_FIFTH_NOTE: next_state = TR_LOAD_FIFTH_NOTE;\\\\n TR_LOAD_FIFTH_NOTE: next_state = (ps2_key_pressed)? TR_CHECK_FIFTH: TR_LOAD_FIFTH_NOTE;\\\\n TR_CHECK_FIFTH: next_state = (keyPressedCode == 8'b00110100)? TR_SIXTH_NOTE: TR_FIFTH_NOTE; //key = 34 = G\\\\n TR_SIXTH_NOTE: next_state = TR_LOAD_SIXTH_NOTE;\\\\n TR_LOAD_SIXTH_NOTE: next_state = (ps2_key_pressed)? TR_CHECK_SIXTH: TR_LOAD_SIXTH_NOTE;\\\\n TR_CHECK_SIXTH: next_state = (keyPressedCode == 8'b00011100)? TR_SEVENTH_NOTE: TR_SIXTH_NOTE; //key = 1c = A \\\\n TR_SEVENTH_NOTE: next_state = TR_LOAD_SEVENTH_NOTE;\\\\n TR_LOAD_SEVENTH_NOTE: next_state = (ps2_key_pressed)? TR_CHECK_SEVENTH: TR_LOAD_SEVENTH_NOTE;\\\\n TR_CHECK_SEVENTH: next_state = (keyPressedCode == 8'b00110010)? HOME_SCREEN: TR_SEVENTH_NOTE; //key = 32 = B\\\\n GAME_MODE: next_state = (keyPressedCode == 8'b00101001)? GAME_FIRST_ROUND: GAME_MODE;\\\\n GAME_FIRST_ROUND: next_state = GAME_LOAD_FIRST_STR;\\\\n GAME_LOAD_FIRST_STR: next_state = (keyPressedCode == 8'b00110001) ? GAME_CHECK_FIRST: GAME_LOAD_FIRST_STR; // key = 31 = N for next\\\\n GAME_CHECK_FIRST: next_state = (keyPressedCode == 8'b00101001) ? GAME_SECOND_ROUND: GAME_CHECK_FIRST;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t GAME_SECOND_ROUND: next_state = GAME_LOAD_SECOND_STR;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t GAME_LOAD_SECOND_STR: next_state = (keyPressedCode == 8'b00110001) ? GAME_CHECK_SECOND: GAME_LOAD_SECOND_STR;\\\\n GAME_CHECK_SECOND: next_state = (keyPressedCode == 8'b00101001) ? GAME_THIRD_ROUND: GAME_CHECK_SECOND;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t GAME_THIRD_ROUND: next_state = GAME_LOAD_THIRD_STR;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t GAME_LOAD_THIRD_STR: next_state = (keyPressedCode == 8'b00110001) ? GAME_CHECK_THIRD: GAME_LOAD_THIRD_STR;\\\\n GAME_CHECK_THIRD: next_state = (keyPressedCode == 8'b00101001) ? GAME_FOURTH_ROUND: GAME_CHECK_THIRD;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t GAME_FOURTH_ROUND: next_state = GAME_LOAD_FOURTH_STR;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t GAME_LOAD_FOURTH_STR: next_state = (keyPressedCode == 8'b00110001) ? GAME_CHECK_FOURTH: GAME_LOAD_FOURTH_STR;\\\\n GAME_CHECK_FOURTH: next_state = (keyPressedCode == 8'b00101001) ? GAME_FIFTH_ROUND: GAME_CHECK_FOURTH;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t GAME_FIFTH_ROUND: next_state = GAME_LOAD_FIFTH_STR;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t GAME_LOAD_FIFTH_STR: next_state = (keyPressedCode == 8'b00110001) ? GAME_CHECK_FIFTH: GAME_LOAD_FIFTH_STR;\\\\n GAME_CHECK_FIFTH: next_state = HOME_SCREEN;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t \\\\n\\\\n default: next_state = HOME_SCREEN;\\\\n\\\\t endcase\\\\n end\\\\n\\\\n always @ (*)\\\\n begin: enable_signals\\\\n\\\\t \\\\n\\\\t\\\\n\\\\t\\\\t\\\\t\\\\t\\\\n case(current_state)\\\\n\\\\t\\\\tHOME_SCREEN:\\\\n\\\\t\\\\tbegin\\\\n\\\\t\\\\tnotes = 0;\\\\n\\\\t\\\\taud_en = 0;\\\\n\\\\t\\\\tsel_note_en = 0;\\\\n\\\\t\\\\tload_str_en = 0;\\\\n\\\\t\\\\tgame_check_en = 0;\\\\n\\\\t\\\\tend\\\\n\\\\n TR_FIRST_NOTE: \\\\n begin\\\\n aud_en = 1;\\\\n\\\\t\\\\tsel_note_en = 1;\\\\n\\\\t\\\\tnotes = 64'h2121212121212121;\\\\n //delay = 19'd191109; //C4 Note: 261.63Hz\\\\n end\\\\n\\\\t\\\\t\\\\n\\\\t\\\\tTR_CHECK_FIRST:\\\\n\\\\t\\\\tbegin\\\\n\\\\t\\\\taud_en = 0;\\\\n\\\\t\\\\tsel_note_en = 0;\\\\n\\\\t\\\\tnotes = 0;\\\\n\\\\t\\\\tend\\\\n\\\\n TR_SECOND_NOTE:\\\\n begin\\\\n aud_en = 1;\\\\n\\\\t\\\\tsel_note_en = 1;\\\\n\\\\t\\\\tnotes = 64'h2323232323232323;\\\\n //delay = 19'd170265; //D4 Note: 293.66Hz\\\\n end\\\\n\\\\t\\\\t\\\\n\\\\t\\\\tTR_CHECK_SECOND:\\\\n\\\\t\\\\tbegin\\\\n\\\\t\\\\taud_en = 0;\\\\n\\\\t\\\\tsel_note_en = 0;\\\\n\\\\t\\\\tnotes = 0;\\\\n\\\\t\\\\tend\\\\n\\\\n TR_THIRD_NOTE:\\\\n begin\\\\n aud_en = 1;\\\\n\\\\t\\\\tsel_note_en = 1;\\\\n\\\\t\\\\tnotes = 64'h2424242424242424;\\\\n //delay = 19'd151685; //E4 Note: 326.63Hz\\\\n end\\\\n\\\\n\\\\t\\\\tTR_CHECK_THIRD:\\\\n\\\\t\\\\tbegin\\\\n\\\\t\\\\taud_en = 0;\\\\n\\\\t\\\\tsel_note_en = 0;\\\\n\\\\t\\\\tnotes = 0;\\\\n\\\\t\\\\tend\\\\n\\\\n TR_FOURTH_NOTE:\\\\n begin\\\\n aud_en = 1;\\\\n\\\\t\\\\tsel_note_en = 1;\\\\n\\\\t\\\\tnotes = 64'h2B2B2B2B2B2B2B2B;\\\\n //delay = 19'd143172; //F4 Note: 349.23Hz\\\\n end\\\\n\\\\n\\\\t\\\\tTR_CHECK_FOURTH:\\\\n\\\\t\\\\tbegin\\\\n\\\\t\\\\taud_en = 0;\\\\n\\\\t\\\\tsel_note_en = 0;\\\\n\\\\t\\\\tnotes = 0;\\\\n\\\\t\\\\tend\\\\n\\\\n\\\\n TR_FIFTH_NOTE:\\\\n begin\\\\n aud_en = 1;\\\\n\\\\t\\\\tsel_note_en = 1;\\\\n\\\\t\\\\tnotes = 64'h3434343434343434;\\\\n //delay = 19'd125771; //G4 Note: 392.00Hz\\\\n end\\\\n\\\\t\\\\t\\\\n\\\\t\\\\tTR_CHECK_FIFTH:\\\\n\\\\t\\\\tbegin\\\\n\\\\t\\\\taud_en = 0;\\\\n\\\\t\\\\tsel_note_en = 0;\\\\n\\\\t\\\\tnotes = 0;\\\\n\\\\t\\\\tend\\\\n\\\\n TR_SIXTH_NOTE:\\\\n begin\\\\n aud_en = 1;\\\\n\\\\t\\\\tsel_note_en = 1;\\\\n\\\\t\\\\tnotes = 64'h1C1C1C1C1C1C1C1C;\\\\n //delay = 19'd113636; //A4 Note: 440.00Hz\\\\n end\\\\n\\\\n\\\\t\\\\tTR_CHECK_SIXTH:\\\\n\\\\t\\\\tbegin\\\\n\\\\t\\\\taud_en = 0;\\\\n\\\\t\\\\tsel_note_en = 0;\\\\n\\\\t\\\\tnotes = 0;\\\\n\\\\t\\\\tend\\\\n\\\\n TR_SEVENTH_NOTE:\\\\n begin\\\\n aud_en = 1;\\\\n\\\\t\\\\tsel_note_en = 1;\\\\n\\\\t\\\\tnotes = 64'h3232323232323232;\\\\n //delay = 19'd101239; //B4 Note: 493.88Hz\\\\n end\\\\n\\\\t\\\\t\\\\n\\\\t\\\\tTR_CHECK_SEVENTH:\\\\n\\\\t\\\\tbegin\\\\n\\\\t\\\\taud_en = 0;\\\\n\\\\t\\\\tsel_note_en = 0;\\\\n\\\\t\\\\tnotes = 0;\\\\n\\\\t\\\\tend\\\\n\\\\n GAME_FIRST_ROUND:\\\\n begin\\\\n aud_en = 1;\\\\n sel_note_en = 1;\\\\n notes = 64'h2123242B341C3221;\\\\n end\\\\n\\\\t\\\\t\\\\n\\\\t\\\\tGAME_LOAD_FIRST_STR:\\\\n\\\\t\\\\tbegin\\\\n\\\\t\\\\tload_str_en = 1;\\\\n\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\n\\\\t\\\\tGAME_CHECK_FIRST:\\\\n\\\\t\\\\tbegin\\\\n\\\\t\\\\taud_en = 0;\\\\n\\\\t\\\\tsel_note_en = 0;\\\\n\\\\t\\\\tload_str_en = 0;\\\\n\\\\t\\\\tgame_check_en = 1;\\\\n\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t\\\\n\\\\t\\\\tGAME_SECOND_ROUND:\\\\n\\\\t\\\\tbegin\\\\n\\\\t\\\\taud_en = 1;\\\\n\\\\t\\\\tsel_note_en = 1;\\\\n\\\\t\\\\tnotes = 64'h342B24232123212B;\\\\n\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\n\\\\t\\\\tGAME_LOAD_SECOND_STR:\\\\n\\\\t\\\\tbegin\\\\n\\\\t\\\\tload_str_en = 1;\\\\n\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\n\\\\t\\\\tGAME_CHECK_SECOND:\\\\n\\\\t\\\\tbegin\\\\n\\\\t\\\\taud_en = 0;\\\\n\\\\t\\\\tsel_note_en = 0;\\\\n\\\\t\\\\tload_str_en = 0;\\\\n\\\\t\\\\tgame_check_en = 1;\\\\n\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\n\\\\t\\\\tGAME_THIRD_ROUND:\\\\n\\\\t\\\\tbegin\\\\n\\\\t\\\\taud_en = 1;\\\\n\\\\t\\\\tsel_note_en = 1;\\\\n\\\\t\\\\tnotes = 64'h23322B34212B3234;\\\\n\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\n\\\\t\\\\tGAME_LOAD_THIRD_STR:\\\\n\\\\t\\\\tbegin\\\\n\\\\t\\\\tload_str_en = 1;\\\\n\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\n\\\\t\\\\tGAME_CHECK_THIRD:\\\\n\\\\t\\\\tbegin\\\\n\\\\t\\\\taud_en = 0;\\\\n\\\\t\\\\tsel_note_en = 0;\\\\n\\\\t\\\\tload_str_en = 0;\\\\n\\\\t\\\\tgame_check_en = 1;\\\\n\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\n\\\\t\\\\tGAME_FOURTH_ROUND:\\\\n\\\\t\\\\tbegin\\\\n\\\\t\\\\taud_en = 1;\\\\n\\\\t\\\\tsel_note_en = 1;\\\\n\\\\t\\\\tnotes = 64'h23241C321C322124;\\\\n\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\n\\\\t\\\\tGAME_LOAD_FOURTH_STR:\\\\n\\\\t\\\\tbegin\\\\n\\\\t\\\\tload_str_en = 1;\\\\n\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\n\\\\t\\\\tGAME_CHECK_FOURTH:\\\\n\\\\t\\\\tbegin\\\\n\\\\t\\\\taud_en = 0;\\\\n\\\\t\\\\tsel_note_en = 0;\\\\n\\\\t\\\\tload_str_en = 0;\\\\n\\\\t\\\\tgame_check_en = 1;\\\\n\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\n\\\\t\\\\tGAME_FIFTH_ROUND:\\\\n\\\\t\\\\tbegin\\\\n\\\\t\\\\taud_en = 1;\\\\n\\\\t\\\\tsel_note_en = 1;\\\\n\\\\t\\\\tnotes = 64'h1C2B342334232132;\\\\n\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\n\\\\t\\\\tGAME_LOAD_FIFTH_STR:\\\\n\\\\t\\\\tbegin\\\\n\\\\t\\\\tload_str_en = 1;\\\\n\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\n\\\\t\\\\tGAME_CHECK_FIFTH:\\\\n\\\\t\\\\tbegin\\\\n\\\\t\\\\taud_en = 0;\\\\n\\\\t\\\\tsel_note_en = 0;\\\\n\\\\t\\\\tload_str_en = 0;\\\\n\\\\t\\\\tgame_check_en = 1;\\\\n\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\n\\\\t\\\\t\\\\n\\\\t endcase\\\\n\\\\t\\\\t//cdefgab 1234567 gfedcdc\\\\n end\\\\n\\\\n \\\\n\\\\n always @ (posedge CLOCK_50)\\\\n if(!resetn)\\\\n begin\\\\n keyPressedCode <= 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t //notes <= 0;\\\\n current_state <= HOME_SCREEN;\\\\n end\\\\n else if(ps2_key_pressed)\\\\n begin\\\\n keyPressedCode <= ps2_key_data;\\\\n current_state <= next_state;\\\\n end\\\\n else current_state <= next_state;\\\\n \\\\n\\\\n\\\\n\\\\n\\\\n \\\\nendmodule", "module load_str(CLOCK_50, resetn, load_str_en, ps2_key_data, ps2_key_pressed, game_str, counter);\\\\n\\\\tinput CLOCK_50, resetn, load_str_en;\\\\n\\\\tinput [7:0] ps2_key_data;\\\\n\\\\tinput ps2_key_pressed;\\\\n\\\\toutput reg [63:0] game_str;\\\\n\\\\toutput reg [3:0] counter;\\\\n\\\\talways @(posedge CLOCK_50)\\\\n\\\\t\\\\tif(!resetn)\\\\n\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\tgame_str <= 0;\\\\n\\\\t\\\\t\\\\tcounter <= 0;\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\telse if(load_str_en)\\\\n\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\tif(counter == 0 && ps2_key_pressed)\\\\n\\\\t\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tif(ps2_key_data != 8'h31)\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tgame_str[63:56] <= ps2_key_data;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tcounter <= counter + 1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\telse if(counter == 1 && ps2_key_pressed)\\\\n\\\\t\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tif(ps2_key_data != game_str[63:56])\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tgame_str[55:48] <= ps2_key_data;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tcounter <= counter + 1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\telse if(counter == 2 && ps2_key_pressed)\\\\n\\\\t\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tif(ps2_key_data != game_str[55:48])\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tgame_str[47:40] <= ps2_key_data;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tcounter <= counter +1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\telse if(counter == 3 && ps2_key_pressed)\\\\n\\\\t\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tif(ps2_key_data != game_str[47:40])\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tgame_str[39:32] <= ps2_key_data;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tcounter <= counter +1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\telse if(counter == 4 && ps2_key_pressed)\\\\n\\\\t\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tif(ps2_key_data != game_str[39:32])\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tgame_str[31:24] <= ps2_key_data;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tcounter <= counter +1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\telse if(counter == 5 && ps2_key_pressed)\\\\n\\\\t\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tif(ps2_key_data != game_str[31:24])\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tgame_str[23:16] <= ps2_key_data;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tcounter <= counter +1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\telse if(counter == 6 && ps2_key_pressed)\\\\n\\\\t\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tif(ps2_key_data != game_str[23:16])\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tgame_str[15:8] <= ps2_key_data;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tcounter <= counter +1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\telse if(counter == 7 && ps2_key_pressed)\\\\n\\\\t\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tif(ps2_key_data != game_str[15:8])\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tgame_str[7:0] <= ps2_key_data;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tcounter <= counter +1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\telse if(counter == 8)\\\\n\\\\t\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tcounter <= 0;\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\n\\\\nendmodule", 'module game_check_str(CLOCK_50, game_check_en, notes, game_str, game_check_done, score);\\\\n\\\\tinput game_check_en, CLOCK_50;\\\\n\\\\tinput [63:0] notes, game_str;\\\\n\\\\toutput reg game_check_done;\\\\n\\\\toutput reg score;\\\\n\\\\talways @(posedge CLOCK_50)\\\\n\\\\t\\\\tif(game_check_en)\\\\n\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\tif(notes == game_str)\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tgame_check_done = 1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tscore = 1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t\\\\telse\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tgame_check_done = 1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tscore = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\nendmodule', "module with modifications made\\\\n\\\\nmodule DE1_SoC_Audio_Example (\\\\n\\\\t// Inputs\\\\n\\\\tCLOCK_50,\\\\n\\\\tKEY,\\\\n\\\\n\\\\tAUD_ADCDAT,\\\\n\\\\n\\\\t// Bidirectionals\\\\n\\\\tAUD_BCLK,\\\\n\\\\tAUD_ADCLRCK,\\\\n\\\\tAUD_DACLRCK,\\\\n\\\\n\\\\tFPGA_I2C_SDAT,\\\\n\\\\n\\\\t// Outputs\\\\n\\\\tAUD_XCK,\\\\n\\\\tAUD_DACDAT,\\\\n\\\\n\\\\tFPGA_I2C_SCLK,\\\\n\\\\tSW,\\\\n\\\\tPS2_CLK,\\\\n\\\\tPS2_DAT,\\\\n\\\\tHEX0,\\\\n\\\\tHEX1,\\\\n\\\\tHEX2,\\\\n\\\\tHEX3,\\\\n\\\\tHEX4,\\\\n\\\\tHEX5,\\\\n\\\\tHEX6,\\\\n\\\\tHEX7\\\\n);\\\\n\\\\n/*****************************************************************************\\\\n * Parameter Declarations *\\\\n *****************************************************************************/\\\\n\\\\n\\\\n/*****************************************************************************\\\\n * Port Declarations *\\\\n *****************************************************************************/\\\\n// Inputs\\\\ninput\\\\t\\\\t\\\\t\\\\tCLOCK_50;\\\\ninput\\\\t\\\\t[3:0]\\\\tKEY;\\\\ninput\\\\t\\\\t[9:0]\\\\tSW;\\\\n\\\\ninput\\\\t\\\\t\\\\t\\\\tAUD_ADCDAT;\\\\n//input\\\\t\\\\t[7:0] Note;\\\\n//input \\\\taud_en;\\\\n\\\\n\\\\ninout\\\\t\\\\t\\\\t\\\\tPS2_CLK;\\\\ninout\\\\t\\\\t\\\\t\\\\tPS2_DAT;\\\\n\\\\n// Bidirectionals\\\\ninout\\\\t\\\\t\\\\t\\\\tAUD_BCLK;\\\\ninout\\\\t\\\\t\\\\t\\\\tAUD_ADCLRCK;\\\\ninout\\\\t\\\\t\\\\t\\\\tAUD_DACLRCK;\\\\n\\\\ninout\\\\t\\\\t\\\\t\\\\tFPGA_I2C_SDAT;\\\\n\\\\n// Outputs\\\\noutput\\\\t\\\\t\\\\t\\\\tAUD_XCK;\\\\noutput\\\\t\\\\t\\\\t\\\\tAUD_DACDAT;\\\\n\\\\noutput\\\\t\\\\t\\\\t\\\\tFPGA_I2C_SCLK;\\\\noutput [6:0] HEX0;\\\\noutput [6:0] HEX1;\\\\noutput\\\\t\\\\t[6:0]\\\\tHEX2;\\\\noutput\\\\t\\\\t[6:0]\\\\tHEX3;\\\\noutput\\\\t\\\\t[6:0]\\\\tHEX4;\\\\noutput\\\\t\\\\t[6:0]\\\\tHEX5;\\\\noutput\\\\t\\\\t[6:0]\\\\tHEX6;\\\\noutput\\\\t\\\\t[6:0]\\\\tHEX7;\\\\n\\\\n/*****************************************************************************\\\\n * Internal Wires and Registers Declarations *\\\\n *****************************************************************************/\\\\n// Internal Wires\\\\nwire\\\\t\\\\t\\\\t\\\\taudio_in_available;\\\\nwire\\\\t\\\\t[31:0]\\\\tleft_channel_audio_in;\\\\nwire\\\\t\\\\t[31:0]\\\\tright_channel_audio_in;\\\\nwire\\\\t\\\\t\\\\t\\\\tread_audio_in;\\\\n\\\\nwire\\\\t\\\\t\\\\t\\\\taudio_out_allowed;\\\\nwire\\\\t\\\\t[31:0]\\\\tleft_channel_audio_out;\\\\nwire\\\\t\\\\t[31:0]\\\\tright_channel_audio_out;\\\\nwire\\\\t\\\\t\\\\t\\\\twrite_audio_out;\\\\n\\\\n\\\\nwire [7:0] keyPressedCode;\\\\nwire [19:0] current_state;\\\\nwire [3:0] CounterValue;\\\\nwire [7:0] Note;\\\\nwire \\\\taud_en;\\\\nwire\\\\t\\\\t[3:0]score;\\\\n\\\\n\\\\nwire \\\\t\\\\t[7:0] ps2_key_data;\\\\nwire \\\\t\\\\tps2_key_pressed;\\\\nwire \\\\t [63:0] game_str;\\\\nwire\\\\t\\\\t[63:0] notes;\\\\n// Internal Registers\\\\n\\\\nreg [18:0] delay_cnt;\\\\nreg [18:0] delay;\\\\n\\\\n\\\\n\\\\nreg snd;\\\\n\\\\n//assign HEX2 = 7'h7F;\\\\n//assign HEX3 = 7'h7F;\\\\n//assign HEX4 = 7'h7F;\\\\n//assign HEX5 = 7'h7F;\\\\nassign HEX6 = 7'h7F;\\\\nassign HEX7 = 7'h7F;\\\\n\\\\n// State Machine Registers\\\\n\\\\n/*****************************************************************************\\\\n * Finite State Machine(s) *\\\\n *****************************************************************************/\\\\nalways @(*)\\\\n\\\\tbegin\\\\n\\\\tif(Note == 8'h21)\\\\n\\\\t\\\\tdelay = {SW[3:0], 19'd191109};\\\\n\\\\telse if(Note == 8'h23)\\\\n\\\\t\\\\tdelay = {SW[3:0], 19'd170265};\\\\n\\\\telse if(Note == 8'h24)\\\\n\\\\t\\\\tdelay = {SW[3:0], 19'd151685};\\\\n\\\\telse if(Note == 8'h2B)\\\\n\\\\t\\\\tdelay = {SW[3:0], 19'd143172};\\\\n\\\\telse if(Note == 8'h34)\\\\n\\\\t\\\\tdelay = {SW[3:0], 19'd125771};\\\\n\\\\telse if(Note == 8'h1C)\\\\n\\\\t\\\\tdelay = {SW[3:0], 19'd113636};\\\\n\\\\telse if(Note == 8'h32)\\\\n\\\\t\\\\tdelay = {SW[3:0], 19'd101239};\\\\n\\\\t\\\\t\\\\n\\\\tend\\\\n\\\\n/*****************************************************************************\\\\n * Sequential Logic *\\\\n *****************************************************************************/\\\\n\\\\nalways @(posedge CLOCK_50)\\\\n\\\\tif(aud_en)\\\\n\\\\tbegin\\\\n\\\\t\\\\tif(delay_cnt == delay) begin\\\\n\\\\t\\\\t\\\\tdelay_cnt <= 0;\\\\n\\\\t\\\\t\\\\tsnd <= !snd;\\\\n\\\\t\\\\tend else delay_cnt <= delay_cnt + 1;\\\\n\\\\tend\\\\n\\\\n/*****************************************************************************\\\\n * Combinational Logic *\\\\n *****************************************************************************/\\\\n\\\\n//assign delay = {SW[3:0], 19'd191109};\\\\n\\\\nwire [31:0] sound = (SW == 0) ? 0 : snd ? 32'd10000000 : -32'd10000000;\\\\n\\\\n\\\\nassign read_audio_in\\\\t\\\\t\\\\t= audio_in_available & audio_out_allowed;\\\\n\\\\nassign left_channel_audio_out\\\\t= left_channel_audio_in+sound;\\\\nassign right_channel_audio_out\\\\t= right_channel_audio_in+sound;\\\\nassign write_audio_out\\\\t\\\\t\\\\t= audio_in_available & audio_out_allowed;\\\\n\\\\n/*****************************************************************************\\\\n * Internal Modules *\\\\n *****************************************************************************/\\\\n \\\\nPS2_Demo demoio(\\\\n\\\\t// Inputs\\\\n\\\\tCLOCK_50,\\\\n\\\\tKEY[3:0],\\\\n\\\\n\\\\t// Bidirectionals\\\\n\\\\tPS2_CLK,\\\\n\\\\tPS2_DAT,\\\\n\\\\t\\\\n\\\\t// Outputs\\\\n\\\\tSW[9:0],\\\\n\\\\tps2_key_data,\\\\n\\\\tps2_key_pressed\\\\n);\\\\ngame_mode_test game(.CLOCK_50(CLOCK_50),.resetn(KEY[1]), .ps2_key_data(ps2_key_data), .ps2_key_pressed(ps2_key_pressed), .speed(SW[9:8]), .CounterValue(CounterValue), .Note(Note), .current_state(current_state), .aud_en(aud_en), .score(score), .game_str(game_str), .notes(notes));\\\\n\\\\n\\\\nHexadecimal_To_Seven_Segment Segment0 (\\\\n\\\\t// Inputs\\\\n\\\\t.hex_number\\\\t\\\\t\\\\t(score[3:0]),\\\\n\\\\n\\\\t// Bidirectional\\\\n\\\\n\\\\t// Outputs\\\\n\\\\t.seven_seg_display\\\\t(HEX0)\\\\n);\\\\nHexadecimal_To_Seven_Segment Segment1 (\\\\n\\\\t// Inputs\\\\n\\\\t.hex_number\\\\t\\\\t\\\\t(4'b0),\\\\n\\\\n\\\\t// Bidirectional\\\\n\\\\n\\\\t// Outputs\\\\n\\\\t.seven_seg_display\\\\t(HEX1)\\\\n);\\\\n\\\\n\\\\nHexadecimal_To_Seven_Segment Segment2 (\\\\n\\\\t// Inputs\\\\n\\\\t.hex_number\\\\t\\\\t\\\\t(current_state[3:0]),\\\\n\\\\n\\\\t// Bidirectional\\\\n\\\\n\\\\t// Outputs\\\\n\\\\t.seven_seg_display\\\\t(HEX2)\\\\n);\\\\nHexadecimal_To_Seven_Segment Segment3 (\\\\n\\\\t// Inputs\\\\n\\\\t.hex_number\\\\t\\\\t\\\\t(current_state[7:4]),\\\\n\\\\n\\\\t// Bidirectional\\\\n\\\\n\\\\t// Outputs\\\\n\\\\t.seven_seg_display\\\\t(HEX3)\\\\n);\\\\nHexadecimal_To_Seven_Segment Segment4 (\\\\n\\\\t// Inputs\\\\n\\\\t.hex_number\\\\t\\\\t\\\\t(game_str[3:0]),\\\\n\\\\n\\\\t// Bidirectional\\\\n\\\\n\\\\t// Outputs\\\\n\\\\t.seven_seg_display\\\\t(HEX4)\\\\n);\\\\nHexadecimal_To_Seven_Segment Segment5 (\\\\n\\\\t// Inputs\\\\n\\\\t.hex_number\\\\t\\\\t\\\\t(game_str[7:4]),\\\\n\\\\n\\\\t// Bidirectional\\\\n\\\\n\\\\t// Outputs\\\\n\\\\t.seven_seg_display\\\\t(HEX5)\\\\n);\\\\n\\\\n\\\\nAudio_Controller Audio_Controller (\\\\n\\\\t// Inputs\\\\n\\\\t.CLOCK_50\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t(CLOCK_50),\\\\n\\\\t.reset\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t(~KEY[0]),\\\\n\\\\n\\\\t.clear_audio_in_memory\\\\t\\\\t(),\\\\n\\\\t.read_audio_in\\\\t\\\\t\\\\t\\\\t(read_audio_in),\\\\n\\\\t\\\\n\\\\t.clear_audio_out_memory\\\\t\\\\t(),\\\\n\\\\t.left_channel_audio_out\\\\t\\\\t(left_channel_audio_out),\\\\n\\\\t.right_channel_audio_out\\\\t(right_channel_audio_out),\\\\n\\\\t.write_audio_out\\\\t\\\\t\\\\t(write_audio_out),\\\\n\\\\n\\\\t.AUD_ADCDAT\\\\t\\\\t\\\\t\\\\t\\\\t(AUD_ADCDAT),\\\\n\\\\n\\\\t// Bidirectionals\\\\n\\\\t.AUD_BCLK\\\\t\\\\t\\\\t\\\\t\\\\t(AUD_BCLK),\\\\n\\\\t.AUD_ADCLRCK\\\\t\\\\t\\\\t\\\\t(AUD_ADCLRCK),\\\\n\\\\t.AUD_DACLRCK\\\\t\\\\t\\\\t\\\\t(AUD_DACLRCK),\\\\n\\\\n\\\\n\\\\t// Outputs\\\\n\\\\t.audio_in_available\\\\t\\\\t\\\\t(audio_in_available),\\\\n\\\\t.left_channel_audio_in\\\\t\\\\t(left_channel_audio_in),\\\\n\\\\t.right_channel_audio_in\\\\t\\\\t(right_channel_audio_in),\\\\n\\\\n\\\\t.audio_out_allowed\\\\t\\\\t\\\\t(audio_out_allowed),\\\\n\\\\n\\\\t.AUD_XCK\\\\t\\\\t\\\\t\\\\t\\\\t(AUD_XCK),\\\\n\\\\t.AUD_DACDAT\\\\t\\\\t\\\\t\\\\t\\\\t(AUD_DACDAT)\\\\n\\\\n);\\\\n\\\\navconf #(.USE_MIC_INPUT(1)) avc (\\\\n\\\\t.FPGA_I2C_SCLK\\\\t\\\\t\\\\t\\\\t\\\\t(FPGA_I2C_SCLK),\\\\n\\\\t.FPGA_I2C_SDAT\\\\t\\\\t\\\\t\\\\t\\\\t(FPGA_I2C_SDAT),\\\\n\\\\t.CLOCK_50\\\\t\\\\t\\\\t\\\\t\\\\t(CLOCK_50),\\\\n\\\\t.reset\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t(~KEY[0])\\\\n);\\\\n\\\\nendmodule"]
["module FSM\\\\n(\\\\nreset, instr, clock,\\\\nN, Z,\\\\nPCwrite, AddrSel, MemRead,\\\\nMemWrite, IRload, OpASel, MDRload,\\\\nOpABLoad, ALU1, ALU2, ALUop,\\\\nALUOutWrite, RFWrite, RegIn, FlagWrite,//, state\\\\nMDRsel \\\\n);\\\\n\\\\tinput\\\\t[3:0] instr;\\\\n\\\\tinput\\\\tN, Z;\\\\n\\\\tinput\\\\treset, clock;\\\\n\\\\toutput\\\\tPCwrite, AddrSel, MemRead, MemWrite, IRload, OpASel, MDRload;\\\\n\\\\toutput\\\\tOpABLoad, ALU1, ALUOutWrite, RFWrite, RegIn, FlagWrite;\\\\n\\\\t//add one more control \\\\n\\\\toutput MDRsel;\\\\n\\\\toutput\\\\t[2:0] ALU2, ALUop;\\\\n\\\\t//output\\\\t[3:0] state;\\\\n\\\\t\\\\n\\\\treg [4:0]\\\\tstate;\\\\t\\\\t\\\\t// 5-bit state can encode 32 distinct values.\\\\n\\\\treg\\\\tPCwrite, AddrSel, MemRead, MemWrite, IRload, OpASel, MDRload, MDRsel;\\\\n\\\\treg\\\\tOpABLoad, ALU1, ALUOutWrite, RFWrite, RegIn, FlagWrite;\\\\n\\\\treg\\\\t[2:0] ALU2, ALUop;\\\\n\\\\t\\\\n\\\\t\\\\n\\\\t// state constants (note: asn = add/sub/nand, asnsh = add/sub/nand/shift)\\\\n\\\\tparameter [4:0] reset_s = 0, c1 = 1, c2 = 2, c3_asn = 3,\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tc4_asnsh = 4, c3_shift = 5, c3_ori = 6,\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tc4_ori = 7, c5_ori = 8, c3_load = 9, c4_load = 10,\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tc3_store = 11, c3_bpz = 12, c3_bz = 13, c3_bnz = 14,\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tc3_jr = 15, c3_jal = 16, c4_jal = 17, c5_jal = 18,c6_jal =19,\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tc3_ldind = 20, c4_ldind = 21, c5_ldind =22;\\\\n\\\\t\\\\n\\\\t// determines the next state based on the current state; supports\\\\n\\\\t// asynchronous reset\\\\n\\\\talways @(posedge clock or posedge reset)\\\\n\\\\tbegin\\\\n\\\\t\\\\tif (reset) state = reset_s;\\\\n\\\\t\\\\telse\\\\n\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\tcase(state)\\\\n\\\\t\\\\t\\\\t\\\\treset_s:\\\\tstate = c1; \\\\t\\\\t// reset state\\\\n\\\\t\\\\t\\\\t\\\\tc1:\\\\t\\\\t\\\\tstate = c2; \\\\t\\\\t// cycle 1\\\\n\\\\t\\\\t\\\\t\\\\tc2:\\\\t\\\\t\\\\tbegin\\\\t\\\\t\\\\t\\\\t// cycle 2\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tif(instr == 4'b0100 | instr == 4'b0110 | instr == 4'b1000) state = c3_asn;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\telse if( instr[2:0] == 3'b011 ) state = c3_shift;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\telse if( instr[2:0] == 3'b111 ) state = c3_ori;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\telse if( instr == 4'b0000 ) state = c3_load;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\telse if( instr == 4'b0010 ) state = c3_store;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\telse if( instr == 4'b1101 ) state = c3_bpz;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\telse if( instr == 4'b0101 ) state = c3_bz;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\telse if( instr == 4'b1001 ) state = c3_bnz;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t//add new states\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\telse if( instr == 4'b1110) state = c3_jr; //jump register\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\telse if( instr == 4'b1100) state = c3_jal; //JAL, jump and link\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\telse if( instr == 4'b0001) state = c3_ldind; //LDIND. Load indirect\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\telse state = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t\\\\tc3_asn:\\\\t\\\\tstate = c4_asnsh;\\\\t// cycle 3: ADD SUB NAND\\\\n\\\\t\\\\t\\\\t\\\\tc4_asnsh:\\\\tstate = c1;\\\\t\\\\t\\\\t// cycle 4: ADD SUB NAND/SHIFT\\\\n\\\\t\\\\t\\\\t\\\\tc3_shift:\\\\tstate = c4_asnsh;\\\\t// cycle 3: SHIFT\\\\n\\\\t\\\\t\\\\t\\\\tc3_ori:\\\\t\\\\tstate = c4_ori;\\\\t\\\\t// cycle 3: ORI\\\\n\\\\t\\\\t\\\\t\\\\tc4_ori:\\\\t\\\\tstate = c5_ori;\\\\t\\\\t// cycle 4: ORI\\\\n\\\\t\\\\t\\\\t\\\\tc5_ori:\\\\t\\\\tstate = c1;\\\\t\\\\t\\\\t// cycle 5: ORI\\\\n\\\\t\\\\t\\\\t\\\\tc3_load:\\\\tstate = c4_load;\\\\t// cycle 3: LOAD\\\\n\\\\t\\\\t\\\\t\\\\tc4_load:\\\\tstate = c1; \\\\t\\\\t// cycle 4: LOAD\\\\n\\\\t\\\\t\\\\t\\\\tc3_store:\\\\tstate = c1; \\\\t\\\\t// cycle 3: STORE\\\\n\\\\t\\\\t\\\\t\\\\tc3_bpz:\\\\t\\\\tstate = c1; \\\\t\\\\t// cycle 3: BPZ\\\\n\\\\t\\\\t\\\\t\\\\tc3_bz:\\\\t\\\\tstate = c1; \\\\t\\\\t// cycle 3: BZ\\\\n\\\\t\\\\t\\\\t\\\\tc3_bnz:\\\\t\\\\tstate = c1; \\\\t\\\\t// cycle 3: BNZ\\\\n\\\\t\\\\t\\\\t\\\\t//add lab7\\\\n\\\\t\\\\t\\\\t\\\\t//JR\\\\n\\\\t\\\\t\\\\t\\\\tc3_jr: state = c1;\\\\n\\\\t\\\\t\\\\t\\\\t//JAL\\\\n\\\\t\\\\t\\\\t\\\\tc3_jal: state = c4_jal;\\\\n\\\\t\\\\t\\\\t\\\\tc4_jal: state = c5_jal;\\\\n\\\\t\\\\t\\\\t\\\\tc5_jal: state = c6_jal;\\\\n\\\\t\\\\t\\\\t\\\\tc6_jal: state = c1; //done, go reset\\\\n//\\\\t\\\\t\\\\t\\\\t\\\\n\\\\t\\\\t\\\\t\\\\t//LDIND\\\\n\\\\t\\\\t\\\\t\\\\tc3_ldind: state = c4_ldind;\\\\n\\\\t\\\\t\\\\t\\\\tc4_ldind: state = c5_ldind;\\\\n\\\\t\\\\t\\\\t\\\\tc3_ldind: state = c4_ldind;\\\\n\\\\t\\\\t\\\\t\\\\tc4_ldind: state = c5_ldind;\\\\n\\\\t\\\\t\\\\t\\\\tc5_ldind: state = c6_ldind;\\\\n\\\\t\\\\t\\\\t\\\\tc6_ldind: state = c7_ldind;\\\\n\\\\t\\\\t\\\\t\\\\tc7_ldind: state = c1; //reset\\\\n\\\\t\\\\t\\\\tendcase\\\\n\\\\t\\\\tend\\\\n\\\\tend\\\\n\\\\n\\\\t// sets the control sequences based on the current state and instruction\\\\n\\\\talways @(*)\\\\n\\\\tbegin\\\\n\\\\t\\\\tcase (state)\\\\n\\\\t\\\\t\\\\treset_s:\\\\t//control = 19'b0000000000000000000;\\\\n\\\\t\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tPCwrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tAddrSel = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tMemRead = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tMemWrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tIRload = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tOpASel = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tMDRload = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tOpABLoad = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALU1 = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALU2 = 3'b000;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALUop = 3'b000;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALUOutWrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tRFWrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tRegIn = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tFlagWrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tMDRsel = 0;\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\t\\\\t\\\\t\\\\t\\\\t\\\\n\\\\t\\\\t\\\\tc1: \\\\t\\\\t//control = 19'b1110100000010000000;\\\\n\\\\t\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tPCwrite = 1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tAddrSel = 1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tMemRead = 1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tMemWrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tIRload = 1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tOpASel = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tMDRload = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tOpABLoad = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALU1 = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALU2 = 3'b001;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALUop = 3'b000;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALUOutWrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tRFWrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tRegIn = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tFlagWrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tMDRsel =0;\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\t\\\\n\\\\t\\\\t\\\\tc2: \\\\t\\\\t//control = 19'b0000000100000000000;\\\\n\\\\t\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tPCwrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tAddrSel = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tMemRead = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tMemWrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tIRload = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tOpASel = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tMDRload = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tOpABLoad = 1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALU1 = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALU2 = 3'b000;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALUop = 3'b000;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALUOutWrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tRFWrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tRegIn = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tFlagWrite = 0; \\\\n\\\\t\\\\t\\\\t\\\\t\\\\tMDRsel =0; //still let OPA/R1 go through\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\tc3_asn:\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tif ( instr == 4'b0100 ) \\\\t\\\\t// add\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t//control = 19'b0000000010000001001;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tPCwrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tAddrSel = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tMemRead = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tMemWrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tIRload = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tOpASel = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tMDRload = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tOpABLoad = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tALU1 = 1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tALU2 = 3'b000;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tALUop = 3'b000;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tALUOutWrite = 1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tRFWrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tRegIn = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tFlagWrite = 1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tMDRsel =0; //still let OPA/R1 go through\\\\n\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tend\\\\t\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\telse if ( instr == 4'b0110 ) \\\\t// sub\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t//control = 19'b0000000010000011001;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tPCwrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tAddrSel = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tMemRead = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tMemWrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tIRload = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tOpASel = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tMDRload = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tOpABLoad = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tALU1 = 1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tALU2 = 3'b000;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tALUop = 3'b001;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tALUOutWrite = 1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tRFWrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tRegIn = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tFlagWrite = 1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tMDRsel =0; //still let OPA/R1 go through\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\telse \\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t// nand\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t//control = 19'b0000000010000111001;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tPCwrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tAddrSel = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tMemRead = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tMemWrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tIRload = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tOpASel = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tMDRload = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tOpABLoad = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tALU1 = 1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tALU2 = 3'b000;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tALUop = 3'b011;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tALUOutWrite = 1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tRFWrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tRegIn = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tFlagWrite = 1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tMDRsel =0; //still let OPA/R1 go through\\\\n\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t\\\\t \\\\t\\\\tend\\\\n\\\\t\\\\t\\\\tc4_asnsh: \\\\t//control = 19'b0000000000000000100;\\\\n\\\\t\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tPCwrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tAddrSel = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tMemRead = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tMemWrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tIRload = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tOpASel = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tMDRload = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tOpABLoad = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALU1 = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALU2 = 3'b000;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALUop = 3'b000;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALUOutWrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tRFWrite = 1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tRegIn = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tFlagWrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tMDRsel =0; //still let OPA/R1 go through\\\\n\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\tc3_shift: \\\\t//control = 19'b0000000011001001001;\\\\n\\\\t\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tPCwrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tAddrSel = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tMemRead = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tMemWrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tIRload = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tOpASel = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tMDRload = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tOpABLoad = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALU1 = 1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALU2 = 3'b100;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALUop = 3'b100;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALUOutWrite = 1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tRFWrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tRegIn = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tFlagWrite = 1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tMDRsel =0; //still let OPA/R1 go through\\\\n\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\tc3_ori: \\\\t//control = 19'b0000010100000000000;\\\\n\\\\t\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tPCwrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tAddrSel = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tMemRead = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tMemWrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tIRload = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tOpASel = 1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tMDRload = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tOpABLoad = 1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALU1 = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALU2 = 3'b000;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALUop = 3'b000;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALUOutWrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tRFWrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tRegIn = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tFlagWrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tMDRsel =0; //still let OPA/R1 go through\\\\n\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\tc4_ori: \\\\t//control = 19'b0000000010110101001;\\\\n\\\\t\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tPCwrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tAddrSel = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tMemRead = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tMemWrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tIRload = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tOpASel = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tMDRload = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tOpABLoad = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALU1 = 1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALU2 = 3'b011;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALUop = 3'b010;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALUOutWrite = 1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tRFWrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tRegIn = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tFlagWrite = 1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tMDRsel =0; //still let OPA/R1 go through\\\\n\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\tc5_ori: \\\\t//control = 19'b0000010000000000100;\\\\n\\\\t\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tPCwrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tAddrSel = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tMemRead = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tMemWrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tIRload = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tOpASel = 1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tMDRload = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tOpABLoad = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALU1 = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALU2 = 3'b000;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALUop = 3'b000;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALUOutWrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tRFWrite = 1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tRegIn = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tFlagWrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tMDRsel =0; //still let OPA/R1 go through\\\\n\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\tc3_load: \\\\t//control = 19'b0010001000000000000;\\\\n\\\\t\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tPCwrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tAddrSel = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tMemRead = 1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tMemWrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tIRload = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tOpASel = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tMDRload = 1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tOpABLoad = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALU1 = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALU2 = 3'b000;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALUop = 3'b000;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALUOutWrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tRFWrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tRegIn = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tFlagWrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tMDRsel =0; //still let OPA/R1 go through\\\\n\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\tc4_load: \\\\t//control = 19'b0000000000000001110;\\\\n\\\\t\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tPCwrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tAddrSel = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tMemRead = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tMemWrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tIRload = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tOpASel = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tMDRload = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tOpABLoad = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALU1 = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALU2 = 3'b000;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALUop = 3'b000;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALUOutWrite = 1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tRFWrite = 1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tRegIn = 1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tFlagWrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tMDRsel =0; //still let OPA/R1 go through\\\\n\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\tc3_store: \\\\t//control = 19'b0001000000000000000;\\\\n\\\\t\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tPCwrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tAddrSel = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tMemRead = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tMemWrite = 1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tIRload = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tOpASel = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tMDRload = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tOpABLoad = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALU1 = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALU2 = 3'b000;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALUop = 3'b000;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALUOutWrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tRFWrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tRegIn = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tFlagWrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tMDRsel =0; //still let OPA/R1 go through\\\\n\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\tc3_bpz: \\\\t//control = {~N,18'b000000000100000000};\\\\n\\\\t\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tPCwrite = ~N;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tAddrSel = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tMemRead = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tMemWrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tIRload = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tOpASel = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tMDRload = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tOpABLoad = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALU1 = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALU2 = 3'b010;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALUop = 3'b000;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALUOutWrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tRFWrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tRegIn = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tFlagWrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tMDRsel =0; //still let OPA/R1 go through\\\\n\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\tc3_bz: \\\\t\\\\t//control = {Z,18'b000000000100000000};\\\\n\\\\t\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tPCwrite = Z;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tAddrSel = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tMemRead = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tMemWrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tIRload = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tOpASel = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tMDRload = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tOpABLoad = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALU1 = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALU2 = 3'b010;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALUop = 3'b000;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALUOutWrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tRFWrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tRegIn = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tFlagWrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tMDRsel =0; //still let OPA/R1 go through\\\\n\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\tc3_bnz: \\\\t//control = {~Z,18'b000000000100000000};\\\\n\\\\t\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tPCwrite = ~Z;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tAddrSel = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tMemRead = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tMemWrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tIRload = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tOpASel = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tMDRload = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tOpABLoad = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALU1 = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALU2 = 3'b010;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALUop = 3'b000;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALUOutWrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tRFWrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tRegIn = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tFlagWrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tMDRsel =0; //still let OPA/R1 go through\\\\n\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t\\\\t\\\\n\\\\t\\\\t\\\\t//add JR control signals\\\\n\\\\t\\\\t\\\\tc3_jr: // MDR = mem[R2]\\\\n\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tPCwrite = 1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tAddrSel = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tMemRead = 1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tMemWrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tIRload = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tOpASel = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tMDRload = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tOpABLoad = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALU1 = 1; \\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALU2 = 3'b101; //give ALU 0\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALUop = 3'b000; //op = add\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALUOutWrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tRFWrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tRegIn = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tFlagWrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\tMDRsel =0; //still let OPA/R1 go through\\\\n\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t\\\\n\\\\t\\\\t\\\\t//JAL\\\\n\\\\t\\\\t\\\\tc3_jal: //PC+1 to PC\\\\n\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tPCwrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tAddrSel = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tMemRead = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tMemWrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tIRload = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tOpASel = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tMDRload = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tOpABLoad = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALU1 = 0; //get PC\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALU2 = 3'b101; //get im 0\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALUop = 3'b000; //do add\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALUOutWrite = 1; //go to alu_reg\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tRFWrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tRegIn = 0; //chooses ALUout\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tFlagWrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tMDRsel =0; //still let OPA/R1 go through\\\\n\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t\\\\n\\\\t\\\\t\\\\tc4_jal: //PC to R1\\\\n\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tPCwrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tAddrSel = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tMemRead = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tMemWrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tIRload = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tOpASel = 1; //leave it there\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tMDRload = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tOpABLoad = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALU1 = 0; //take the PC +1 directly\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALU2 = 3'b000; //010, IMM4\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALUop = 3'b000; //add\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALUOutWrite = 0; //keep pc + 1\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tRFWrite = 1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tRegIn = 0; //chooses ALUoutReg\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tFlagWrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tMDRsel =0; //still let OPA/R1 go through\\\\n\\\\t\\\\t\\\\t\\\\t\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t\\\\n\\\\t\\\\t\\\\tc5_jal: //get pc + 1 + IMM4 -> PC\\\\n\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tPCwrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tAddrSel = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tMemRead = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tMemWrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tIRload = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tOpASel = 1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tMDRload = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tOpABLoad = 1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALU1 = 0; //take pc directly\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALU2 = 3'b000; //selec imm4\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALUop = 3'b000; //add\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALUOutWrite = 0; //go directly to PC?\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tRFWrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tRegIn = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tFlagWrite = 0;\\\\t\\\\t\\\\t\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\n\\\\t\\\\t\\\\t\\\\n\\\\t\\\\t\\\\tc6_jal: //get pc + 1 + IMM4 -> PC\\\\n\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tPCwrite = 1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tAddrSel = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tMemRead = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tMemWrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tIRload = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tOpASel = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tMDRload = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tOpABLoad = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALU1 = 1; //take pc directly\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALU2 = 3'b010; //selec imm4\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALUop = 3'b000; //add\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALUOutWrite = 0; //go directly to PC?\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tRFWrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tRegIn = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tFlagWrite = 0;\\\\t\\\\t\\\\t\\\\n\\\\t\\\\t\\\\tend\\\\n//\\\\t\\\\t\\\\tc7_jal: //get pc + 1 + IMM4 -> PC\\\\n//\\\\t\\\\t\\\\tbegin\\\\n//\\\\t\\\\t\\\\t\\\\t\\\\tPCwrite = 1;\\\\n//\\\\t\\\\t\\\\t\\\\t\\\\tAddrSel = 0;\\\\n//\\\\t\\\\t\\\\t\\\\t\\\\tMemRead = 0;\\\\n//\\\\t\\\\t\\\\t\\\\t\\\\tMemWrite = 0;\\\\n//\\\\t\\\\t\\\\t\\\\t\\\\tIRload = 0;\\\\n//\\\\t\\\\t\\\\t\\\\t\\\\tOpASel = 0;\\\\n//\\\\t\\\\t\\\\t\\\\t\\\\tMDRload = 0;\\\\n//\\\\t\\\\t\\\\t\\\\t\\\\tOpABLoad = 0;\\\\n//\\\\t\\\\t\\\\t\\\\t\\\\tALU1 = 0; //take pc directly\\\\n//\\\\t\\\\t\\\\t\\\\t\\\\tALU2 = 3'b000; //selec imm4\\\\n//\\\\t\\\\t\\\\t\\\\t\\\\tALUop = 3'b000; //add\\\\n//\\\\t\\\\t\\\\t\\\\t\\\\tALUOutWrite = 0; //go directly to PC?\\\\n//\\\\t\\\\t\\\\t\\\\t\\\\tRFWrite = 0;\\\\n//\\\\t\\\\t\\\\t\\\\t\\\\tRegIn = 0;\\\\n//\\\\t\\\\t\\\\t\\\\t\\\\tFlagWrite = 0;\\\\t\\\\t\\\\t\\\\n//\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t//LDIND\\\\n\\\\t\\\\t\\\\tc3_ldind: //read 1st\\\\n\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tPCwrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tAddrSel = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tMemRead = 1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tMemWrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tIRload = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tOpASel = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tMDRload = 1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tOpABLoad = 1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALU1 = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALU2 = 3'b000;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALUop = 3'b000;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALUOutWrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tRFWrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tRegIn = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tFlagWrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tMDRsel =0; //still let OPA/R1 go through\\\\t\\\\t\\\\t\\\\n\\\\t\\\\t\\\\t\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\t\\\\n\\\\t\\\\t\\\\tc4_ldind: //read 2nd\\\\n\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tPCwrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tAddrSel = 2; //fetch the read addr\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tMemRead = 1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tMemWrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tIRload = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tOpASel = 0; \\\\n\\\\t\\\\t\\\\t\\\\t\\\\tMDRload = 1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tOpABLoad = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALU1 = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALU2 = 3'b000;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALUop = 3'b000;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALUOutWrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tRFWrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tRegIn = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tFlagWrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tMDRsel =1; //still let OPA/R1 go through\\\\t\\\\t\\\\t\\\\n\\\\t\\\\t\\\\t\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\t\\\\tc5_ldind: //read 2nd\\\\n\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tPCwrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tAddrSel = 0; \\\\n\\\\t\\\\t\\\\t\\\\t\\\\tMemRead = 1;//OPA read\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tMemWrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tIRload = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tOpASel = 0; \\\\n\\\\t\\\\t\\\\t\\\\t\\\\tMDRload = 1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tOpABLoad = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALU1 = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALU2 = 3'b000;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALUop = 3'b000;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALUOutWrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tRFWrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tRegIn = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tFlagWrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tMDRsel =1; //still let OPA/R1 go through\\\\t\\\\t\\\\t\\\\n\\\\t\\\\t\\\\t\\\\n\\\\t\\\\t\\\\tend\\\\t\\\\t\\\\t\\\\t\\\\t\\\\t\\\\n\\\\t\\\\t\\\\n\\\\t\\\\t\\\\tc6_ldind: //go to R1\\\\n\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tPCwrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tAddrSel = 1; //read into \\\\n\\\\t\\\\t\\\\t\\\\t\\\\tMemRead = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tMemWrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tIRload = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tOpASel = 1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tMDRload = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tOpABLoad = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALU1 = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALU2 = 3'b000;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALUop = 3'b000;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALUOutWrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tRFWrite = 1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tRegIn = 1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tFlagWrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tMDRsel =0; //still let OPA/R1 go through\\\\t\\\\t\\\\t\\\\n\\\\t\\\\t\\\\t\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\n\\\\t\\\\t\\\\tc7_ldind: //go to R1\\\\n\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tPCwrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tAddrSel = 0; //read into \\\\n\\\\t\\\\t\\\\t\\\\t\\\\tMemRead = 1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tMemWrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tIRload = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tOpASel = 1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tMDRload = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tOpABLoad = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALU1 = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALU2 = 3'b000;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALUop = 3'b000;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALUOutWrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tRFWrite = 1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tRegIn = 1;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tFlagWrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tMDRsel =0; //still let OPA/R1 go through\\\\t\\\\t\\\\t\\\\n\\\\t\\\\t\\\\t\\\\n\\\\t\\\\t\\\\tend\\\\n\\\\n\\\\n\\\\t\\\\t\\\\tdefault:\\\\t//control = 19'b0000000000000000000;\\\\n\\\\t\\\\t\\\\t\\\\tbegin\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tPCwrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tAddrSel = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tMemRead = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tMemWrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tIRload = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tOpASel = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tMDRload = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tOpABLoad = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALU1 = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALU2 = 3'b000;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALUop = 3'b000;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tALUOutWrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tRFWrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tRegIn = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tFlagWrite = 0;\\\\n\\\\t\\\\t\\\\t\\\\t\\\\tMDRsel =0; //still let OPA/R1 go through\\\\n\\\\n\\\\t\\\\t\\\\t\\\\tend\\\\n\\\\t\\\\tendcase\\\\n\\\\tend\\\\n\\\\t\\\\nendmodule"]
["module LCD_MIN(clk, slide, lcd_rs, lcd_rw, lcd_e, minpos, PB1, PB2, PB3, PB4,lcd4,lcd5,lcd6,lcd7\\\\n );\\\\ninput[2:0] slide;\\\\ninput clk, PB1, PB2, PB3, PB4;\\\\noutput lcd_rs, lcd_rw, lcd_e, minpos,lcd4,lcd5,lcd6,lcd7;\\\\nwire lcd_rs, lcd_rw, lcd_e, lcd4,lcd5,lcd6,lcd7;\\\\nwire[7:0] DB;\\\\nwire[1:0] minpos;\\\\n\\\\nreg[127:0] lines, lines1;\\\\nreg[2:0] A, B, C, D;\\\\nreg[1:0] counter;\\\\nreg flag =0;\\\\ninitial begin\\\\n\\\\tcounter <= 2'b00;\\\\n\\\\tA <= 3'b0;\\\\n\\\\tB <= 3'b0;\\\\n\\\\tC <= 3'b0;\\\\n\\\\tD <= 3'b0;\\\\n\\\\tflag <= 0;\\\\nend\\\\n\\\\n// using 4th slide to trigger input and the rest three buttons to set input value\\\\nalways@(posedge PB1) begin\\\\n\\\\t\\\\t\\\\tA <= slide[2:0];\\\\n\\\\t\\\\t\\\\tlines[127:120] <= (8'b00110000);\\\\n\\\\t\\\\t\\\\tlines[122:120] <= A;\\\\n\\\\t\\\\t\\\\tlines[119:112] <= 8'b00101100;\\\\n\\\\t\\\\t\\\\tlines[111:104] <= 8'b00100000;\\\\nend\\\\nalways@(posedge PB2) begin\\\\n\\\\t\\\\t\\\\tB <= slide[2:0];\\\\n\\\\t\\\\t\\\\tlines[103:96] <= (8'b00110000);\\\\n\\\\t\\\\t\\\\tlines[98:96] <= B;\\\\n\\\\t\\\\t\\\\tlines[95:88] <= 8'b00101100;\\\\n\\\\t\\\\t\\\\tlines[87:80] <= 8'b00100000;\\\\nend\\\\nalways@(posedge PB3) begin\\\\n\\\\t\\\\t\\\\tC <= slide[2:0];\\\\n\\\\t\\\\t\\\\tlines[79:72] <= (8'b00110000);\\\\n\\\\t\\\\t\\\\tlines[74:72] <= C;\\\\n\\\\t\\\\t\\\\tlines[71:64] <= 8'b00101100;\\\\n\\\\t\\\\t\\\\tlines[63:56] <= 8'b00100000;\\\\nend\\\\nalways@(posedge PB4) begin\\\\n\\\\t\\\\t\\\\tD <= slide[2:0];\\\\n\\\\t\\\\t\\\\tlines[55:48] <= (8'b00110000);\\\\n\\\\t\\\\t\\\\tlines[50:48] <= D;\\\\n\\\\t\\\\t\\\\tlines[47:40] <= 8'b00101100;\\\\n\\\\t\\\\t\\\\tlines[39:32] <= 8'b00100000;\\\\n\\\\t\\\\t\\\\tlines[31:24] <= 8'b00100000;\\\\n\\\\t\\\\t\\\\tlines[23:16] <= 8'b00100000;\\\\n\\\\t\\\\t\\\\tlines[15:8] <= 8'b00100000;\\\\n\\\\t\\\\t\\\\tlines[7:0] <= 8'b00100000;\\\\n\\\\t\\\\t\\\\t\\\\n\\\\t\\\\t\\\\tlines1[127:120] <= DB;\\\\n\\\\t\\\\t\\\\tlines1[119:112] <= 8'b00100000;\\\\n\\\\t\\\\t\\\\tlines1[111:104] <= 8'b00100000;\\\\n\\\\t\\\\t\\\\tlines1[103:96] <= 8'b00100000;\\\\n\\\\t\\\\t\\\\tlines1[95:88] <= 8'b00100000;\\\\n\\\\t\\\\t\\\\tlines1[87:80] <= 8'b00100000;\\\\n\\\\t\\\\t\\\\tlines1[79:72] <= 8'b00100000;\\\\n\\\\t\\\\t\\\\t\\\\n\\\\t\\\\t\\\\tlines1[71:64] <= 8'b00100000;\\\\n\\\\t\\\\t\\\\tlines1[63:56] <= 8'b00100000;\\\\n\\\\t\\\\t\\\\tlines1[55:48] <= 8'b00100000;\\\\n\\\\t\\\\t\\\\tlines1[47:40] <= 8'b00100000;\\\\n\\\\t\\\\t\\\\tlines1[39:32] <= 8'b00100000;\\\\n\\\\t\\\\t\\\\tlines1[31:24] <= 8'b00100000;\\\\n\\\\t\\\\t\\\\tlines1[23:16] <= 8'b00100000;\\\\n\\\\t\\\\t\\\\tlines1[15:8] <= 8'b00100000;\\\\n\\\\t\\\\t\\\\tlines1[7:0] <= 8'b00100000;\\\\n\\\\t\\\\t\\\\tflag <= 1;\\\\n\\\\t\\\\t\\\\t\\\\nend\\\\n\\\\nminimum uut0(A, B, C, D, clk, DB, minpos);\\\\n\\\\n\\\\nLCD uut1(lines,\\\\n\\\\t\\\\t\\\\t lines1,clk, lcd_rs, lcd_rw, lcd_e, lcd4,lcd5,lcd6,lcd7,flag);\\\\n\\\\nendmodule"]
["module dataPath_V2_TB();\\\\nreg [63:0] k;\\\\nreg [4:0] FS;\\\\nreg B_Sel;\\\\nreg EN_B = 1'b0;\\\\nreg EN_ALU = 1'b0;\\\\nreg w_reg = 1'b0;\\\\nreg reset_reg = 1'b0;\\\\nreg C0 = 1'b0;\\\\nreg [4:0] SA = 5'b00000;\\\\nreg [4:0] SB = 5'b00000;\\\\nreg [4:0] DA = 5'b00000;\\\\nwire [63:0] data_bus;\\\\nwire [15:0] r0, r1, r2, r3, r4, r5, r6, r7;\\\\nreg clock = 1'b0;\\\\nreg ram_cs = 1'b1;\\\\nreg ram_write_en = 1'b0;\\\\nreg ram_read_en = 1'b0;\\\\nreg EN_ADDR_ALU = 1'b0;\\\\nreg [1:0] ramOutsize = 2'b11;\\\\n \\\\n\\\\t\\\\t\\\\t\\\\t\\\\t//r0, r1, r2, r3, r4, r5, r6, r7, data_bus, k, FS, B_Sel, EN_B, EN_ALU, EN_ADDR_ALU, ram_cs, ram_write_en, ram_read_en, w_reg, reset_reg, clock, SA, SB, DA, C0\\\\ndataPath_V2 dp (r0, r1, r2, r3, r4, r5, r6, r7, data_bus, k, FS, B_Sel, EN_B, EN_ALU, EN_ADDR_ALU, ram_cs, ram_write_en, ram_read_en, w_reg, reset_reg, ramOutsize, clock, SA, SB, DA, C0);\\\\n\\\\nwire [31:0] add = dp.addressLine;\\\\nwire [63:0] regOutB = dp.regOut_B;\\\\nwire [63:0] regOutA = dp.regOut_A;\\\\nwire [63:0] muxOut = dp.muxOut;\\\\nwire [63:0] aluOut = dp.alu_out;\\\\n\\\\nalways begin\\\\n\\\\t#5 clock <= ~clock;\\\\nend\\\\n\\\\ninitial begin\\\\n\\\\t//LOAD X0 with 10;\\\\n\\\\t#5;\\\\n\\\\tk = 64'd10;\\\\n\\\\tEN_ALU = 1'b1;\\\\n\\\\tFS = 5'b01100; //OR\\\\n\\\\tDA = 5'b00000;\\\\n\\\\tSA = 5'd31;\\\\t\\\\n\\\\tw_reg = 1'b1;\\\\n\\\\tB_Sel = 1'b1;\\\\n\\\\t#5;\\\\n\\\\tEN_ALU = 1'b0;\\\\n\\\\t#5;\\\\t\\\\n\\\\t//X1 <= X0 + 5\\\\n\\\\tk = 64'd5;\\\\n\\\\tFS = 5'b01000; //ADD\\\\n\\\\tDA = 5'b00001;\\\\n\\\\tSA = 5'd0;\\\\n\\\\tEN_ALU = 1'b1;\\\\n\\\\t//X3 <= X0;\\\\n\\\\t#5;\\\\n\\\\tEN_ALU = 1'b0;\\\\n\\\\t#5; \\\\n\\\\tDA = 5'b00011;\\\\n\\\\tSB = 5'd0;\\\\n\\\\tEN_B = 1'b1;\\\\n\\\\t#5;\\\\n\\\\tEN_B = 1'b0;\\\\n\\\\tw_reg = 1'b0;\\\\n\\\\t//Testing RAM\\\\n\\\\t#20;\\\\n\\\\tSA = 5'd31;\\\\n\\\\tSB = 5'd1;\\\\n\\\\tFS = 5'b00000; //AND\\\\n\\\\tEN_ADDR_ALU = 1'b1;\\\\n\\\\tEN_B = 1'b1;\\\\n\\\\tram_write_en = 1'b1;\\\\n\\\\t#20;\\\\n\\\\tEN_B = 1'b0;\\\\n\\\\tram_write_en = 1'b0;\\\\n\\\\t#10;\\\\n\\\\tDA = 5'd4;\\\\n\\\\tram_read_en = 1'b1;\\\\n\\\\tw_reg = 1'b1;\\\\n\\\\t#10;\\\\n\\\\t#100 $stop;\\\\nend\\\\n\\\\nendmodule"]
module glbl ();parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL;
module PureCSHA_4_3 (C, S, X, Y); output [5:4] C; output [4:3] S; input [4:3] X; input [4:3] Y; UBHA_3 U0 (C[4], S[3], X[3], Y[3]); UBHA_4 U1 (C[5], S[4], X[4], Y[4]); endmodule
//***************************************************************************** // (c) Copyright 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // Description // This module instantiates the clock synchronization logic. It passes the // incoming signal through two flops to ensure metastability. // //***************************************************************************** `timescale 1ps / 1ps `default_nettype none (* DowngradeIPIdentifiedWarnings="yes" *) module axis_infrastructure_v1_1_clock_synchronizer # ( /////////////////////////////////////////////////////////////////////////////// // Parameter Definitions /////////////////////////////////////////////////////////////////////////////// parameter integer C_NUM_STAGES = 4 ) ( /////////////////////////////////////////////////////////////////////////////// // Port Declarations /////////////////////////////////////////////////////////////////////////////// input wire clk, input wire synch_in , output wire synch_out ); //////////////////////////////////////////////////////////////////////////////// // Local Parameters //////////////////////////////////////////////////////////////////////////////// localparam integer P_SYNCH_D_WIDTH = (C_NUM_STAGES > 0) ? C_NUM_STAGES : 1; //////////////////////////////////////////////////////////////////////////////// // Wires/Reg declarations //////////////////////////////////////////////////////////////////////////////// (* ASYNC_REG *) reg [P_SYNCH_D_WIDTH-1:0] synch_d = 'b0; generate if (C_NUM_STAGES > 0) begin : gen_synchronizer genvar i; always @(posedge clk) begin synch_d[0] <= synch_in; end for (i = 1; i < C_NUM_STAGES ; i = i + 1) begin : gen_stage always @(posedge clk) begin synch_d[i] <= synch_d[i-1]; end end assign synch_out = synch_d[C_NUM_STAGES-1]; end else begin : gen_no_synchronizer assign synch_out = synch_in; end endgenerate endmodule `default_nettype wire
module glbl ();parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL;
`timescale 1ps / 1ps /***************************************************************************** Verilog RTL Description Configured at: 02:10:16 CST (+0800), Wednesday 05 May 2021 Configured on: ws28 Configured by: m109061634 (m109061634) Created by: Stratus DpOpt 2019.1.01 *******************************************************************************/ module DC_Filter_Add2i36Mul2i258Add2u1Mul2i3u2_1 ( in2, in1, out1 ); /* architecture "behavioural" */ input [1:0] in2; input in1; output [11:0] out1; wire [11:0] asc001; wire [3:0] asc002; wire [3:0] asc002_tmp_0; assign asc002_tmp_0 = +(4'B0011 * in2); assign asc002 = asc002_tmp_0 +(in1); wire [11:0] asc001_tmp_1; assign asc001_tmp_1 = +(12'B000100000010 * asc002); assign asc001 = asc001_tmp_1 +(12'B000000100100); assign out1 = asc001; endmodule /* CADENCE v7b0SAg= : u9/ySgnWtBlWxVPRXgAZ4Og= ** DO NOT EDIT THIS LINE ******/
`timescale 1ps / 1ps /***************************************************************************** Verilog RTL Description Configured at: 00:38:31 CST (+0800), Wednesday 05 May 2021 Configured on: ws28 Configured by: m109061634 (m109061634) Created by: Stratus DpOpt 2019.1.01 *******************************************************************************/ module DC_Filter_Add2i180Mul2i258Add2u1Mul2i3u2_4 ( in2, in1, out1 ); /* architecture "behavioural" */ input [1:0] in2; input in1; output [11:0] out1; wire [11:0] asc001; wire [3:0] asc002; wire [3:0] asc002_tmp_0; assign asc002_tmp_0 = +(4'B0011 * in2); assign asc002 = asc002_tmp_0 +(in1); wire [11:0] asc001_tmp_1; assign asc001_tmp_1 = +(12'B000100000010 * asc002); assign asc001 = asc001_tmp_1 +(12'B000010110100); assign out1 = asc001; endmodule /* CADENCE v7X3SgA= : u9/ySgnWtBlWxVPRXgAZ4Og= ** DO NOT EDIT THIS LINE ******/
module PDKGEPDKGENNAND2X1(input A, input B, output Y ); assign Y = A & B;
module PureCSHA_4_3 (C, S, X, Y); output [5:4] C; output [4:3] S; input [4:3] X; input [4:3] Y; UBHA_3 U0 (C[4], S[3], X[3], Y[3]); UBHA_4 U1 (C[5], S[4], X[4], Y[4]); endmodule
module PDKGEPDKGENNOR2X1(input A, input B, output Y ); assign Y = A | B;
module UB1DCON_6(O, I); output O; input I; assign O = I; endmodule
module PDKGEPDKGENNOR2X1(input A, input B, output Y ); assign Y = A | B;
module glbl ();parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL;
module PDKGEPDKGENNAND2X1(input A, input B, output Y ); assign Y = A & B;
// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2003 by Wilson Snyder. module t (/*AUTOARG*/ // Inputs clk ); input clk; integer _mode; reg _guard1; reg [127:0] r_wide0; reg _guard2; wire [63:0] r_wide1; reg _guard3; reg _guard4; reg _guard5; reg _guard6; assign r_wide1 = r_wide0[127:64]; // surefire lint_off STMINI initial _mode = 0; always @ (posedge clk) begin if (_mode==0) begin $write("[%0t] t_equal: Running\n", $time); _guard1 <= 0; _guard2 <= 0; _guard3 <= 0; _guard4 <= 0; _guard5 <= 0; _guard6 <= 0; _mode<=1; r_wide0 <= {32'h aa111111,32'hbb222222,32'hcc333333,32'hdd444444}; end else if (_mode==1) begin _mode<=2; // if (5'd10 != 5'b1010) $stop; if (5'd10 != 5'd10) $stop; if (5'd10 != 5'ha) $stop; if (5'd10 != 5'o12) $stop; if (5'd10 != 5'B 1010) $stop; if (5'd10 != 5'D10) $stop; if (5'd10 != 5'H a) $stop; if (5'd10 != 5 'O 12) $stop; // if (r_wide0 !== {32'haa111111,32'hbb222222,32'hcc333333,32'hdd444444}) $stop; if (r_wide1 !== {32'haa111111,32'hbb222222}) $stop; if (|{_guard1,_guard2,_guard3,_guard4,_guard5,_guard6}) begin $write("Guard error %x %x %x %x %x\n",_guard1,_guard2,_guard3,_guard4,_guard5); $stop; end $write("*-* All Finished *-*\n"); $finish; end end endmodule
module UB1DCON_6(O, I); output O; input I; assign O = I; endmodule
`timescale 1ps / 1ps /***************************************************************************** Verilog RTL Description Configured at: 00:37:55 CST (+0800), Wednesday 05 May 2021 Configured on: ws28 Configured by: m109061634 (m109061634) Created by: Stratus DpOpt 2019.1.01 *******************************************************************************/ module DC_Filter_Add2i235Mul2i258Add2u1Mul2i3u2_4 ( in2, in1, out1 ); /* architecture "behavioural" */ input [1:0] in2; input in1; output [11:0] out1; wire [11:0] asc001; wire [3:0] asc002; wire [3:0] asc002_tmp_0; assign asc002_tmp_0 = +(4'B0011 * in2); assign asc002 = asc002_tmp_0 +(in1); wire [11:0] asc001_tmp_1; assign asc001_tmp_1 = +(12'B000100000010 * asc002); assign asc001 = asc001_tmp_1 +(12'B000011101011); assign out1 = asc001; endmodule /* CADENCE v7X2SQ0= : u9/ySgnWtBlWxVPRXgAZ4Og= ** DO NOT EDIT THIS LINE ******/
module glbl ();parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL;
`timescale 1ps / 1ps /***************************************************************************** Verilog RTL Description Configured at: 00:48:08 CST (+0800), Wednesday 05 May 2021 Configured on: ws28 Configured by: m109061634 (m109061634) Created by: Stratus DpOpt 2019.1.01 *******************************************************************************/ module DC_Filter_Add2i165Mul2i258Add2u1Mul2i3u2_1 ( in2, in1, out1 ); /* architecture "behavioural" */ input [1:0] in2; input in1; output [11:0] out1; wire [11:0] asc001; wire [3:0] asc002; wire [3:0] asc002_tmp_0; assign asc002_tmp_0 = +(4'B0011 * in2); assign asc002 = asc002_tmp_0 +(in1); wire [11:0] asc001_tmp_1; assign asc001_tmp_1 = +(12'B000100000010 * asc002); assign asc001 = asc001_tmp_1 +(12'B000010100101); assign out1 = asc001; endmodule /* CADENCE v7X4QwA= : u9/ySgnWtBlWxVPRXgAZ4Og= ** DO NOT EDIT THIS LINE ******/
`timescale 1ps / 1ps /***************************************************************************** Verilog RTL Description Configured at: 00:37:55 CST (+0800), Wednesday 05 May 2021 Configured on: ws28 Configured by: m109061634 (m109061634) Created by: Stratus DpOpt 2019.1.01 *******************************************************************************/ module DC_Filter_Add2i236Mul2i258Add2u1Mul2i3u2_4 ( in2, in1, out1 ); /* architecture "behavioural" */ input [1:0] in2; input in1; output [11:0] out1; wire [11:0] asc001; wire [3:0] asc002; wire [3:0] asc002_tmp_0; assign asc002_tmp_0 = +(4'B0011 * in2); assign asc002 = asc002_tmp_0 +(in1); wire [11:0] asc001_tmp_1; assign asc001_tmp_1 = +(12'B000100000010 * asc002); assign asc001 = asc001_tmp_1 +(12'B000011101100); assign out1 = asc001; endmodule /* CADENCE v7X1TQA= : u9/ySgnWtBlWxVPRXgAZ4Og= ** DO NOT EDIT THIS LINE ******/
module glbl ();parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL;
module glbl ();parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL;
// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2003 by Wilson Snyder. module t (/*AUTOARG*/ // Inputs clk ); input clk; integer _mode; reg _guard1; reg [127:0] r_wide0; reg _guard2; wire [63:0] r_wide1; reg _guard3; reg _guard4; reg _guard5; reg _guard6; assign r_wide1 = r_wide0[127:64]; // surefire lint_off STMINI initial _mode = 0; always @ (posedge clk) begin if (_mode==0) begin $write("[%0t] t_equal: Running\n", $time); _guard1 <= 0; _guard2 <= 0; _guard3 <= 0; _guard4 <= 0; _guard5 <= 0; _guard6 <= 0; _mode<=1; r_wide0 <= {32'h aa111111,32'hbb222222,32'hcc333333,32'hdd444444}; end else if (_mode==1) begin _mode<=2; // if (5'd10 != 5'b1010) $stop; if (5'd10 != 5'd10) $stop; if (5'd10 != 5'ha) $stop; if (5'd10 != 5'o12) $stop; if (5'd10 != 5'B 1010) $stop; if (5'd10 != 5'D10) $stop; if (5'd10 != 5'H a) $stop; if (5'd10 != 5 'O 12) $stop; // if (r_wide0 !== {32'haa111111,32'hbb222222,32'hcc333333,32'hdd444444}) $stop; if (r_wide1 !== {32'haa111111,32'hbb222222}) $stop; if (|{_guard1,_guard2,_guard3,_guard4,_guard5,_guard6}) begin $write("Guard error %x %x %x %x %x\n",_guard1,_guard2,_guard3,_guard4,_guard5); $stop; end $write("*-* All Finished *-*\n"); $finish; end end endmodule
//------------------------------------------------------------------------------ // (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. //------------------------------------------------------------------------------ // *************************** // * DO NOT MODIFY THIS FILE * // *************************** `timescale 1ps/1ps module gtwizard_ultrascale_v1_7_1_gthe4_cpll_cal # ( parameter integer C_RX_PLL_TYPE = 0, parameter integer C_TX_PLL_TYPE = 0, parameter C_SIM_CPLL_CAL_BYPASS = 1'b1, parameter SIM_RESET_SPEEDUP = "TRUE", parameter C_FREERUN_FREQUENCY = 100, parameter REVISION = 2, parameter C_PCIE_ENABLE = "FALSE", parameter C_PCIE_CORECLK_FREQ = 250 )( // control signals input wire [17:0] TXOUTCLK_PERIOD_IN, input wire [15:0] WAIT_DEASSERT_CPLLPD_IN, input wire [17:0] CNT_TOL_IN, input wire [15:0] FREQ_COUNT_WINDOW_IN, // User Interface input wire RESET_IN, input wire CLK_IN, input wire DRPRST_IN, input wire [1:0] USER_TXPLLCLKSEL, input wire [1:0] USER_RXPLLCLKSEL, input wire USER_RXPROGDIVRESET_IN, output wire USER_RXPRGDIVRESETDONE_OUT, output wire USER_RXPMARESETDONE_OUT, input wire [2:0] USER_RXOUTCLKSEL_IN, input wire USER_RXOUTCLK_BUFG_CE_IN, input wire USER_RXOUTCLK_BUFG_CLR_IN, input wire USER_GTRXRESET_IN, input wire USER_RXCDRHOLD_IN, input wire USER_RXPMARESET_IN, input wire USER_TXPROGDIVRESET_IN, output wire USER_TXPRGDIVRESETDONE_OUT, input wire [2:0] USER_TXOUTCLKSEL_IN, input wire USER_TXOUTCLK_BUFG_CE_IN, input wire USER_TXOUTCLK_BUFG_CLR_IN, output wire USER_CPLLLOCK_OUT, input wire [9:0] USER_CHANNEL_DRPADDR_IN, input wire [15:0] USER_CHANNEL_DRPDI_IN, input wire USER_CHANNEL_DRPEN_IN, input wire USER_CHANNEL_DRPWE_IN, output wire USER_CHANNEL_DRPRDY_OUT, output wire [15:0] USER_CHANNEL_DRPDO_OUT, // Debug Interface output wire CPLL_CAL_FAIL, output wire CPLL_CAL_DONE, output wire [15:0] DEBUG_OUT, output wire [17:0] CAL_FREQ_CNT, input [3:0] REPEAT_RESET_LIMIT, // GT Interface input wire GTHE4_TXOUTCLK_IN, input wire GTHE4_RXOUTCLK_IN, input wire GTHE4_CPLLLOCK_IN, output wire GTHE4_CPLLRESET_OUT, output wire GTHE4_RXCDRHOLD_OUT, output wire GTHE4_GTRXRESET_OUT, output wire GTHE4_RXPMARESET_OUT, output wire GTHE4_RXPROGDIVRESET_OUT, output wire [2:0] GTHE4_RXOUTCLKSEL_OUT, input wire GTHE4_RXPRGDIVRESETDONE_IN, input wire GTHE4_RXPMARESETDONE_IN, output wire GTHE4_CPLLPD_OUT, output wire GTHE4_TXPROGDIVRESET_OUT, output wire [2:0] GTHE4_TXOUTCLKSEL_OUT, input wire GTHE4_TXPRGDIVRESETDONE_IN, output wire [9:0] GTHE4_CHANNEL_DRPADDR_OUT, output wire [15:0] GTHE4_CHANNEL_DRPDI_OUT, output wire GTHE4_CHANNEL_DRPEN_OUT, output wire GTHE4_CHANNEL_DRPWE_OUT, input wire GTHE4_CHANNEL_DRPRDY_IN, input wire [15:0] GTHE4_CHANNEL_DRPDO_IN ); wire rx_done; wire tx_done; wire cal_on_rx_cal_fail; wire cal_on_rx_cal_done; wire [15:0] cal_on_rx_debug_out; wire [17:0] cal_on_rx_cal_freq_cnt; wire cal_on_rx_cpllreset_out; wire cal_on_rx_cpllpd_out; wire cal_on_rx_cplllock_out; wire cal_on_rx_drpen_out; wire cal_on_rx_drpwe_out; wire [9:0] cal_on_rx_drpaddr_out; wire [15:0] cal_on_rx_drpdi_out; wire [15:0] cal_on_rx_dout; wire cal_on_rx_drdy; wire cal_on_tx_cal_fail; wire cal_on_tx_cal_done; wire [15:0] cal_on_tx_debug_out; wire [17:0] cal_on_tx_cal_freq_cnt; wire cal_on_tx_cpllreset_out; wire cal_on_tx_cpllpd_out; wire cal_on_tx_cplllock_out; wire cal_on_tx_drpen_out; wire cal_on_tx_drpwe_out; wire [9:0] cal_on_tx_drpaddr_out; wire [15:0] cal_on_tx_drpdi_out; wire [15:0] cal_on_tx_dout; wire cal_on_tx_drdy; localparam [9:0] ADDR_TX_PROGCLK_SEL = 10'h00C; localparam [9:0] ADDR_TX_PROGDIV_CFG = 10'h03E; // GTH /GTY addresses are different (003E in GTH; 0057 in GTY) localparam [9:0] ADDR_RX_PROGDIV_CFG = 10'h0C6; localparam [9:0] ADDR_X0E1 = 10'h0E1; localparam [9:0] ADDR_X079 = 10'h079; localparam [9:0] ADDR_X114 = 10'h114; localparam CPLL_CAL_ONLY_TX = (C_RX_PLL_TYPE == C_TX_PLL_TYPE); // If top level configuration of TX and RX PLL TYPE are same, don't use RX Cal block wire cpll_cal_on_tx_or_rx; //1: RX cal block, 0: TX cal block; assign cpll_cal_on_tx_or_rx = CPLL_CAL_ONLY_TX ? 1'b0 : ((USER_TXPLLCLKSEL != 2'b00 && USER_RXPLLCLKSEL == 2'b00) ? 1'b1 : 1'b0); // TX reset version wire cal_on_tx_reset_in; assign cal_on_tx_reset_in = RESET_IN | cpll_cal_on_tx_or_rx; wire cal_on_tx_reset_in_sync; gtwizard_ultrascale_v1_7_1_reset_synchronizer reset_synchronizer_resetin_tx_inst ( .clk_in (CLK_IN), .rst_in (cal_on_tx_reset_in), .rst_out (cal_on_tx_reset_in_sync) ); // RX reset version wire cal_on_rx_reset_in; assign cal_on_rx_reset_in = RESET_IN | !cpll_cal_on_tx_or_rx; wire cal_on_rx_reset_in_sync; gtwizard_ultrascale_v1_7_1_reset_synchronizer reset_synchronizer_resetin_rx_inst ( .clk_in (CLK_IN), .rst_in (cal_on_rx_reset_in), .rst_out (cal_on_rx_reset_in_sync) ); wire drprst_in_sync; gtwizard_ultrascale_v1_7_1_bit_synchronizer bit_synchronizer_drprst_inst ( .clk_in (CLK_IN), .i_in (DRPRST_IN), .o_out (drprst_in_sync) ); gtwizard_ultrascale_v1_7_1_gthe4_cpll_cal_tx # ( .C_SIM_CPLL_CAL_BYPASS(C_SIM_CPLL_CAL_BYPASS), .SIM_RESET_SPEEDUP(SIM_RESET_SPEEDUP), .C_FREERUN_FREQUENCY(C_FREERUN_FREQUENCY), .C_PCIE_ENABLE(C_PCIE_ENABLE), .C_PCIE_CORECLK_FREQ(C_PCIE_CORECLK_FREQ) ) gtwizard_ultrascale_v1_7_1_gthe4_cpll_cal_tx_i ( // control signals .TXOUTCLK_PERIOD_IN(TXOUTCLK_PERIOD_IN), .WAIT_DEASSERT_CPLLPD_IN(WAIT_DEASSERT_CPLLPD_IN), .CNT_TOL_IN(CNT_TOL_IN), .FREQ_COUNT_WINDOW_IN(FREQ_COUNT_WINDOW_IN), // User Interface .RESET_IN(cal_on_tx_reset_in_sync), .CLK_IN(CLK_IN), .USER_TXPLLCLKSEL(USER_TXPLLCLKSEL), .USER_TXPROGDIVRESET_IN(USER_TXPROGDIVRESET_IN), .USER_TXPRGDIVRESETDONE_OUT(USER_TXPRGDIVRESETDONE_OUT), .USER_TXOUTCLKSEL_IN(USER_TXOUTCLKSEL_IN), .USER_TXOUTCLK_BUFG_CE_IN(USER_TXOUTCLK_BUFG_CE_IN), .USER_TXOUTCLK_BUFG_CLR_IN(USER_TXOUTCLK_BUFG_CLR_IN), .USER_CPLLLOCK_OUT(cal_on_tx_cplllock_out), // Debug Interface .CPLL_CAL_FAIL(cal_on_tx_cal_fail), .CPLL_CAL_DONE(cal_on_tx_cal_done), .DEBUG_OUT(cal_on_tx_debug_out), .CAL_FREQ_CNT(cal_on_tx_cal_freq_cnt), .REPEAT_RESET_LIMIT(REPEAT_RESET_LIMIT), // GT Interface .GTHE4_TXOUTCLK_IN(GTHE4_TXOUTCLK_IN), .GTHE4_CPLLLOCK_IN(GTHE4_CPLLLOCK_IN), .GTHE4_CPLLRESET_OUT(cal_on_tx_cpllreset_out), .GTHE4_CPLLPD_OUT(cal_on_tx_cpllpd_out), .GTHE4_TXPROGDIVRESET_OUT(GTHE4_TXPROGDIVRESET_OUT), .GTHE4_TXOUTCLKSEL_OUT(GTHE4_TXOUTCLKSEL_OUT), .GTHE4_TXPRGDIVRESETDONE_IN(GTHE4_TXPRGDIVRESETDONE_IN), .GTHE4_CHANNEL_DRPADDR_OUT(cal_on_tx_drpaddr_out), .GTHE4_CHANNEL_DRPDI_OUT(cal_on_tx_drpdi_out), .GTHE4_CHANNEL_DRPEN_OUT(cal_on_tx_drpen_out), .GTHE4_CHANNEL_DRPWE_OUT(cal_on_tx_drpwe_out), .GTHE4_CHANNEL_DRPRDY_IN(cal_on_tx_drdy), .GTHE4_CHANNEL_DRPDO_IN(cal_on_tx_dout), .DONE(tx_done) ); gtwizard_ultrascale_v1_7_1_gthe4_cpll_cal_rx # ( .C_SIM_CPLL_CAL_BYPASS(C_SIM_CPLL_CAL_BYPASS), .SIM_RESET_SPEEDUP(SIM_RESET_SPEEDUP), .CPLL_CAL_ONLY_TX(CPLL_CAL_ONLY_TX), .C_FREERUN_FREQUENCY(C_FREERUN_FREQUENCY) ) gtwizard_ultrascale_v1_7_1_gthe4_cpll_cal_rx_i ( // control signals .RXOUTCLK_PERIOD_IN(TXOUTCLK_PERIOD_IN), .WAIT_DEASSERT_CPLLPD_IN(WAIT_DEASSERT_CPLLPD_IN), .CNT_TOL_IN(CNT_TOL_IN), .FREQ_COUNT_WINDOW_IN(FREQ_COUNT_WINDOW_IN), // User Interface .RESET_IN(cal_on_rx_reset_in_sync), .CLK_IN(CLK_IN), .USER_RXPROGDIVRESET_IN(USER_RXPROGDIVRESET_IN), .USER_RXPRGDIVRESETDONE_OUT(USER_RXPRGDIVRESETDONE_OUT), .USER_RXPMARESETDONE_OUT(USER_RXPMARESETDONE_OUT), .USER_RXOUTCLKSEL_IN(USER_RXOUTCLKSEL_IN), .USER_RXOUTCLK_BUFG_CE_IN(USER_RXOUTCLK_BUFG_CE_IN), .USER_RXOUTCLK_BUFG_CLR_IN(USER_RXOUTCLK_BUFG_CLR_IN), .USER_CPLLLOCK_OUT(cal_on_rx_cplllock_out), .USER_RXCDRHOLD_IN(USER_RXCDRHOLD_IN), .USER_GTRXRESET_IN(USER_GTRXRESET_IN), .USER_RXPMARESET_IN(USER_RXPMARESET_IN), // Debug Interface .CPLL_CAL_FAIL(cal_on_rx_cal_fail), .CPLL_CAL_DONE(cal_on_rx_cal_done), .DEBUG_OUT(cal_on_rx_debug_out), .CAL_FREQ_CNT(cal_on_rx_cal_freq_cnt), .REPEAT_RESET_LIMIT(REPEAT_RESET_LIMIT), // GT Interface .GTHE4_RXOUTCLK_IN(GTHE4_RXOUTCLK_IN), .GTHE4_CPLLLOCK_IN(GTHE4_CPLLLOCK_IN), .GTHE4_CPLLRESET_OUT(cal_on_rx_cpllreset_out), .GTHE4_CPLLPD_OUT(cal_on_rx_cpllpd_out), .GTHE4_RXPROGDIVRESET_OUT(GTHE4_RXPROGDIVRESET_OUT), .GTHE4_RXOUTCLKSEL_OUT(GTHE4_RXOUTCLKSEL_OUT), .GTHE4_RXPRGDIVRESETDONE_IN(GTHE4_RXPRGDIVRESETDONE_IN), .GTHE4_CHANNEL_DRPADDR_OUT(cal_on_rx_drpaddr_out), .GTHE4_CHANNEL_DRPDI_OUT(cal_on_rx_drpdi_out), .GTHE4_CHANNEL_DRPEN_OUT(cal_on_rx_drpen_out), .GTHE4_CHANNEL_DRPWE_OUT(cal_on_rx_drpwe_out), .GTHE4_CHANNEL_DRPRDY_IN(cal_on_rx_drdy), .GTHE4_CHANNEL_DRPDO_IN(cal_on_rx_dout), .GTHE4_GTRXRESET_OUT(GTHE4_GTRXRESET_OUT), .GTHE4_RXPMARESET_OUT(GTHE4_RXPMARESET_OUT), .GTHE4_RXCDRHOLD_OUT(GTHE4_RXCDRHOLD_OUT), .GTHE4_RXPMARESETDONE_IN(GTHE4_RXPMARESETDONE_IN), .DONE(rx_done) ); //OR with TX versions assign GTHE4_CPLLRESET_OUT = cal_on_rx_cpllreset_out | cal_on_tx_cpllreset_out; assign GTHE4_CPLLPD_OUT = cal_on_rx_cpllpd_out | cal_on_tx_cpllpd_out; assign USER_CPLLLOCK_OUT = cal_on_rx_cplllock_out | cal_on_tx_cplllock_out; //Mux the debug signals out assign CPLL_CAL_DONE = cpll_cal_on_tx_or_rx ? cal_on_rx_cal_done : cal_on_tx_cal_done; assign CPLL_CAL_FAIL = cpll_cal_on_tx_or_rx ? cal_on_rx_cal_fail : cal_on_tx_cal_fail; assign DEBUG_OUT = cpll_cal_on_tx_or_rx ? cal_on_rx_debug_out : cal_on_tx_debug_out; assign CAL_FREQ_CNT = cpll_cal_on_tx_or_rx ? cal_on_rx_cal_freq_cnt : cal_on_tx_cal_freq_cnt; //---------------------------------------------------------------------------------------------- // DRP ARBITER //---------------------------------------------------------------------------------------------- gtwizard_ultrascale_v1_7_1_gte4_drp_arb # ( .ADDR_TX_PROGCLK_SEL(ADDR_TX_PROGCLK_SEL), .ADDR_TX_PROGDIV_CFG(ADDR_TX_PROGDIV_CFG), .ADDR_RX_PROGDIV_CFG(ADDR_RX_PROGDIV_CFG), .ADDR_X0E1(ADDR_X0E1), .ADDR_X079(ADDR_X079), .ADDR_X114(ADDR_X114), .C_NUM_CLIENTS(3), .C_ADDR_WIDTH(10), .C_DATA_WIDTH(16) ) gtwizard_ultrascale_v1_7_1_gte4_drp_arb_i ( .DCLK_I (CLK_IN), .RESET_I (drprst_in_sync), .DEN_USR_I ({cal_on_tx_drpen_out, cal_on_rx_drpen_out, USER_CHANNEL_DRPEN_IN}), .DWE_USR_I ({cal_on_tx_drpwe_out, cal_on_rx_drpwe_out, USER_CHANNEL_DRPWE_IN}), .DADDR_USR_I ({cal_on_tx_drpaddr_out, cal_on_rx_drpaddr_out, USER_CHANNEL_DRPADDR_IN}), .DI_USR_I ({cal_on_tx_drpdi_out, cal_on_rx_drpdi_out, USER_CHANNEL_DRPDI_IN}), .DO_USR_O ({cal_on_tx_dout, cal_on_rx_dout, USER_CHANNEL_DRPDO_OUT}), .DRDY_USR_O ({cal_on_tx_drdy, cal_on_rx_drdy, USER_CHANNEL_DRPRDY_OUT}), // arbitrated port .DEN_O (GTHE4_CHANNEL_DRPEN_OUT), .DWE_O (GTHE4_CHANNEL_DRPWE_OUT), .DADDR_O (GTHE4_CHANNEL_DRPADDR_OUT), .DI_O (GTHE4_CHANNEL_DRPDI_OUT), .DO_I (GTHE4_CHANNEL_DRPDO_IN), .DRDY_I (GTHE4_CHANNEL_DRPRDY_IN), .TX_CAL_DONE_I (tx_done), .RX_CAL_DONE_I (rx_done) ); endmodule //CPLL_CAL
// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2003 by Wilson Snyder. module t (/*AUTOARG*/ // Inputs clk ); input clk; integer _mode; reg _guard1; reg [127:0] r_wide0; reg _guard2; wire [63:0] r_wide1; reg _guard3; reg _guard4; reg _guard5; reg _guard6; assign r_wide1 = r_wide0[127:64]; // surefire lint_off STMINI initial _mode = 0; always @ (posedge clk) begin if (_mode==0) begin $write("[%0t] t_equal: Running\n", $time); _guard1 <= 0; _guard2 <= 0; _guard3 <= 0; _guard4 <= 0; _guard5 <= 0; _guard6 <= 0; _mode<=1; r_wide0 <= {32'h aa111111,32'hbb222222,32'hcc333333,32'hdd444444}; end else if (_mode==1) begin _mode<=2; // if (5'd10 != 5'b1010) $stop; if (5'd10 != 5'd10) $stop; if (5'd10 != 5'ha) $stop; if (5'd10 != 5'o12) $stop; if (5'd10 != 5'B 1010) $stop; if (5'd10 != 5'D10) $stop; if (5'd10 != 5'H a) $stop; if (5'd10 != 5 'O 12) $stop; // if (r_wide0 !== {32'haa111111,32'hbb222222,32'hcc333333,32'hdd444444}) $stop; if (r_wide1 !== {32'haa111111,32'hbb222222}) $stop; if (|{_guard1,_guard2,_guard3,_guard4,_guard5,_guard6}) begin $write("Guard error %x %x %x %x %x\n",_guard1,_guard2,_guard3,_guard4,_guard5); $stop; end $write("*-* All Finished *-*\n"); $finish; end end endmodule
module UB1DCON_6(O, I); output O; input I; assign O = I; endmodule
//------------------------------------------------------------------------------ // (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. //------------------------------------------------------------------------------ // *************************** // * DO NOT MODIFY THIS FILE * // *************************** `timescale 1ps/1ps module gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_freq_counter # ( parameter REVISION = 1 )( output reg [17:0] freq_cnt_o = 18'd0, output reg done_o, input wire rst_i, input wire [15:0] test_term_cnt_i, input wire ref_clk_i, input wire test_clk_i ); //**************************************************************************** // Local Parameters //**************************************************************************** localparam RESET_STATE = 0; localparam MEASURE_STATE = 1; localparam HOLD_STATE = 2; localparam UPDATE_STATE = 3; localparam DONE_STATE = 4; //**************************************************************************** // Local Signals //**************************************************************************** reg [17:0] testclk_cnt = 18'h00000; reg [15:0] refclk_cnt = 16'h0000; reg [3:0] testclk_div4 = 4'h1; wire testclk_rst; wire testclk_en; reg [5:0] hold_clk = 6'd0; reg [4:0] state = 5'd1; (* ASYNC_REG = "TRUE" *) reg tstclk_rst_dly1, tstclk_rst_dly2; (* ASYNC_REG = "TRUE" *) reg testclk_en_dly1, testclk_en_dly2; // // need to get testclk_rst into TESTCLK_I domain // always @(posedge test_clk_i) begin tstclk_rst_dly1 <= testclk_rst; tstclk_rst_dly2 <= tstclk_rst_dly1; end // // need to get testclk_en into TESTCLK_I domain // always @(posedge test_clk_i) begin testclk_en_dly1 <= testclk_en; testclk_en_dly2 <= testclk_en_dly1; end always @(posedge test_clk_i) begin if (tstclk_rst_dly2 == 1'b1) begin testclk_div4 <= 4'h1; end else begin testclk_div4 <= {testclk_div4[2:0], testclk_div4[3]}; end end wire testclk_rst_sync; gtwizard_ultrascale_v1_7_1_reset_synchronizer reset_synchronizer_testclk_rst_inst ( .clk_in (test_clk_i), .rst_in (testclk_rst), .rst_out (testclk_rst_sync) ); always @(posedge test_clk_i or posedge testclk_rst_sync) begin if (testclk_rst_sync == 1'b1) begin testclk_cnt <= 0; end else if (testclk_en_dly2 == 1'b1 && testclk_div4 == 4'h8) begin testclk_cnt <= testclk_cnt + 1; end end /* always @(posedge test_clk_i or posedge testclk_rst) begin if (testclk_rst == 1'b1) begin testclk_cnt <= 0; end else if (testclk_en_dly2 == 1'b1 && testclk_div4 == 4'h8) begin testclk_cnt <= testclk_cnt + 1; end end */ always @(posedge ref_clk_i or posedge rst_i) begin if (rst_i) done_o <= 1'b0; else done_o <= state[DONE_STATE]; end always @(posedge ref_clk_i or posedge rst_i) begin if (rst_i) begin state <= 0; state[RESET_STATE] <= 1'b1; end else begin state <= 0; case (1'b1) // synthesis parallel_case full_case state[RESET_STATE]: begin if (hold_clk == 6'h3F) state[MEASURE_STATE] <= 1'b1; else state[RESET_STATE] <= 1'b1; end state[MEASURE_STATE]: begin if (refclk_cnt == test_term_cnt_i) state[HOLD_STATE] <= 1'b1; else state[MEASURE_STATE] <= 1'b1; end state[HOLD_STATE]: begin if (hold_clk == 6'hF) state[UPDATE_STATE] <= 1'b1; else state[HOLD_STATE] <= 1'b1; end state[UPDATE_STATE]: begin freq_cnt_o <= testclk_cnt; state[DONE_STATE] <= 1'b1; end state[DONE_STATE]: begin state[DONE_STATE] <= 1'b1; end endcase end end assign testclk_rst = state[RESET_STATE]; assign testclk_en = state[MEASURE_STATE]; always @(posedge ref_clk_i) begin if (state[RESET_STATE] == 1'b1 || state[HOLD_STATE] == 1'b1) hold_clk <= hold_clk + 1; else hold_clk <= 0; end always @(posedge ref_clk_i) begin if (state[MEASURE_STATE] == 1'b1) refclk_cnt <= refclk_cnt + 1; else refclk_cnt <= 0; end endmodule
module PDKGEPDKGENNAND2X1(input A, input B, output Y ); assign Y = A & B;
module PDKGEPDKGENNAND2X1(input A, input B, output Y ); assign Y = A & B;
//***************************************************************************** // (c) Copyright 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // Description // This module instantiates the clock synchronization logic. It passes the // incoming signal through two flops to ensure metastability. // //***************************************************************************** `timescale 1ps / 1ps `default_nettype none (* DowngradeIPIdentifiedWarnings="yes" *) module axis_infrastructure_v1_1_0_clock_synchronizer # ( /////////////////////////////////////////////////////////////////////////////// // Parameter Definitions /////////////////////////////////////////////////////////////////////////////// parameter integer C_NUM_STAGES = 4 ) ( /////////////////////////////////////////////////////////////////////////////// // Port Declarations /////////////////////////////////////////////////////////////////////////////// input wire clk, input wire synch_in , output wire synch_out ); //////////////////////////////////////////////////////////////////////////////// // Local Parameters //////////////////////////////////////////////////////////////////////////////// localparam integer P_SYNCH_D_WIDTH = (C_NUM_STAGES > 0) ? C_NUM_STAGES : 1; //////////////////////////////////////////////////////////////////////////////// // Wires/Reg declarations //////////////////////////////////////////////////////////////////////////////// (* ASYNC_REG = "TRUE" *) reg [P_SYNCH_D_WIDTH-1:0] synch_d = 'b0; generate if (C_NUM_STAGES > 0) begin : gen_synchronizer genvar i; always @(posedge clk) begin synch_d[0] <= synch_in; end for (i = 1; i < C_NUM_STAGES ; i = i + 1) begin : gen_stage always @(posedge clk) begin synch_d[i] <= synch_d[i-1]; end end assign synch_out = synch_d[C_NUM_STAGES-1]; end else begin : gen_no_synchronizer assign synch_out = synch_in; end endgenerate endmodule `default_nettype wire
module UB1DCON_6(O, I); output O; input I; assign O = I; endmodule
// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2003 by Wilson Snyder. module t (/*AUTOARG*/ // Inputs clk ); input clk; integer _mode; reg _guard1; reg [127:0] r_wide0; reg _guard2; wire [63:0] r_wide1; reg _guard3; reg _guard4; reg _guard5; reg _guard6; assign r_wide1 = r_wide0[127:64]; // surefire lint_off STMINI initial _mode = 0; always @ (posedge clk) begin if (_mode==0) begin $write("[%0t] t_equal: Running\n", $time); _guard1 <= 0; _guard2 <= 0; _guard3 <= 0; _guard4 <= 0; _guard5 <= 0; _guard6 <= 0; _mode<=1; r_wide0 <= {32'h aa111111,32'hbb222222,32'hcc333333,32'hdd444444}; end else if (_mode==1) begin _mode<=2; // if (5'd10 != 5'b1010) $stop; if (5'd10 != 5'd10) $stop; if (5'd10 != 5'ha) $stop; if (5'd10 != 5'o12) $stop; if (5'd10 != 5'B 1010) $stop; if (5'd10 != 5'D10) $stop; if (5'd10 != 5'H a) $stop; if (5'd10 != 5 'O 12) $stop; // if (r_wide0 !== {32'haa111111,32'hbb222222,32'hcc333333,32'hdd444444}) $stop; if (r_wide1 !== {32'haa111111,32'hbb222222}) $stop; if (|{_guard1,_guard2,_guard3,_guard4,_guard5,_guard6}) begin $write("Guard error %x %x %x %x %x\n",_guard1,_guard2,_guard3,_guard4,_guard5); $stop; end $write("*-* All Finished *-*\n"); $finish; end end endmodule
`timescale 1ps / 1ps /***************************************************************************** Verilog RTL Description Configured at: 00:39:58 CST (+0800), Wednesday 05 May 2021 Configured on: ws28 Configured by: m109061634 (m109061634) Created by: Stratus DpOpt 2019.1.01 *******************************************************************************/ module DC_Filter_Add2i46Mul2i258Add2u1Mul2i3u2_4 ( in2, in1, out1 ); /* architecture "behavioural" */ input [1:0] in2; input in1; output [11:0] out1; wire [11:0] asc001; wire [3:0] asc002; wire [3:0] asc002_tmp_0; assign asc002_tmp_0 = +(4'B0011 * in2); assign asc002 = asc002_tmp_0 +(in1); wire [11:0] asc001_tmp_1; assign asc001_tmp_1 = +(12'B000100000010 * asc002); assign asc001 = asc001_tmp_1 +(12'B000000101110); assign out1 = asc001; endmodule /* CADENCE v7b0Qgk= : u9/ySgnWtBlWxVPRXgAZ4Og= ** DO NOT EDIT THIS LINE ******/
module PDKGEPDKGENNOR2X1(input A, input B, output Y ); assign Y = A | B;
`timescale 1ps / 1ps /***************************************************************************** Verilog RTL Description Configured at: 00:38:42 CST (+0800), Wednesday 05 May 2021 Configured on: ws28 Configured by: m109061634 (m109061634) Created by: Stratus DpOpt 2019.1.01 *******************************************************************************/ module DC_Filter_Add2i164Mul2i258Add2u1Mul2i3u2_4 ( in2, in1, out1 ); /* architecture "behavioural" */ input [1:0] in2; input in1; output [11:0] out1; wire [11:0] asc001; wire [3:0] asc002; wire [3:0] asc002_tmp_0; assign asc002_tmp_0 = +(4'B0011 * in2); assign asc002 = asc002_tmp_0 +(in1); wire [11:0] asc001_tmp_1; assign asc001_tmp_1 = +(12'B000100000010 * asc002); assign asc001 = asc001_tmp_1 +(12'B000010100100); assign out1 = asc001; endmodule /* CADENCE v7X5SQA= : u9/ySgnWtBlWxVPRXgAZ4Og= ** DO NOT EDIT THIS LINE ******/
`timescale 1ps / 1ps /***************************************************************************** Verilog RTL Description Configured at: 02:09:29 CST (+0800), Wednesday 05 May 2021 Configured on: ws28 Configured by: m109061634 (m109061634) Created by: Stratus DpOpt 2019.1.01 *******************************************************************************/ module DC_Filter_Add2i97Mul2i258Add2u1Mul2i3u2_1 ( in2, in1, out1 ); /* architecture "behavioural" */ input [1:0] in2; input in1; output [11:0] out1; wire [11:0] asc001; wire [3:0] asc002; wire [3:0] asc002_tmp_0; assign asc002_tmp_0 = +(4'B0011 * in2); assign asc002 = asc002_tmp_0 +(in1); wire [11:0] asc001_tmp_1; assign asc001_tmp_1 = +(12'B000100000010 * asc002); assign asc001 = asc001_tmp_1 +(12'B000001100001); assign out1 = asc001; endmodule /* CADENCE v7bzQww= : u9/ySgnWtBlWxVPRXgAZ4Og= ** DO NOT EDIT THIS LINE ******/
module PureCSHA_4_3 (C, S, X, Y); output [5:4] C; output [4:3] S; input [4:3] X; input [4:3] Y; UBHA_3 U0 (C[4], S[3], X[3], Y[3]); UBHA_4 U1 (C[5], S[4], X[4], Y[4]); endmodule
module FPAddSub_ExceptionModule( Z, NegE, R, S, InputExc, EOF, P, Flags );// Input ports input [`DWIDTH-1:0] Z ; // Final product input NegE ; // Negative exponent? input R ; // Round bit input S ; // Sticky bit input [4:0] InputExc ; // Exceptions in inputs A and B input EOF ; // Output ports output [`DWIDTH-1:0] P ; // Final result output [4:0] Flags ; // Exception flags
module PureCSHA_4_3 (C, S, X, Y); output [5:4] C; output [4:3] S; input [4:3] X; input [4:3] Y; UBHA_3 U0 (C[4], S[3], X[3], Y[3]); UBHA_4 U1 (C[5], S[4], X[4], Y[4]); endmodule
module PureCSHA_4_3 (C, S, X, Y); output [5:4] C; output [4:3] S; input [4:3] X; input [4:3] Y; UBHA_3 U0 (C[4], S[3], X[3], Y[3]); UBHA_4 U1 (C[5], S[4], X[4], Y[4]); endmodule
`timescale 1ps / 1ps /***************************************************************************** Verilog RTL Description Configured at: 02:07:20 CST (+0800), Wednesday 05 May 2021 Configured on: ws28 Configured by: m109061634 (m109061634) Created by: Stratus DpOpt 2019.1.01 *******************************************************************************/ module DC_Filter_Add2u9Mul2i258Add2i2Mul2i3u2_1 ( in2, in1, out1 ); /* architecture "behavioural" */ input [1:0] in2; input [8:0] in1; output [11:0] out1; wire [11:0] asc001; wire [3:0] asc002; wire [3:0] asc002_tmp_0; assign asc002_tmp_0 = +(4'B0011 * in2); assign asc002 = asc002_tmp_0 +(4'B0010); wire [11:0] asc001_tmp_1; assign asc001_tmp_1 = +(12'B000100000010 * asc002); assign asc001 = asc001_tmp_1 +(in1); assign out1 = asc001; endmodule /* CADENCE v7PwTAk= : u9/ySgnWtBlWxVPRXgAZ4Og= ** DO NOT EDIT THIS LINE ******/